BeRTOS
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00001 00040 #ifndef CPU_ATTR_H 00041 #define CPU_ATTR_H 00042 00043 #include "detect.h" 00044 00045 #include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */ 00046 #include "cfg/cfg_attr.h" /* CONFIG_FAST_MEM */ 00047 00048 00053 #define CPU_BIG_ENDIAN 0x1234 00054 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */ 00055 /*\}*/ 00056 00058 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h) 00059 00061 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c) 00062 00063 00064 #if CPU_I196 00065 00066 #define NOP nop_instruction() 00067 00068 #define CPU_REG_BITS 16 00069 #define CPU_REGS_CNT 16 00070 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00071 #define CPU_HARVARD 0 00072 00074 #define CPU_RAM_START 0x100 00075 00076 #elif CPU_X86 00077 00078 #define CPU_REGS_CNT 7 00079 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00080 #define CPU_HARVARD 0 00081 00082 #if CPU_X86_64 00083 #define CPU_REG_BITS 64 00084 00085 #ifdef __WIN64__ 00086 /* WIN64 is an IL32-P64 weirdo. */ 00087 #define SIZEOF_LONG 4 00088 #endif 00089 #else 00090 #define CPU_REG_BITS 32 00091 #endif 00092 00094 #define CPU_RAM_START 0x1000 00095 00096 #ifdef __GNUC__ 00097 #define NOP asm volatile ("nop") 00098 /* This is a good thing to insert into busy-wait loops. */ 00099 #define PAUSE asm volatile ("rep; nop" ::: "memory") 00100 #define BREAKPOINT asm volatile ("int3" ::) 00101 #endif 00102 00103 #elif CPU_ARM 00104 00105 #define CPU_REG_BITS 32 00106 #define CPU_REGS_CNT 16 00107 #define CPU_HARVARD 0 00108 00110 #if CPU_ARM_AT91 00111 #define CPU_RAM_START 0x00200000 00112 #elif CPU_ARM_LPC2 00113 #define CPU_RAM_START 0x40000000 00114 #else 00115 #warning Fix CPU_RAM_START address for your ARM, default value set to 0x200 00116 #define CPU_RAM_START 0x200 00117 #endif 00118 00119 #ifdef __IAR_SYSTEMS_ICC__ 00120 #warning Check CPU_BYTE_ORDER 00121 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN) 00122 00123 #define NOP __no_operation() 00124 00125 #else /* GCC and compatibles */ 00126 00127 #if defined(__ARMEB__) 00128 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN 00129 #elif defined(__ARMEL__) 00130 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00131 #else 00132 #error Unable to detect ARM endianness! 00133 #endif 00134 00135 #define NOP asm volatile ("mov r0,r0" ::) 00136 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */ 00137 00138 #if CONFIG_FAST_MEM 00139 00147 #define FAST_FUNC __attribute__((section(".ramfunc"))) 00148 00154 #define FAST_RODATA __attribute__((section(".data"))) 00155 00156 #else // !CONFIG_FAST_MEM 00157 #define FAST_RODATA 00158 #define FAST_FUNC 00159 #endif 00160 00161 /* 00162 * Function attribute to move it into ram memory. 00163 */ 00164 #define RAM_FUNC __attribute__((section(".ramfunc"))) 00165 00166 #endif /* !__IAR_SYSTEMS_ICC_ */ 00167 #elif CPU_CM3 00168 00169 #define CPU_REG_BITS 32 00170 #define CPU_REGS_CNT 16 00171 #define CPU_HARVARD 0 00172 00174 #if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3) 00175 #define CPU_RAM_START 0x20000000 00176 #else 00177 #warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000 00178 #define CPU_RAM_START 0x20000000 00179 #endif 00180 00181 #if defined( __ICCARM__) 00182 #if ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 0)) 00183 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN 00184 #elif ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 1)) 00185 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00186 #else 00187 #error Unable to detect Cortex-M3 endianess! 00188 #endif 00189 00190 #define NOP __no_operation() 00191 #else 00192 #if defined(__ARMEB__) // GCC 00193 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN 00194 #elif defined(__ARMEL__) // GCC 00195 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00196 #else 00197 #error Unable to detect Cortex-M3 endianess! 00198 #endif 00199 00200 #define NOP asm volatile ("nop") 00201 #define PAUSE asm volatile ("wfi" ::: "memory") 00202 #define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */ 00203 00204 /* 00205 * Function attribute to move it into ram memory. 00206 */ 00207 #define RAM_FUNC __attribute__((section(".ramfunc"))) 00208 #endif 00209 00210 #elif CPU_PPC 00211 00212 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64) 00213 #define CPU_REGS_CNT FIXME 00214 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN) 00215 #define CPU_HARVARD 0 00216 00218 #define CPU_RAM_START 0x1000 00219 00220 #ifdef __GNUC__ 00221 #define NOP asm volatile ("nop" ::) 00222 #define BREAKPOINT asm volatile ("twge 2,2" ::) 00223 #endif 00224 00225 #elif CPU_DSP56K 00226 00227 #define CPU_REG_BITS 16 00228 #define CPU_REGS_CNT FIXME 00229 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN 00230 #define CPU_HARVARD 1 00231 00232 /* Memory is word-addessed in the DSP56K */ 00233 #define CPU_BITS_PER_CHAR 16 00234 #define SIZEOF_SHORT 1 00235 #define SIZEOF_INT 1 00236 #define SIZEOF_LONG 2 00237 #define SIZEOF_PTR 1 00238 00240 #define CPU_RAM_START 0x200 00241 00242 #define NOP asm(nop) 00243 #define BREAKPOINT asm(debug) 00244 00245 #elif CPU_AVR 00246 00247 #define NOP asm volatile ("nop" ::) 00248 00249 #define CPU_REG_BITS 8 00250 #define CPU_REGS_CNT 33 /* Includes SREG */ 00251 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00252 #define CPU_HARVARD 1 00253 00255 #if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA103 00256 #define CPU_RAM_START 0x60 00257 #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P 00258 #define CPU_RAM_START 0x100 00259 #elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 00260 #define CPU_RAM_START 0x200 00261 #elif CPU_AVR_XMEGA_D 00262 #define CPU_RAM_START 0x2000 00263 #else 00264 #warning Fix CPU_RAM_START address for your AVR, default value set to 0x100 00265 #define CPU_RAM_START 0x100 00266 #endif 00267 00268 #elif CPU_MSP430 00269 00270 #define CPU_REG_BITS 16 00271 #define CPU_REGS_CNT 12 00272 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN 00273 #define CPU_HARVARD 0 00274 00276 #define CPU_RAM_START 0x200 00277 00278 #define NOP __asm__ __volatile__ ("nop") 00279 00280 #else 00281 #error No CPU_... defined. 00282 #endif 00283 00284 #ifndef BREAKPOINT 00285 #define BREAKPOINT /* nop */ 00286 #endif 00287 00288 #ifndef FAST_FUNC 00289 00290 #define FAST_FUNC /* */ 00291 #endif 00292 00293 #ifndef FAST_RODATA 00294 00295 #define FAST_RODATA /* */ 00296 #endif 00297 00298 #ifndef PAUSE 00299 00300 #define PAUSE do {NOP; MEMORY_BARRIER;} while (0) 00301 #endif 00302 00303 #endif /* CPU_ATTR_H */