BeRTOS
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00001 00036 #ifndef LM3S_MEMMAP_H 00037 #define LM3S_MEMMAP_H 00038 00043 /*\{*/ 00044 #define FLASH_BASE 0x00000000 //< FLASH memory 00045 #define SRAM_BASE 0x20000000 //< SRAM memory 00046 #define WATCHDOG0_BASE 0x40000000 //< Watchdog0 00047 #define WATCHDOG1_BASE 0x40001000 //< Watchdog1 00048 #define GPIO_PORTA_BASE 0x40004000 //< GPIO Port A 00049 #define GPIO_PORTB_BASE 0x40005000 //< GPIO Port B 00050 #define GPIO_PORTC_BASE 0x40006000 //< GPIO Port C 00051 #define GPIO_PORTD_BASE 0x40007000 //< GPIO Port D 00052 #define SSI0_BASE 0x40008000 //< SSI0 00053 #define SSI1_BASE 0x40009000 //< SSI1 00054 #define UART0_BASE 0x4000C000 //< UART0 00055 #define UART1_BASE 0x4000D000 //< UART1 00056 #define UART2_BASE 0x4000E000 //< UART2 00057 #define I2C0_MASTER_BASE 0x40020000 //< I2C0 Master 00058 #define I2C0_SLAVE_BASE 0x40020800 //< I2C0 Slave 00059 #define I2C1_MASTER_BASE 0x40021000 //< I2C1 Master 00060 #define I2C1_SLAVE_BASE 0x40021800 //< I2C1 Slave 00061 #define GPIO_PORTE_BASE 0x40024000 //< GPIO Port E 00062 #define GPIO_PORTF_BASE 0x40025000 //< GPIO Port F 00063 #define GPIO_PORTG_BASE 0x40026000 //< GPIO Port G 00064 #define GPIO_PORTH_BASE 0x40027000 //< GPIO Port H 00065 #define PWM_BASE 0x40028000 //< PWM 00066 #define QEI0_BASE 0x4002C000 //< QEI0 00067 #define QEI1_BASE 0x4002D000 //< QEI1 00068 #define TIMER0_BASE 0x40030000 //< Timer0 00069 #define TIMER1_BASE 0x40031000 //< Timer1 00070 #define TIMER2_BASE 0x40032000 //< Timer2 00071 #define TIMER3_BASE 0x40033000 //< Timer3 00072 #define ADC0_BASE 0x40038000 //< ADC0 00073 #define ADC1_BASE 0x40039000 //< ADC1 00074 #define COMP_BASE 0x4003C000 //< Analog comparators 00075 #define GPIO_PORTJ_BASE 0x4003D000 //< GPIO Port J 00076 #define CAN0_BASE 0x40040000 //< CAN0 00077 #define CAN1_BASE 0x40041000 //< CAN1 00078 #define CAN2_BASE 0x40042000 //< CAN2 00079 #define ETH_BASE 0x40048000 //< Ethernet 00080 #define MAC_BASE 0x40048000 //< Ethernet 00081 #define USB0_BASE 0x40050000 //< USB 0 Controller 00082 #define I2S0_BASE 0x40054000 //< I2S0 00083 #define GPIO_PORTA_AHB_BASE 0x40058000 //< GPIO Port A (high speed) 00084 #define GPIO_PORTB_AHB_BASE 0x40059000 //< GPIO Port B (high speed) 00085 #define GPIO_PORTC_AHB_BASE 0x4005A000 //< GPIO Port C (high speed) 00086 #define GPIO_PORTD_AHB_BASE 0x4005B000 //< GPIO Port D (high speed) 00087 #define GPIO_PORTE_AHB_BASE 0x4005C000 //< GPIO Port E (high speed) 00088 #define GPIO_PORTF_AHB_BASE 0x4005D000 //< GPIO Port F (high speed) 00089 #define GPIO_PORTG_AHB_BASE 0x4005E000 //< GPIO Port G (high speed) 00090 #define GPIO_PORTH_AHB_BASE 0x4005F000 //< GPIO Port H (high speed) 00091 #define GPIO_PORTJ_AHB_BASE 0x40060000 //< GPIO Port J (high speed) 00092 #define EPI0_BASE 0x400D0000 //< EPI0 00093 #define HIB_BASE 0x400FC000 //< Hibernation Module 00094 #define FLASH_CTRL_BASE 0x400FD000 //< FLASH Controller 00095 #define SYSCTL_BASE 0x400FE000 //< System Control 00096 #define UDMA_BASE 0x400FF000 //< uDMA Controller 00097 #define ITM_BASE 0xE0000000 //< Instrumentation Trace Macrocell 00098 #define DWT_BASE 0xE0001000 //< Data Watchpoint and Trace 00099 #define FPB_BASE 0xE0002000 //< FLASH Patch and Breakpoint 00100 #define NVIC_BASE 0xE000E000 //< Nested Vectored Interrupt Ctrl 00101 #define TPIU_BASE 0xE0040000 //< Trace Port Interface Unit 00102 /*\}*/ 00103 00107 /*\{*/ 00108 #ifndef DEPRECATED 00109 /*\}*/ 00110 00111 #define WATCHDOG_BASE 0x40000000 //< Watchdog 00112 #define SSI_BASE 0x40008000 //< SSI 00113 #define I2C_MASTER_BASE 0x40020000 //< I2C Master 00114 #define I2C_SLAVE_BASE 0x40020800 //< I2C Slave 00115 #define QEI_BASE 0x4002C000 //< QEI 00116 #define ADC_BASE 0x40038000 //< ADC 00117 00118 #endif /* DEPRECATED */ 00119 00120 #endif /* LM3S_MEMMAP_H */