BeRTOS
ser_mega.c
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00001 
00041 #include "hw/hw_ser.h"  /* Required for bus macros overrides */
00042 #include <hw/hw_cpufreq.h>  /* CPU_FREQ */
00043 
00044 #include "cfg/cfg_ser.h"
00045 
00046 #include <cfg/macros.h> /* DIV_ROUND */
00047 #include <cfg/debug.h>
00048 #include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
00049 
00050 #include <drv/ser.h>
00051 #include <drv/ser_p.h>
00052 #include <drv/timer.h>
00053 
00054 #include <struct/fifobuf.h>
00055 
00056 #include <avr/io.h>
00057 
00058 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
00059     #include <avr/interrupt.h>
00060 #else
00061     #include <avr/signal.h>
00062 #endif
00063 
00064 
00065 #if !CONFIG_SER_HWHANDSHAKE
00066 
00070     #define RTS_ON      do {} while (0)
00071     #define RTS_OFF     do {} while (0)
00072     #define IS_CTS_ON   true
00073     #define EIMSKF_CTS  0 
00074     /*\}*/
00075 #endif
00076 
00077 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00078     #define BIT_RXCIE0 RXCIE0
00079     #define BIT_RXEN0  RXEN0
00080     #define BIT_TXEN0  TXEN0
00081     #define BIT_UDRIE0 UDRIE0
00082 
00083     #define BIT_RXCIE1 RXCIE1
00084     #define BIT_RXEN1  RXEN1
00085     #define BIT_TXEN1  TXEN1
00086     #define BIT_UDRIE1 UDRIE1
00087     #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00088         #define BIT_RXCIE2 RXCIE2
00089         #define BIT_RXEN2  RXEN2
00090         #define BIT_TXEN2  TXEN2
00091         #define BIT_UDRIE2 UDRIE2
00092 
00093         #define BIT_RXCIE3 RXCIE3
00094         #define BIT_RXEN3  RXEN3
00095         #define BIT_TXEN3  TXEN3
00096         #define BIT_UDRIE3 UDRIE3
00097     #endif
00098 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
00099     #define BIT_RXCIE0 RXCIE0
00100     #define BIT_RXEN0  RXEN0
00101     #define BIT_TXEN0  TXEN0
00102     #define BIT_UDRIE0 UDRIE0
00103 
00104     #define BIT_RXCIE1 RXCIE0
00105     #define BIT_RXEN1  RXEN0
00106     #define BIT_TXEN1  TXEN0
00107     #define BIT_UDRIE1 UDRIE0
00108 #else
00109     #define BIT_RXCIE0 RXCIE
00110     #define BIT_RXEN0  RXEN
00111     #define BIT_TXEN0  TXEN
00112     #define BIT_UDRIE0 UDRIE
00113 
00114     #define BIT_RXCIE1 RXCIE
00115     #define BIT_RXEN1  RXEN
00116     #define BIT_TXEN1  TXEN
00117     #define BIT_UDRIE1 UDRIE
00118 #endif
00119 
00120 
00141 #ifndef SER_UART0_BUS_TXINIT
00142 
00148     #define SER_UART0_BUS_TXINIT do { \
00149         UCSR0A = 0; /* The Arduino Uno bootloader turns on U2X0 */ \
00150         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00151     } while (0)
00152 #endif
00153 
00154 #ifndef SER_UART0_BUS_TXBEGIN
00155 
00161     #define SER_UART0_BUS_TXBEGIN do { \
00162         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00163     } while (0)
00164 #endif
00165 
00166 #ifndef SER_UART0_BUS_TXCHAR
00167 
00170     #define SER_UART0_BUS_TXCHAR(c) do { \
00171         UDR0 = (c); \
00172     } while (0)
00173 #endif
00174 
00175 #ifndef SER_UART0_BUS_TXEND
00176 
00183     #define SER_UART0_BUS_TXEND do { \
00184         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
00185     } while (0)
00186 #endif
00187 
00188 #ifndef SER_UART0_BUS_TXOFF
00189 
00196     #ifdef __doxygen__
00197     #define SER_UART0_BUS_TXOFF
00198     #endif
00199 #endif
00200 
00201 #ifndef SER_UART1_BUS_TXINIT
00202 
00203     #define SER_UART1_BUS_TXINIT do { \
00204         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00205     } while (0)
00206 #endif
00207 #ifndef SER_UART1_BUS_TXBEGIN
00208 
00209     #define SER_UART1_BUS_TXBEGIN do { \
00210         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00211     } while (0)
00212 #endif
00213 #ifndef SER_UART1_BUS_TXCHAR
00214 
00215     #define SER_UART1_BUS_TXCHAR(c) do { \
00216         UDR1 = (c); \
00217     } while (0)
00218 #endif
00219 #ifndef SER_UART1_BUS_TXEND
00220 
00221     #define SER_UART1_BUS_TXEND do { \
00222         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
00223     } while (0)
00224 #endif
00225 #ifndef SER_UART1_BUS_TXOFF
00226 
00231     #ifdef __doxygen__
00232     #define SER_UART1_BUS_TXOFF
00233     #endif
00234 #endif
00235 
00236 #ifndef SER_UART2_BUS_TXINIT
00237 
00238     #define SER_UART2_BUS_TXINIT do { \
00239         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00240     } while (0)
00241 #endif
00242 #ifndef SER_UART2_BUS_TXBEGIN
00243 
00244     #define SER_UART2_BUS_TXBEGIN do { \
00245         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00246     } while (0)
00247 #endif
00248 #ifndef SER_UART2_BUS_TXCHAR
00249 
00250     #define SER_UART2_BUS_TXCHAR(c) do { \
00251         UDR2 = (c); \
00252     } while (0)
00253 #endif
00254 #ifndef SER_UART2_BUS_TXEND
00255 
00256     #define SER_UART2_BUS_TXEND do { \
00257         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
00258     } while (0)
00259 #endif
00260 #ifndef SER_UART2_BUS_TXOFF
00261 
00266     #ifdef __doxygen__
00267     #define SER_UART2_BUS_TXOFF
00268     #endif
00269 #endif
00270 
00271 #ifndef SER_UART3_BUS_TXINIT
00272 
00273     #define SER_UART3_BUS_TXINIT do { \
00274         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00275     } while (0)
00276 #endif
00277 #ifndef SER_UART3_BUS_TXBEGIN
00278 
00279     #define SER_UART3_BUS_TXBEGIN do { \
00280         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00281     } while (0)
00282 #endif
00283 #ifndef SER_UART3_BUS_TXCHAR
00284 
00285     #define SER_UART3_BUS_TXCHAR(c) do { \
00286         UDR3 = (c); \
00287     } while (0)
00288 #endif
00289 #ifndef SER_UART3_BUS_TXEND
00290 
00291     #define SER_UART3_BUS_TXEND do { \
00292         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
00293     } while (0)
00294 #endif
00295 #ifndef SER_UART3_BUS_TXOFF
00296 
00301     #ifdef __doxygen__
00302     #define SER_UART3_BUS_TXOFF
00303     #endif
00304 #endif
00305 /*\}*/
00306 
00307 
00316 #ifndef SER_SPI_BUS_TXINIT
00317 
00321     #define SER_SPI_BUS_TXINIT
00322 #endif
00323 
00324 #ifndef SER_SPI_BUS_TXCLOSE
00325 
00329     #define SER_SPI_BUS_TXCLOSE
00330 #endif
00331 /*\}*/
00332 
00333 
00334 /* SPI port and pin configuration */
00335 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
00336     || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00337     #define SPI_PORT      PORTB
00338     #define SPI_DDR       DDRB
00339     #define SPI_SS_BIT    PB0
00340     #define SPI_SCK_BIT   PB1
00341     #define SPI_MOSI_BIT  PB2
00342     #define SPI_MISO_BIT  PB3
00343 // TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
00344 // They should be the same!
00345 #elif CPU_AVR_ATMEGA328P
00346     #define SPI_PORT      PORTB
00347     #define SPI_DDR       DDRB
00348     #define SPI_SS_BIT    PORTB2
00349     #define SPI_SCK_BIT   PORTB5
00350     #define SPI_MOSI_BIT  PORTB3
00351     #define SPI_MISO_BIT  PORTB4
00352 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
00353     #define SPI_PORT      PORTB
00354     #define SPI_DDR       DDRB
00355     #define SPI_SS_BIT    PB2
00356     #define SPI_SCK_BIT   PB5
00357     #define SPI_MOSI_BIT  PB3
00358     #define SPI_MISO_BIT  PB4
00359 #elif CPU_AVR_ATMEGA32
00360     #define SPI_PORT      PORTB
00361     #define SPI_DDR       DDRB
00362     #define SPI_SS_BIT    PB4
00363     #define SPI_SCK_BIT   PB7
00364     #define SPI_MOSI_BIT  PB5
00365     #define SPI_MISO_BIT  PB6
00366 #else
00367     #error Unknown architecture
00368 #endif
00369 
00370 /* USART register definitions */
00371 #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
00372     #define AVR_HAS_UART1 1
00373     #define AVR_HAS_UART2 1
00374     #define AVR_HAS_UART3 1
00375 #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
00376     #define AVR_HAS_UART1 1
00377     #define AVR_HAS_UART2 0
00378     #define AVR_HAS_UART3 0
00379 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
00380     #define AVR_HAS_UART1 0
00381     #define AVR_HAS_UART2 0
00382     #define AVR_HAS_UART3 0
00383     #define USART0_UDRE_vect USART_UDRE_vect
00384     #define USART0_RX_vect USART_RX_vect
00385     #define USART0_TX_vect USART_TX_vect
00386 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
00387     #define AVR_HAS_UART1 0
00388     #define AVR_HAS_UART2 0
00389     #define AVR_HAS_UART3 0
00390     #define UCSR0A UCSRA
00391     #define UCSR0B UCSRB
00392     #define UCSR0C UCSRC
00393     #define UDR0   UDR
00394     #define UBRR0L UBRRL
00395     #define UBRR0H UBRRH
00396     #define UPM01  UPM1
00397     #define UPM00  UPM0
00398     #define USART0_UDRE_vect USART_UDRE_vect
00399     #define USART0_RX_vect USART_RXC_vect
00400     #define USART0_TX_vect USART_TXC_vect
00401 #elif CPU_AVR_ATMEGA103
00402     #define AVR_HAS_UART1 0
00403     #define AVR_HAS_UART2 0
00404     #define AVR_HAS_UART3 0
00405     #define UCSR0B UCR
00406     #define UDR0   UDR
00407     #define UCSR0A USR
00408     #define UBRR0L UBRR
00409     #define USART0_UDRE_vect USART_UDRE_vect
00410     #define USART0_RX_vect USART_RX_vect
00411     #define USART0_TX_vect USART_TX_vect
00412 #else
00413     #error Unknown architecture
00414 #endif
00415 
00416 
00417 /* From the high-level serial driver */
00418 extern struct Serial *ser_handles[SER_CNT];
00419 
00420 /* TX and RX buffers */
00421 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
00422 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
00423 #if AVR_HAS_UART1
00424     static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
00425     static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
00426 #endif
00427 #if AVR_HAS_UART2
00428     static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
00429     static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
00430 #endif
00431 #if AVR_HAS_UART3
00432     static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
00433     static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
00434 #endif
00435 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
00436 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
00437 
00438 
00455 struct AvrSerial
00456 {
00457     struct SerialHardware hw;
00458     volatile bool sending;
00459 };
00460 
00461 static uint16_t uart_period(unsigned long bps)
00462 {
00463     uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, bps) - 1;
00464 
00465     #ifdef _DEBUG
00466         long skew = bps - (long)(period + 1) * (CPU_FREQ / 16);
00467         /* 8N1 is reliable within 3% skew */
00468         if ((unsigned long)ABS(skew) > bps / (100 / 3))
00469             kprintf("Baudrate off by %ldbps\n", skew);
00470     #endif
00471 
00472     //DB(kprintf("uart_period(bps=%lu): period=%u\n", bps, period);)
00473     return period;
00474 }
00475 
00476 /*
00477  * Callbacks
00478  */
00479 static void uart0_init(
00480     UNUSED_ARG(struct SerialHardware *, _hw),
00481     UNUSED_ARG(struct Serial *, ser))
00482 {
00483     SER_UART0_BUS_TXINIT;
00484     RTS_ON;
00485     SER_STROBE_INIT;
00486 }
00487 
00488 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00489 {
00490     UCSR0B = 0;
00491 }
00492 
00493 static void uart0_enabletxirq(struct SerialHardware *_hw)
00494 {
00495     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00496 
00497     /*
00498      * WARNING: racy code here!  The tx interrupt sets hw->sending to false
00499      * when it runs with an empty fifo.  The order of statements in the
00500      * if-block matters.
00501      */
00502     if (!hw->sending)
00503     {
00504         hw->sending = true;
00505         SER_UART0_BUS_TXBEGIN;
00506     }
00507 }
00508 
00509 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00510 {
00511     uint16_t period = uart_period(rate);
00512 
00513 #if !CPU_AVR_ATMEGA103
00514     UBRR0H = period >> 8;
00515 #endif
00516     UBRR0L = period;
00517 }
00518 
00519 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00520 {
00521 #if !CPU_AVR_ATMEGA103
00522     UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
00523 #endif
00524 }
00525 
00526 #if AVR_HAS_UART1
00527 
00528 static void uart1_init(
00529     UNUSED_ARG(struct SerialHardware *, _hw),
00530     UNUSED_ARG(struct Serial *, ser))
00531 {
00532     SER_UART1_BUS_TXINIT;
00533     RTS_ON;
00534     SER_STROBE_INIT;
00535 }
00536 
00537 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00538 {
00539     UCSR1B = 0;
00540 }
00541 
00542 static void uart1_enabletxirq(struct SerialHardware *_hw)
00543 {
00544     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00545 
00546     /*
00547      * WARNING: racy code here!  The tx interrupt
00548      * sets hw->sending to false when it runs with
00549      * an empty fifo.  The order of the statements
00550      * in the if-block matters.
00551      */
00552     if (!hw->sending)
00553     {
00554         hw->sending = true;
00555         SER_UART1_BUS_TXBEGIN;
00556     }
00557 }
00558 
00559 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00560 {
00561     uint16_t period = uart_period(rate);
00562     UBRR1H = period >> 8;
00563     UBRR1L = period;
00564 }
00565 
00566 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00567 {
00568     UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
00569 }
00570 
00571 #endif // AVR_HAS_UART1
00572 
00573 #if AVR_HAS_UART2
00574 
00575 static void uart2_init(
00576     UNUSED_ARG(struct SerialHardware *, _hw),
00577     UNUSED_ARG(struct Serial *, ser))
00578 {
00579     SER_UART2_BUS_TXINIT;
00580     RTS_ON;
00581     SER_STROBE_INIT;
00582 }
00583 
00584 static void uart2_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00585 {
00586     UCSR2B = 0;
00587 }
00588 
00589 static void uart2_enabletxirq(struct SerialHardware *_hw)
00590 {
00591     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00592 
00593     /*
00594      * WARNING: racy code here!  The tx interrupt
00595      * sets hw->sending to false when it runs with
00596      * an empty fifo.  The order of the statements
00597      * in the if-block matters.
00598      */
00599     if (!hw->sending)
00600     {
00601         hw->sending = true;
00602         SER_UART2_BUS_TXBEGIN;
00603     }
00604 }
00605 
00606 static void uart2_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00607 {
00608     uint16_t period = uart_period(rate);
00609     UBRR2H = period >> 8;
00610     UBRR2L = period;
00611 }
00612 
00613 static void uart2_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00614 {
00615     UCSR2C = (UCSR2C & ~(BV(UPM21) | BV(UPM20))) | ((parity) << UPM20);
00616 }
00617 
00618 #endif // AVR_HAS_UART2
00619 
00620 #if AVR_HAS_UART3
00621 
00622 static void uart3_init(
00623     UNUSED_ARG(struct SerialHardware *, _hw),
00624     UNUSED_ARG(struct Serial *, ser))
00625 {
00626     SER_UART3_BUS_TXINIT;
00627     RTS_ON;
00628     SER_STROBE_INIT;
00629 }
00630 
00631 static void uart3_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00632 {
00633     UCSR3B = 0;
00634 }
00635 
00636 static void uart3_enabletxirq(struct SerialHardware *_hw)
00637 {
00638     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00639 
00640     /*
00641      * WARNING: racy code here!  The tx interrupt
00642      * sets hw->sending to false when it runs with
00643      * an empty fifo.  The order of the statements
00644      * in the if-block matters.
00645      */
00646     if (!hw->sending)
00647     {
00648         hw->sending = true;
00649         SER_UART3_BUS_TXBEGIN;
00650     }
00651 }
00652 
00653 static void uart3_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
00654 {
00655     uint16_t period = uart_period(rate);
00656     UBRR3H = period >> 8;
00657     UBRR3L = period;
00658 }
00659 
00660 static void uart3_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
00661 {
00662     UCSR3C = (UCSR3C & ~(BV(UPM31) | BV(UPM30))) | ((parity) << UPM30);
00663 }
00664 
00665 #endif // AVR_HAS_UART3
00666 
00667 
00668 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
00669 {
00670     /*
00671      * Set MOSI and SCK ports out, MISO in.
00672      *
00673      * The ATmega64/128 datasheet explicitly states that the input/output
00674      * state of the SPI pins is not significant, as when the SPI is
00675      * active the I/O port are overrided.
00676      * This is *blatantly FALSE*.
00677      *
00678      * Moreover, the MISO pin on the board_kc *must* be in high impedance
00679      * state even when the SPI is off, because the line is wired together
00680      * with the KBus serial RX, and the transmitter of the slave boards
00681      * would be unable to drive the line.
00682      */
00683     ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
00684 
00685     /*
00686      * If the SPI master mode is activated and the SS pin is in input and tied low,
00687      * the SPI hardware will automatically switch to slave mode!
00688      * For proper communication this pins should therefore be:
00689      * - as output
00690      * - as input but tied high forever!
00691      * This driver set the pin as output.
00692      */
00693     #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
00694     ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
00695 
00696     ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
00697     /* Enable SPI, IRQ on, Master */
00698     SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
00699 
00700     /* Set data order */
00701     #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
00702         SPCR |= BV(DORD);
00703     #endif
00704 
00705     /* Set SPI clock rate */
00706     #if CONFIG_SPI_CLOCK_DIV == 128
00707         SPCR |= (BV(SPR1) | BV(SPR0));
00708     #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
00709         SPCR |= BV(SPR1);
00710     #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
00711         SPCR |= BV(SPR0);
00712     #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
00713         // SPR0 & SDPR1 both at 0
00714     #else
00715         #error Unsupported SPI clock division factor.
00716     #endif
00717 
00718     /* Set SPI2X bit (spi double frequency) */
00719     #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
00720       || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
00721         SPSR &= ~BV(SPI2X);
00722     #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
00723         SPSR |= BV(SPI2X);
00724     #else
00725         #error Unsupported SPI clock division factor.
00726     #endif
00727 
00728     /* Set clock polarity */
00729     #if CONFIG_SPI_CLOCK_POL == 1
00730         SPCR |= BV(CPOL);
00731     #endif
00732 
00733     /* Set clock phase */
00734     #if CONFIG_SPI_CLOCK_PHASE == 1
00735         SPCR |= BV(CPHA);
00736     #endif
00737     SER_SPI_BUS_TXINIT;
00738 
00739     SER_STROBE_INIT;
00740 }
00741 
00742 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
00743 {
00744     SPCR = 0;
00745 
00746     SER_SPI_BUS_TXCLOSE;
00747 
00748     /* Set all pins as inputs */
00749     ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
00750 }
00751 
00752 static void spi_starttx(struct SerialHardware *_hw)
00753 {
00754     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00755 
00756     cpu_flags_t flags;
00757     IRQ_SAVE_DISABLE(flags);
00758 
00759     /* Send data only if the SPI is not already transmitting */
00760     if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
00761     {
00762         hw->sending = true;
00763         SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
00764     }
00765 
00766     IRQ_RESTORE(flags);
00767 }
00768 
00769 static void spi_setbaudrate(
00770     UNUSED_ARG(struct SerialHardware *, _hw),
00771     UNUSED_ARG(unsigned long, rate))
00772 {
00773     // nop
00774 }
00775 
00776 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
00777 {
00778     // nop
00779 }
00780 
00781 static bool tx_sending(struct SerialHardware* _hw)
00782 {
00783     struct AvrSerial *hw = (struct AvrSerial *)_hw;
00784     return hw->sending;
00785 }
00786 
00787 
00788 
00789 // FIXME: move into compiler.h?  Ditch?
00790 #if COMPILER_C99
00791     #define C99INIT(name,val) .name = val
00792 #elif defined(__GNUC__)
00793     #define C99INIT(name,val) name: val
00794 #else
00795     #warning No designated initializers, double check your code
00796     #define C99INIT(name,val) (val)
00797 #endif
00798 
00799 /*
00800  * High-level interface data structures
00801  */
00802 static const struct SerialHardwareVT UART0_VT =
00803 {
00804     C99INIT(init, uart0_init),
00805     C99INIT(cleanup, uart0_cleanup),
00806     C99INIT(setBaudrate, uart0_setbaudrate),
00807     C99INIT(setParity, uart0_setparity),
00808     C99INIT(txStart, uart0_enabletxirq),
00809     C99INIT(txSending, tx_sending),
00810 };
00811 
00812 #if AVR_HAS_UART1
00813 static const struct SerialHardwareVT UART1_VT =
00814 {
00815     C99INIT(init, uart1_init),
00816     C99INIT(cleanup, uart1_cleanup),
00817     C99INIT(setBaudrate, uart1_setbaudrate),
00818     C99INIT(setParity, uart1_setparity),
00819     C99INIT(txStart, uart1_enabletxirq),
00820     C99INIT(txSending, tx_sending),
00821 };
00822 #endif // AVR_HAS_UART1
00823 
00824 #if AVR_HAS_UART2
00825 static const struct SerialHardwareVT UART2_VT =
00826 {
00827     C99INIT(init, uart2_init),
00828     C99INIT(cleanup, uart2_cleanup),
00829     C99INIT(setBaudrate, uart2_setbaudrate),
00830     C99INIT(setParity, uart2_setparity),
00831     C99INIT(txStart, uart2_enabletxirq),
00832     C99INIT(txSending, tx_sending),
00833 };
00834 #endif // AVR_HAS_UART2
00835 
00836 #if AVR_HAS_UART3
00837 static const struct SerialHardwareVT UART3_VT =
00838 {
00839     C99INIT(init, uart3_init),
00840     C99INIT(cleanup, uart3_cleanup),
00841     C99INIT(setBaudrate, uart3_setbaudrate),
00842     C99INIT(setParity, uart3_setparity),
00843     C99INIT(txStart, uart3_enabletxirq),
00844     C99INIT(txSending, tx_sending),
00845 };
00846 #endif // AVR_HAS_UART3
00847 
00848 static const struct SerialHardwareVT SPI_VT =
00849 {
00850     C99INIT(init, spi_init),
00851     C99INIT(cleanup, spi_cleanup),
00852     C99INIT(setBaudrate, spi_setbaudrate),
00853     C99INIT(setParity, spi_setparity),
00854     C99INIT(txStart, spi_starttx),
00855     C99INIT(txSending, tx_sending),
00856 };
00857 
00858 static struct AvrSerial UARTDescs[SER_CNT] =
00859 {
00860     {
00861         C99INIT(hw, ) {
00862             C99INIT(table, &UART0_VT),
00863             C99INIT(txbuffer, uart0_txbuffer),
00864             C99INIT(rxbuffer, uart0_rxbuffer),
00865             C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
00866             C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
00867         },
00868         C99INIT(sending, false),
00869     },
00870 #if AVR_HAS_UART1
00871     {
00872         C99INIT(hw, ) {
00873             C99INIT(table, &UART1_VT),
00874             C99INIT(txbuffer, uart1_txbuffer),
00875             C99INIT(rxbuffer, uart1_rxbuffer),
00876             C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
00877             C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
00878         },
00879         C99INIT(sending, false),
00880     },
00881 #endif
00882 #if AVR_HAS_UART2
00883     {
00884         C99INIT(hw, ) {
00885             C99INIT(table, &UART2_VT),
00886             C99INIT(txbuffer, uart2_txbuffer),
00887             C99INIT(rxbuffer, uart2_rxbuffer),
00888             C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
00889             C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
00890         },
00891         C99INIT(sending, false),
00892     },
00893 #endif
00894 #if AVR_HAS_UART3
00895     {
00896         C99INIT(hw, ) {
00897             C99INIT(table, &UART3_VT),
00898             C99INIT(txbuffer, uart3_txbuffer),
00899             C99INIT(rxbuffer, uart3_rxbuffer),
00900             C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
00901             C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
00902         },
00903         C99INIT(sending, false),
00904     },
00905 #endif
00906     {
00907         C99INIT(hw, ) {
00908             C99INIT(table, &SPI_VT),
00909             C99INIT(txbuffer, spi_txbuffer),
00910             C99INIT(rxbuffer, spi_rxbuffer),
00911             C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
00912             C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
00913         },
00914         C99INIT(sending, false),
00915     }
00916 };
00917 
00918 struct SerialHardware *ser_hw_getdesc(int unit)
00919 {
00920     ASSERT(unit < SER_CNT);
00921     return &UARTDescs[unit].hw;
00922 }
00923 
00924 
00925 /*
00926  * Interrupt handlers
00927  */
00928 
00929 #if CONFIG_SER_HWHANDSHAKE
00930 
00932 DECLARE_ISR(SIG_CTS)
00933 {
00934     // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
00935     UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
00936     EIMSK &= ~EIMSKF_CTS;
00937 }
00938 
00939 #endif // CONFIG_SER_HWHANDSHAKE
00940 
00941 
00945 DECLARE_ISR(USART0_UDRE_vect)
00946 {
00947     SER_STROBE_ON;
00948 
00949     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
00950 
00951     if (fifo_isempty(txfifo))
00952     {
00953         SER_UART0_BUS_TXEND;
00954 #ifndef SER_UART0_BUS_TXOFF
00955         UARTDescs[SER_UART0].sending = false;
00956 #endif
00957     }
00958 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
00959     else if (!IS_CTS_ON)
00960     {
00961         // Disable rx interrupt and tx, enable CTS interrupt
00962         // UNTESTED
00963         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
00964         EIFR |= EIMSKF_CTS;
00965         EIMSK |= EIMSKF_CTS;
00966     }
00967 #endif
00968     else
00969     {
00970         char c = fifo_pop(txfifo);
00971         SER_UART0_BUS_TXCHAR(c);
00972     }
00973 
00974     SER_STROBE_OFF;
00975 }
00976 
00977 #ifdef SER_UART0_BUS_TXOFF
00978 
00993 DECLARE_ISR(USART0_TX_vect)
00994 {
00995     SER_STROBE_ON;
00996 
00997     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
00998     if (fifo_isempty(txfifo))
00999     {
01000         SER_UART0_BUS_TXOFF;
01001         UARTDescs[SER_UART0].sending = false;
01002     }
01003     else
01004         UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
01005 
01006     SER_STROBE_OFF;
01007 }
01008 #endif /* SER_UART0_BUS_TXOFF */
01009 
01010 
01011 #if AVR_HAS_UART1
01012 
01016 DECLARE_ISR(USART1_UDRE_vect)
01017 {
01018     SER_STROBE_ON;
01019 
01020     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
01021 
01022     if (fifo_isempty(txfifo))
01023     {
01024         SER_UART1_BUS_TXEND;
01025 #ifndef SER_UART1_BUS_TXOFF
01026         UARTDescs[SER_UART1].sending = false;
01027 #endif
01028     }
01029 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
01030     else if (!IS_CTS_ON)
01031     {
01032         // Disable rx interrupt and tx, enable CTS interrupt
01033         // UNTESTED
01034         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
01035         EIFR |= EIMSKF_CTS;
01036         EIMSK |= EIMSKF_CTS;
01037     }
01038 #endif
01039     else
01040     {
01041         char c = fifo_pop(txfifo);
01042         SER_UART1_BUS_TXCHAR(c);
01043     }
01044 
01045     SER_STROBE_OFF;
01046 }
01047 
01048 #ifdef SER_UART1_BUS_TXOFF
01049 
01054 DECLARE_ISR(USART1_TX_vect)
01055 {
01056     SER_STROBE_ON;
01057 
01058     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
01059     if (fifo_isempty(txfifo))
01060     {
01061         SER_UART1_BUS_TXOFF;
01062         UARTDescs[SER_UART1].sending = false;
01063     }
01064     else
01065         UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
01066 
01067     SER_STROBE_OFF;
01068 }
01069 #endif /* SER_UART1_BUS_TXOFF */
01070 
01071 #endif // AVR_HAS_UART1
01072 
01073 #if AVR_HAS_UART2
01074 
01078 DECLARE_ISR(USART2_UDRE_vect)
01079 {
01080     SER_STROBE_ON;
01081 
01082     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
01083 
01084     if (fifo_isempty(txfifo))
01085     {
01086         SER_UART2_BUS_TXEND;
01087 #ifndef SER_UART2_BUS_TXOFF
01088         UARTDescs[SER_UART2].sending = false;
01089 #endif
01090     }
01091     else
01092     {
01093         char c = fifo_pop(txfifo);
01094         SER_UART2_BUS_TXCHAR(c);
01095     }
01096 
01097     SER_STROBE_OFF;
01098 }
01099 
01100 #ifdef SER_UART2_BUS_TXOFF
01101 
01106 DECLARE_ISR(USART2_TX_vect)
01107 {
01108     SER_STROBE_ON;
01109 
01110     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
01111     if (fifo_isempty(txfifo))
01112     {
01113         SER_UART2_BUS_TXOFF;
01114         UARTDescs[SER_UART2].sending = false;
01115     }
01116     else
01117         UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2);
01118 
01119     SER_STROBE_OFF;
01120 }
01121 #endif /* SER_UART2_BUS_TXOFF */
01122 
01123 #endif // AVR_HAS_UART2
01124 
01125 #if AVR_HAS_UART3
01126 
01130 DECLARE_ISR(USART3_UDRE_vect)
01131 {
01132     SER_STROBE_ON;
01133 
01134     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
01135 
01136     if (fifo_isempty(txfifo))
01137     {
01138         SER_UART3_BUS_TXEND;
01139 #ifndef SER_UART3_BUS_TXOFF
01140         UARTDescs[SER_UART3].sending = false;
01141 #endif
01142     }
01143     else
01144     {
01145         char c = fifo_pop(txfifo);
01146         SER_UART3_BUS_TXCHAR(c);
01147     }
01148 
01149     SER_STROBE_OFF;
01150 }
01151 
01152 #ifdef SER_UART3_BUS_TXOFF
01153 
01158 DECLARE_ISR(USART3_TX_vect)
01159 {
01160     SER_STROBE_ON;
01161 
01162     struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
01163     if (fifo_isempty(txfifo))
01164     {
01165         SER_UART3_BUS_TXOFF;
01166         UARTDescs[SER_UART3].sending = false;
01167     }
01168     else
01169         UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3);
01170 
01171     SER_STROBE_OFF;
01172 }
01173 #endif /* SER_UART3_BUS_TXOFF */
01174 
01175 #endif // AVR_HAS_UART3
01176 
01177 
01193 DECLARE_ISR(USART0_RX_vect)
01194 {
01195     SER_STROBE_ON;
01196 
01197     /* Disable Recv complete IRQ */
01198     //UCSR0B &= ~BV(RXCIE);
01199     //IRQ_ENABLE;
01200 
01201     /* Should be read before UDR */
01202     ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01203 
01204     /* To clear the RXC flag we must _always_ read the UDR even when we're
01205      * not going to accept the incoming data, otherwise a new interrupt
01206      * will occur once the handler terminates.
01207      */
01208     char c = UDR0;
01209     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
01210 
01211     if (fifo_isfull(rxfifo))
01212         ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
01213     else
01214     {
01215         fifo_push(rxfifo, c);
01216 #if CONFIG_SER_HWHANDSHAKE
01217         if (fifo_isfull(rxfifo))
01218             RTS_OFF;
01219 #endif
01220     }
01221 
01222     /* Reenable receive complete int */
01223     //IRQ_DISABLE;
01224     //UCSR0B |= BV(RXCIE);
01225 
01226     SER_STROBE_OFF;
01227 }
01228 
01229 
01230 #if AVR_HAS_UART1
01231 
01243 DECLARE_ISR(USART1_RX_vect)
01244 {
01245     SER_STROBE_ON;
01246 
01247     /* Disable Recv complete IRQ */
01248     //UCSR1B &= ~BV(RXCIE);
01249     //IRQ_ENABLE;
01250 
01251     /* Should be read before UDR */
01252     ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01253 
01254     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01255      * not going to accept the incoming data
01256      */
01257     char c = UDR1;
01258     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
01259     //ASSERT_VALID_FIFO(rxfifo);
01260 
01261     if (UNLIKELY(fifo_isfull(rxfifo)))
01262         ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
01263     else
01264     {
01265         fifo_push(rxfifo, c);
01266 #if CONFIG_SER_HWHANDSHAKE
01267         if (fifo_isfull(rxfifo))
01268             RTS_OFF;
01269 #endif
01270     }
01271     /* Re-enable receive complete int */
01272     //IRQ_DISABLE;
01273     //UCSR1B |= BV(RXCIE);
01274 
01275     SER_STROBE_OFF;
01276 }
01277 
01278 #endif // AVR_HAS_UART1
01279 
01280 #if AVR_HAS_UART2
01281 
01293 DECLARE_ISR(USART2_RX_vect)
01294 {
01295     SER_STROBE_ON;
01296 
01297     /* Disable Recv complete IRQ */
01298     //UCSR1B &= ~BV(RXCIE);
01299     //IRQ_ENABLE;
01300 
01301     /* Should be read before UDR */
01302     ser_handles[SER_UART2]->status |= UCSR2A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01303 
01304     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01305      * not going to accept the incoming data
01306      */
01307     char c = UDR2;
01308     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART2]->rxfifo;
01309     //ASSERT_VALID_FIFO(rxfifo);
01310 
01311     if (UNLIKELY(fifo_isfull(rxfifo)))
01312         ser_handles[SER_UART2]->status |= SERRF_RXFIFOOVERRUN;
01313     else
01314     {
01315         fifo_push(rxfifo, c);
01316 #if CONFIG_SER_HWHANDSHAKE
01317         if (fifo_isfull(rxfifo))
01318             RTS_OFF;
01319 #endif
01320     }
01321     /* Re-enable receive complete int */
01322     //IRQ_DISABLE;
01323     //UCSR1B |= BV(RXCIE);
01324 
01325     SER_STROBE_OFF;
01326 }
01327 
01328 #endif // AVR_HAS_UART2
01329 
01330 #if AVR_HAS_UART3
01331 
01343 DECLARE_ISR(USART3_RX_vect)
01344 {
01345     SER_STROBE_ON;
01346 
01347     /* Disable Recv complete IRQ */
01348     //UCSR1B &= ~BV(RXCIE);
01349     //IRQ_ENABLE;
01350 
01351     /* Should be read before UDR */
01352     ser_handles[SER_UART3]->status |= UCSR3A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
01353 
01354     /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
01355      * not going to accept the incoming data
01356      */
01357     char c = UDR3;
01358     struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART3]->rxfifo;
01359     //ASSERT_VALID_FIFO(rxfifo);
01360 
01361     if (UNLIKELY(fifo_isfull(rxfifo)))
01362         ser_handles[SER_UART3]->status |= SERRF_RXFIFOOVERRUN;
01363     else
01364     {
01365         fifo_push(rxfifo, c);
01366 #if CONFIG_SER_HWHANDSHAKE
01367         if (fifo_isfull(rxfifo))
01368             RTS_OFF;
01369 #endif
01370     }
01371     /* Re-enable receive complete int */
01372     //IRQ_DISABLE;
01373     //UCSR1B |= BV(RXCIE);
01374 
01375     SER_STROBE_OFF;
01376 }
01377 
01378 #endif // AVR_HAS_UART3
01379 
01380 
01384 DECLARE_ISR(SPI_STC_vect)
01385 {
01386     SER_STROBE_ON;
01387 
01388     /* Read incoming byte. */
01389     if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
01390         fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
01391     /*
01392      * FIXME
01393     else
01394         ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
01395     */
01396 
01397     /* Send */
01398     if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
01399         SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
01400     else
01401         UARTDescs[SER_SPI].sending = false;
01402 
01403     SER_STROBE_OFF;
01404 }