BeRTOS
sam3_rstc.h
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00001 
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 
00072 #ifndef SAM3_RTSC_H
00073 #define SAM3_RTSC_H
00074 
00075 #define RSTC_BASE  0x400E1A00
00076 
00078 /*\{*/
00079 #define RSTC_CR         (*((reg32_t *)(RSTC_BASE + 0x00)))      ///< Reset controller control register address.
00080 #define RSTC_PROCRST                     0  ///< Processor reset.
00081 #define RSTC_PERRST                      2  ///< Peripheral reset.
00082 #define RSTC_EXTRST                      3  ///< External reset.
00083 #define RSTC_KEY                0xA5000000  ///< Password.
00084 /*\}*/
00085 
00087 /*\{*/
00088 #define RSTC_SR         (*((reg32_t *)(RSTC_BASE + 0x04)))      ///< Reset controller status register address.
00089 #define RSTC_URSTS                       0  ///< User reset status.
00090 #define RSTC_BODSTS                      1  ///< Brownout detection status.
00091 #define RSTC_RSTTYP_MASK        0x00000700  ///< Reset type.
00092 #define RSTC_RSTTYP_POWERUP     0x00000000  ///< Power-up reset.
00093 //#define RSTC_RSTTYP_WAKEUP      0x00000100      ///< VDDCORE rising.
00094 #define RSTC_RSTTYP_WATCHDOG    0x00000200  ///< Watchdog reset.
00095 #define RSTC_RSTTYP_SOFTWARE    0x00000300  ///< Software reset.
00096 #define RSTC_RSTTYP_USER        0x00000400  ///< User reset.
00097 #define RSTC_RSTTYP_BROWNOUT    0x00000500  ///< Brownout reset.
00098 #define RSTC_NRSTL                      16  ///< NRST pin level.
00099 #define RSTC_SRCMP                      17  ///< Software reset command in progress.
00100 /*\}*/
00101 
00103 /*\{*/
00104 #define RSTC_MR         (*((reg32_t *)(RSTC_BASE + 0x08)))      ///< Reset controller mode register address.
00105 #define RSTC_URSTEN                      0  ///< User reset enable.
00106 #define RSTC_URSTIEN                     4  ///< User reset interrupt enable.
00107 #define RSTC_ERSTL_MASK         0x00000F00  ///< External reset length.
00108 #define RSTC_ERSTL_SHIFT                 8  ///< Least significant bit of external reset length.
00109 #define RSTC_BODIEN                     16  ///< Brown-out detection interrupt enable.
00110 /*\}*/
00111 
00112 
00113 #endif /* SAM3_RTSC_H */