BeRTOS
at91_pwm.h
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00001 
00039 #ifndef AT91_PWM_H
00040 #define AT91_PWM_H
00041 
00045 /*\{*/
00046 #define PWM_MR_OFF              0x00000000    ///< PWM Mode Register offset.
00047 #define PWM_MR     (*((reg32_t *)(PWMC_BASE + PWM_MR_OFF))) ///< PWM Mode Register.
00048 #define PWM_MR_DIVA_MASK        0x000000FF    ///< PWM Mode Divide factor A Mask.
00049 #define PWM_MR_DIVA_SHIFT       0             ///< PWM Mode Divide factor A LSB.
00050 #define PWM_MR_DIVB_MASK        0x00FF0000    ///< PWM Mode Divide factor B Mask.
00051 #define PWM_MR_DIVB_SHIFT       16            ///< PWM Mode Divide factor B LSB.
00052 
00053 #define PWM_MR_PREA_MASK        0x00000F00    ///< PWM Mode prescaler A Mask.
00054 #define PWM_MR_PREA_SHIFT       8             ///< PWM Mode prescaler A LSB.
00055 #define PWM_MR_PREB_MASK        0x0F000000    ///< PWM Mode prescaler B Mask.
00056 #define PWM_MR_PREB_SHIFT       24            ///< PWM Mode prescaler B LSB.
00057 
00058 #define PWM_MR_PRE_MCK          0             ///< PWM Mode prescaler set to MCK.
00059 #define PWM_MR_PRE_MCK_DIV2     1             ///< PWM Mode prescaler set to MCK/2.
00060 #define PWM_MR_PRE_MCK_DIV4     2             ///< PWM Mode prescaler set to MCK/4.
00061 #define PWM_MR_PRE_MCK_DIV8     3             ///< PWM Mode prescaler set to MCK/8.
00062 #define PWM_MR_PRE_MCK_DIV16    4             ///< PWM Mode prescaler set to MCK/16.
00063 #define PWM_MR_PRE_MCK_DIV32    5             ///< PWM Mode prescaler set to MCK/32.
00064 #define PWM_MR_PRE_MCK_DIV64    6             ///< PWM Mode prescaler set to MCK/64.
00065 #define PWM_MR_PRE_MCK_DIV128   7             ///< PWM Mode prescaler set to MCK/128.
00066 #define PWM_MR_PRE_MCK_DIV256   8             ///< PWM Mode prescaler set to MCK/256.
00067 #define PWM_MR_PRE_MCK_DIV512   9             ///< PWM Mode prescaler set to MCK/512.
00068 #define PWM_MR_PRE_MCK_DIV1024  10            ///< PWM Mode prescaler set to MCK/1024.
00069 /*\}*/
00070 
00074 /*\{*/
00075 #define PWM_CHID_MASK           0x0000000F
00076 #define PWM_CHID0               0
00077 #define PWM_CHID1               1
00078 #define PWM_CHID2               2
00079 #define PWM_CHID3               3
00080 /*\}*/
00081 
00085 /*\{*/
00086 #define PWM_ENA_OFF             0x00000004    ///< PWM Enable Register offset.
00087 #define PWM_ENA     (*((reg32_t *)(PWMC_BASE + PWM_ENA_OFF))) ///< PWM Enable Register.
00088 /*\}*/
00089 
00093 /*\{*/
00094 #define PWM_DIS_OFF             0x00000008    ///< PWM Disable Register offset.
00095 #define PWM_DIS     (*((reg32_t *)(PWMC_BASE + PWM_DIS_OFF))) ///< PWM Disable Register.
00096 /*\}*/
00097 
00101 /*\{*/
00102 #define PWM_SR_OFF              0x0000000C    ///< PWM Status Register offset.
00103 #define PWM_SR      (*((reg32_t *)(PWMC_BASE + PWM_SR_OFF)))  ///< PWM Status Register.
00104 /*\}*/
00105 
00109 /*\{*/
00110 #define PWM_IER_OFF             0x00000010    ///< PWM Interrupt Enable Register offset.
00111 #define PWM_IER     (*((reg32_t *)(PWMC_BASE + PWM_IER_OFF))) ///< PWM Interrupt Enable Register.
00112 /*\}*/
00113 
00117 /*\{*/
00118 #define PWM_IDR_OFF             0x00000014    ///< PWM Interrupt Disable Register offset.
00119 #define PWM_IDR     (*((reg32_t *)(PWMC_BASE + PWM_IDR_OFF))) ///< PWM Interrupt Disable Register.
00120 /*\}*/
00121 
00125 /*\{*/
00126 #define PWM_IMR_OFF             0x00000018    ///< PWM Interrupt Mask Register offset.
00127 #define PWM_IMR     (*((reg32_t *)(PWMC_BASE + PWM_IMR_OFF))) ///< PWM Interrupt Mask Register.
00128 /*\}*/
00129 
00133 /*\{*/
00134 #define PWM_ISR_OFF             0x0000001C    ///< PWM Interrupt Status Register offset.
00135 #define PWM_ISR     (*((reg32_t *)(PWMC_BASE + PWM_ISR_OFF))) ///< PWM Interrupt Status Register.
00136 /*\}*/
00137 
00138 #define PWM_CH0_OFF             0x00000200    ///< PWM Channel 0 registers offset.
00139 #define PWM_CH1_OFF             0x00000220    ///< PWM Channel 1 registers offset.
00140 #define PWM_CH2_OFF             0x00000240    ///< PWM Channel 2 registers offset.
00141 #define PWM_CH3_OFF             0x00000260    ///< PWM Channel 3 registers offset.
00142 
00146 /*\{*/
00147 #define PWM_CMR_OFF             0x00000000    ///< PWM Channel Mode Register offset.
00148 #define PWM_CMR0    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Mode Register.
00149 #define PWM_CMR1    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Mode Register.
00150 #define PWM_CMR2    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Mode Register.
00151 #define PWM_CMR3    (*((reg32_t *)(PWMC_BASE + PWM_CMR_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Mode Register.
00152 
00153 #define PWM_CPRE_MCK_MASK       0x0000000F    ///< PWM Mode prescaler mask.
00154 #define PWM_CPRE_MCK            0             ///< PWM Mode prescaler set to MCK.
00155 #define PWM_CPRE_MCK_DIV2       1             ///< PWM Mode prescaler set to MCK/2.
00156 #define PWM_CPRE_MCK_DIV4       2             ///< PWM Mode prescaler set to MCK/4.
00157 #define PWM_CPRE_MCK_DIV8       3             ///< PWM Mode prescaler set to MCK/8.
00158 #define PWM_CPRE_MCK_DIV16      4             ///< PWM Mode prescaler set to MCK/16.
00159 #define PWM_CPRE_MCK_DIV32      5             ///< PWM Mode prescaler set to MCK/32.
00160 #define PWM_CPRE_MCK_DIV64      6             ///< PWM Mode prescaler set to MCK/64.
00161 #define PWM_CPRE_MCK_DIV128     7             ///< PWM Mode prescaler set to MCK/128.
00162 #define PWM_CPRE_MCK_DIV256     8             ///< PWM Mode prescaler set to MCK/256.
00163 #define PWM_CPRE_MCK_DIV512     9             ///< PWM Mode prescaler set to MCK/512.
00164 #define PWM_CPRE_MCK_DIV1024    10            ///< PWM Mode prescaler set to MCK/1024.
00165 #define PWM_CPRE_CLKA           11            ///< PWM Mode prescaler set to CLKA.
00166 #define PWM_CPRE_CLKB           12            ///< PWM Mode prescaler set to CLKB.
00167 
00168 #define PWM_CALG                8             ///< PWM Mode channel alignment.
00169 #define PWM_CPOL                9             ///< PWM Mode channel polarity.
00170 #define PWM_CPD                 10            ///< PWM Mode channel update period.
00171 /*\}*/
00172 
00173 
00177 /*\{*/
00178 #define PWM_CDTY_OFF            0x00000004    ///< PWM Channel Duty Cycle Register offset.
00179 #define PWM_CDTY0   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Duty Cycle Register.
00180 #define PWM_CDTY1   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Duty Cycle Register.
00181 #define PWM_CDTY2   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Duty Cycle Register.
00182 #define PWM_CDTY3   (*((reg32_t *)(PWMC_BASE + PWM_CDTY_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Duty Cycle Register.
00183 /*\}*/
00184 
00185 
00189 /*\{*/
00190 #define PWM_CPRD_OFF            0x00000008    ///< PWM Channel Period Register offset.
00191 #define PWM_CPRD0   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Period Register.
00192 #define PWM_CPRD1   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Period Register.
00193 #define PWM_CPRD2   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Period Register.
00194 #define PWM_CPRD3   (*((reg32_t *)(PWMC_BASE + PWM_CPRD_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Period Register.
00195 /*\}*/
00196 
00197 
00201 /*\{*/
00202 #define PWM_CCNT_OFF            0x0000000C    ///< PWM Channel Counter Register offset.
00203 #define PWM_CCNT0   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Counter Register.
00204 #define PWM_CCNT1   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Counter Register.
00205 #define PWM_CCNT2   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Counter Register.
00206 #define PWM_CCNT3   (*((reg32_t *)(PWMC_BASE + PWM_CCNT_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Counter Register.
00207 /*\}*/
00208 
00209 
00213 /*\{*/
00214 #define PWM_CUPD_OFF            0x00000010    ///< PWM Channel Update Register offset.
00215 #define PWM_CUPD0   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH0_OFF))) ///< PWM Channel 0 Update Register.
00216 #define PWM_CUPD1   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH1_OFF))) ///< PWM Channel 1 Update Register.
00217 #define PWM_CUPD2   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH2_OFF))) ///< PWM Channel 2 Update Register.
00218 #define PWM_CUPD3   (*((reg32_t *)(PWMC_BASE + PWM_CUPD_OFF + PWM_CH3_OFF))) ///< PWM Channel 3 Update Register.
00219 /*\}*/
00220 
00221 #endif /* AT91_PWM_H */