BeRTOS
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00001 00041 #ifndef SAM3_DACC_H 00042 #define SAM3_DACC_H 00043 00045 #define DACC_BASE 0x400C8000 00046 00051 #define DACC_CR_OFF 0x00000000 ///< Control register offeset. 00052 #define DACC_CR (*((reg32_t*)(DACC_BASE + DACC_CR_OFF))) ///< Control register address. 00053 #define DACC_SWRST 0 ///< Software reset. 00054 /* \} */ 00055 00060 #define DACC_MR_OFF 0x00000004 ///< Mode register offeset. 00061 #define DACC_MR (*((reg32_t*) (DACC_BASE + DACC_MR_OFF))) ///< Mode register address. 00062 #define DACC_TRGEN 0 ///< Trigger enable. 00063 #define DACC_TRGSEL_MASK 0x14 ///< Trigger selection mask. 00064 #define DACC_TRGSEL_SHIFT 1 ///< Trigger selection shift. 00065 #define DACC_WORD 4 ///< Word transfer. 00066 #define DACC_SLEEP 5 ///< Sleep mode.Fast Wake up Mode 00067 #define DACC_FASTWKUP 6 ///< Fast Wake up Mode 00068 #define DACC_REFRESH_MASK 0xFF00 ///< Refresh Period mask 00069 #define DACC_REFRESH_SHIFT 8 ///< Refresh Period shift 00070 #define DACC_USER_SEL_MASK 0x30000 ///< User Channel Selection mask 00071 #define DACC_USER_SEL_SHIFT 16 ///< User Channel Selection shift 00072 #define DACC_TAG 20 ///< Tag selection mode 00073 #define DACC_MAXS 21 ///< Max speed mode 00074 #define DACC_STARTUP_MASK 0x3F000000 ///< Startup time selection 00075 #define DACC_STARTUP_SHIFT 24 ///< Startup time selsection shift 00076 00077 00083 #define DACC_TRGSEL_TIO_CH0 1 00084 #define DACC_TRGSEL_TIO_CH1 2 00085 #define DACC_TRGSEL_TIO_CH2 3 00086 #define DACC_TRGSEL_PWM0 4 00087 #define DACC_TRGSEL_PWM1 5 00088 /* \} */ 00089 00090 #define DACC_MR_STARTUP_0 0 ///< 0 periods of DACClock 00091 #define DACC_MR_STARTUP_8 1 ///< 8 periods of DACClock 00092 #define DACC_MR_STARTUP_16 2 ///< 16 periods of of DACClock 00093 #define DACC_MR_STARTUP_24 3 ///< 24 periods of of DACClock 00094 #define DACC_MR_STARTUP_64 4 ///< 64 periods of of DACClock 00095 #define DACC_MR_STARTUP_80 5 ///< 70 periods of of DACClock 00096 #define DACC_MR_STARTUP_96 6 ///< 96 periods of of DACClock 00097 #define DACC_MR_STARTUP_112 7 ///< 112 periods of of DACClock 00098 #define DACC_MR_STARTUP_512 8 ///< 512 periods of DACClock 00099 #define DACC_MR_STARTUP_576 9 ///< 576 periods of DACClock 00100 #define DACC_MR_STARTUP_640 10 ///< 640 periods of DACClock 00101 #define DACC_MR_STARTUP_704 11 ///< 704 periods of DACClock 00102 #define DACC_MR_STARTUP_768 12 ///< 768 periods of DACClock 00103 #define DACC_MR_STARTUP_832 13 ///< 832 periods of DACClock 00104 #define DACC_MR_STARTUP_896 14 ///< 896 periods of DACClock 00105 #define DACC_MR_STARTUP_960 15 ///< 960 periods of DACClock 00106 #define DACC_MR_STARTUP_1024 16 ///< 1024 periods of DACClock 00107 #define DACC_MR_STARTUP_1088 17 ///< 1088 periods of DACClock 00108 #define DACC_MR_STARTUP_1152 18 ///< 1152 periods of DACClock 00109 #define DACC_MR_STARTUP_1216 19 ///< 1216 periods of DACClock 00110 #define DACC_MR_STARTUP_1280 20 ///< 1280 periods of DACClock 00111 #define DACC_MR_STARTUP_1344 21 ///< 1344 periods of DACClock 00112 #define DACC_MR_STARTUP_1408 22 ///< 1408 periods of DACClock 00113 #define DACC_MR_STARTUP_1472 23 ///< 1472 periods of DACClock 00114 #define DACC_MR_STARTUP_1536 24 ///< 1536 periods of DACClock 00115 #define DACC_MR_STARTUP_1600 25 ///< 1600 periods of DACClock 00116 #define DACC_MR_STARTUP_1664 26 ///< 1664 periods of DACClock 00117 #define DACC_MR_STARTUP_1728 27 ///< 1728 periods of DACClock 00118 #define DACC_MR_STARTUP_1792 28 ///< 1792 periods of DACClock 00119 #define DACC_MR_STARTUP_1856 29 ///< 1856 periods of DACClock 00120 #define DACC_MR_STARTUP_1920 30 ///< 1920 periods of DACClock 00121 #define DACC_MR_STARTUP_1984 31 ///< 1984 periods of DACClock 00122 /* \} */ 00123 00127 #define DACC_CHER_OFF 0x00000010 ///< Channel enable register offeset. 00128 #define DACC_CHER (*((reg32_t*) (DACC_BASE + DACC_CHER_OFF))) ///< Channel enable register address. 00129 00133 #define DACC_CHDR_OFF 0x00000014 ///< Channel disable register offeset. 00134 #define DACC_CHDR (*((reg32_t*) (DACC_BASE + DACC_CHDR_OFF))) ///< Channel disable register address. 00135 00139 #define DACC_CHSR_OFF 0x00000018 ///< Channel status register offeset. 00140 #define DACC_CHSR (*((reg32_t*) (DACC_BASE + DACC_CHSR_OFF))) ///< Channel status register address. 00141 00142 #define DACC_CH0 0 ///< Channel 0. 00143 #define DACC_CH1 1 ///< Channel 1. 00144 /* \} */ 00145 00149 #define DACC_CDR_OFF 0x00000020 ///< Conversion data register offeset. 00150 #define DACC_CDR (*((reg32_t*) (DACC_BASE + DACC_CDR_OFF))) ///< Conversion data register address. 00151 00152 00156 #define DACC_IER_OFF 0x00000024 ///< Interrupt enable register offeset. 00157 #define DACC_IER (*((reg32_t*) (DACC_BASE + DACC_IER_OFF))) ///< Interrupt enable register address. 00158 00162 #define DACC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset. 00163 #define DACC_IDR (*((reg32_t*) (DACC_BASE + DACC_IDR_OFF))) ///< Interrupt disable register address. 00164 00168 #define DACC_IMR_OFF 0x0000002C ///< Interrupt disable register offeset. 00169 #define DACC_IMR (*((reg32_t*) (DACC_BASE + DACC_IMR_OFF))) ///< Interrupt disable register address. 00170 00174 #define DACC_ISR_OFF 0x00000030 ///< Interrupt disable status offeset. 00175 #define DACC_ISR (*((reg32_t*) (DACC_BASE + DACC_ISR_OFF))) ///< Interrupt status register address. 00176 00177 #define DACC_TXRDY 0 ///< Transmit ready interrupt 00178 #define DACC_EOC 1 ///< End of conversion interrupt 00179 #define DACC_ENDTX 2 ///< End of transmit buffer interrupt 00180 #define DACC_TXBUFE 3 ///< Transmit buffer empty interrupt 00181 00182 00187 #define DACC_RPR_OFF 0x100 ///< Receive Pointer Register. 00188 #define DACC_RPR (*((reg32_t*) (DACC_BASE + DACC_RPR_OFF))) ///< Receive Pointer Register. 00189 00190 #define DACC_RCR_OFF 0x104 ///< Receive Counter Register. 00191 #define DACC_RCR (*((reg32_t*) (DACC_BASE + DACC_RCR_OFF))) ///< Receive Counter Register. 00192 00193 #define DACC_TPR_OFF 0x108 ///< Transmit Pointer Register. 00194 #define DACC_TPR (*((reg32_t*) (DACC_BASE + DACC_TPR_OFF))) ///< Transmit Pointer Register. 00195 00196 #define DACC_TCR_OFF 0x10C ///< Transmit Counter Register. 00197 #define DACC_TCR (*((reg32_t*) (DACC_BASE + DACC_TCR_OFF))) ///< Transmit Counter Register. 00198 00199 #define DACC_RNPR_OFF 0x110 ///< Receive Next Pointer Register. 00200 #define DACC_RNPR (*((reg32_t*) (DACC_BASE + DACC_RNPR_OFF))) ///< Receive Next Pointer Register. 00201 00202 #define DACC_RNCR_OFF 0x114 ///< Receive Next Counter Register. 00203 #define DACC_RNCR (*((reg32_t*) (DACC_BASE + DACC_RNCR_OFF))) ///< Receive Next Counter Register. 00204 00205 #define DACC_TNPR_OFF 0x118 ///< Transmit Next Pointer Register. 00206 #define DACC_TNPR (*((reg32_t*) (DACC_BASE + DACC_TNPR_OFF))) ///< Transmit Next Pointer Register. 00207 00208 #define DACC_TNCR_OFF 0x11C ///< Transmit Next Counter Register. 00209 #define DACC_TNCR (*((reg32_t*) (DACC_BASE + DACC_TNCR_OFF))) ///< Transmit Next Counter Register. 00210 00211 #define DACC_PTCR_OFF 0x120 ///< Transfer Control Register. 00212 #define DACC_PTCR (*((reg32_t*) (DACC_BASE + DACC_PTCR_OFF))) ///< Transfer Control Register. 00213 00214 #define DACC_PTSR_OFF 0x124 ///< Transfer Status Register. 00215 #define DACC_PTSR (*((reg32_t*) (DACC_BASE + DACC_PTSR_OFF))) ///< Transfer Status Register. 00216 00217 00218 #define DACC_PTCR_RXTEN 0 ///< DACC_PTCR Receiver Transfer Enable. 00219 #define DACC_PTCR_RXTDIS 1 ///< DACC_PTCR Receiver Transfer Disable. 00220 #define DACC_PTCR_TXTEN 8 ///< DACC_PTCR Transmitter Transfer Enable. 00221 #define DACC_PTCR_TXTDIS 9 ///< DACC_PTCR Transmitter Transfer Disable. 00222 #define DACC_PTSR_RXTEN 0 ///< DACC_PTSR Receiver Transfer Enable. 00223 #define DACC_PTSR_TXTEN 8 ///< DACC_PTSR Transmitter Transfer Enable. 00224 00225 #endif /* SAM3_DACC_H */