BeRTOS
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00001 00036 #ifndef LM3S_SYSCTL_H 00037 #define LM3S_SYSCTL_H 00038 00042 /*\{*/ 00043 #define SYSCTL_DID0 0x400FE000 ///< Device Identification 0 00044 #define SYSCTL_DID1 0x400FE004 ///< Device Identification 1 00045 #define SYSCTL_DC0 0x400FE008 ///< Device Capabilities 0 00046 #define SYSCTL_DC1 0x400FE010 ///< Device Capabilities 1 00047 #define SYSCTL_DC2 0x400FE014 ///< Device Capabilities 2 00048 #define SYSCTL_DC3 0x400FE018 ///< Device Capabilities 3 00049 #define SYSCTL_DC4 0x400FE01C ///< Device Capabilities 4 00050 #define SYSCTL_DC5 0x400FE020 ///< Device Capabilities 5 00051 #define SYSCTL_DC6 0x400FE024 ///< Device Capabilities 6 00052 #define SYSCTL_DC7 0x400FE028 ///< Device Capabilities 7 00053 #define SYSCTL_DC8 0x400FE02C ///< Device Capabilities 8 ADC 00054 00055 #define SYSCTL_PBORCTL 0x400FE030 ///< Brown-Out Reset Control 00056 #define SYSCTL_LDOPCTL 0x400FE034 ///< LDO Power Control 00057 #define SYSCTL_SRCR0 0x400FE040 ///< Software Reset Control 0 00058 #define SYSCTL_SRCR1 0x400FE044 ///< Software Reset Control 1 00059 #define SYSCTL_SRCR2 0x400FE048 ///< Software Reset Control 2 00060 #define SYSCTL_RIS 0x400FE050 ///< Raw Interrupt Status 00061 #define SYSCTL_IMC 0x400FE054 ///< Interrupt Mask Control 00062 #define SYSCTL_MISC 0x400FE058 ///< Masked Interrupt Status and 00063 00064 #define SYSCTL_RESC 0x400FE05C ///< Reset Cause 00065 #define SYSCTL_RCC 0x400FE060 ///< Run-Mode Clock Configuration 00066 #define SYSCTL_PLLCFG 0x400FE064 ///< XTAL to PLL Translation 00067 #define SYSCTL_GPIOHSCTL 0x400FE06C ///< GPIO High-Speed Control 00068 #define SYSCTL_GPIOHBCTL 0x400FE06C ///< GPIO High-Performance Bus 00069 00070 #define SYSCTL_RCC2 0x400FE070 ///< Run-Mode Clock Configuration 2 00071 #define SYSCTL_MOSCCTL 0x400FE07C ///< Main Oscillator Control 00072 #define SYSCTL_RCGC0 0x400FE100 ///< Run Mode Clock Gating Control 00073 00074 #define SYSCTL_RCGC1 0x400FE104 ///< Run Mode Clock Gating Control 00075 00076 #define SYSCTL_RCGC2 0x400FE108 ///< Run Mode Clock Gating Control 00077 00078 #define SYSCTL_SCGC0 0x400FE110 ///< Sleep Mode Clock Gating Control 00079 00080 #define SYSCTL_SCGC1 0x400FE114 ///< Sleep Mode Clock Gating Control 00081 00082 #define SYSCTL_SCGC2 0x400FE118 ///< Sleep Mode Clock Gating Control 00083 00084 #define SYSCTL_DCGC0 0x400FE120 ///< Deep Sleep Mode Clock Gating 00085 00086 #define SYSCTL_DCGC1 0x400FE124 ///< Deep-Sleep Mode Clock Gating 00087 00088 #define SYSCTL_DCGC2 0x400FE128 ///< Deep Sleep Mode Clock Gating 00089 00090 #define SYSCTL_DSLPCLKCFG 0x400FE144 ///< Deep Sleep Clock Configuration 00091 #define SYSCTL_CLKVCLR 0x400FE150 ///< Clock Verification Clear 00092 #define SYSCTL_PIOSCCAL 0x400FE150 ///< Precision Internal Oscillator 00093 00094 #define SYSCTL_PIOSCSTAT 0x400FE154 ///< Precision Internal Oscillator 00095 00096 #define SYSCTL_LDOARST 0x400FE160 ///< Allow Unregulated LDO to Reset 00097 00098 #define SYSCTL_I2SMCLKCFG 0x400FE170 ///< I2S MCLK Configuration 00099 #define SYSCTL_DC9 0x400FE190 ///< Device Capabilities 9 ADC 00100 00101 #define SYSCTL_NVMSTAT 0x400FE1A0 ///< Non-Volatile Memory Information 00102 /*\}*/ 00103 00107 /*\{*/ 00108 #define SYSCTL_DID0_VER_M 0x70000000 ///< DID0 Version 00109 #define SYSCTL_DID0_VER_0 0x00000000 ///< Initial DID0 register format 00110 00111 00112 #define SYSCTL_DID0_VER_1 0x10000000 ///< Second version of the DID0 00113 00114 #define SYSCTL_DID0_CLASS_M 0x00FF0000 ///< Device Class 00115 #define SYSCTL_DID0_CLASS_SANDSTORM \ 00116 0x00000000 ///< Sandstorm-class Device 00117 #define SYSCTL_DID0_CLASS_FURY 0x00010000 ///< Stellaris(R) Fury-class devices 00118 #define SYSCTL_DID0_CLASS_DUSTDEVIL \ 00119 0x00030000 ///< Stellaris(R) DustDevil-class 00120 00121 #define SYSCTL_DID0_CLASS_TEMPEST \ 00122 0x00040000 ///< Stellaris(R) Tempest-class 00123 00124 #define SYSCTL_DID0_MAJ_M 0x0000FF00 ///< Major Revision 00125 #define SYSCTL_DID0_MAJ_REVA 0x00000000 ///< Revision A (initial device) 00126 #define SYSCTL_DID0_MAJ_REVB 0x00000100 ///< Revision B (first base layer 00127 00128 #define SYSCTL_DID0_MAJ_REVC 0x00000200 ///< Revision C (second base layer 00129 00130 #define SYSCTL_DID0_MIN_M 0x000000FF ///< Minor Revision 00131 #define SYSCTL_DID0_MIN_0 0x00000000 ///< Initial device, or a major 00132 00133 #define SYSCTL_DID0_MIN_1 0x00000001 ///< First metal layer change 00134 #define SYSCTL_DID0_MIN_2 0x00000002 ///< Second metal layer change 00135 #define SYSCTL_DID0_MIN_3 0x00000003 ///< Minor revision 3 00136 #define SYSCTL_DID0_MIN_4 0x00000004 ///< Minor revision 4 00137 #define SYSCTL_DID0_MIN_5 0x00000005 ///< Minor revision 5 00138 /*\}*/ 00139 00143 /*\{*/ 00144 #define SYSCTL_DID1_VER_M 0xF0000000 ///< DID1 Version 00145 #define SYSCTL_DID1_VER_0 0x00000000 ///< Initial DID1 register format 00146 00147 00148 #define SYSCTL_DID1_VER_1 0x10000000 ///< Second version of the DID1 00149 00150 #define SYSCTL_DID1_FAM_M 0x0F000000 ///< Family 00151 #define SYSCTL_DID1_FAM_STELLARIS \ 00152 0x00000000 ///< Stellaris family of 00153 00154 00155 00156 #define SYSCTL_DID1_PRTNO_M 0x00FF0000 ///< Part Number 00157 #define SYSCTL_DID1_PRTNO_101 0x00010000 ///< LM3S101 00158 #define SYSCTL_DID1_PRTNO_102 0x00020000 ///< LM3S102 00159 #define SYSCTL_DID1_PRTNO_300 0x00190000 ///< LM3S300 00160 #define SYSCTL_DID1_PRTNO_301 0x00110000 ///< LM3S301 00161 #define SYSCTL_DID1_PRTNO_308 0x001A0000 ///< LM3S308 00162 #define SYSCTL_DID1_PRTNO_310 0x00120000 ///< LM3S310 00163 #define SYSCTL_DID1_PRTNO_315 0x00130000 ///< LM3S315 00164 #define SYSCTL_DID1_PRTNO_316 0x00140000 ///< LM3S316 00165 #define SYSCTL_DID1_PRTNO_317 0x00170000 ///< LM3S317 00166 #define SYSCTL_DID1_PRTNO_328 0x00150000 ///< LM3S328 00167 #define SYSCTL_DID1_PRTNO_600 0x002A0000 ///< LM3S600 00168 #define SYSCTL_DID1_PRTNO_601 0x00210000 ///< LM3S601 00169 #define SYSCTL_DID1_PRTNO_608 0x002B0000 ///< LM3S608 00170 #define SYSCTL_DID1_PRTNO_610 0x00220000 ///< LM3S610 00171 #define SYSCTL_DID1_PRTNO_611 0x00230000 ///< LM3S611 00172 #define SYSCTL_DID1_PRTNO_612 0x00240000 ///< LM3S612 00173 #define SYSCTL_DID1_PRTNO_613 0x00250000 ///< LM3S613 00174 #define SYSCTL_DID1_PRTNO_615 0x00260000 ///< LM3S615 00175 #define SYSCTL_DID1_PRTNO_617 0x00280000 ///< LM3S617 00176 #define SYSCTL_DID1_PRTNO_618 0x00290000 ///< LM3S618 00177 #define SYSCTL_DID1_PRTNO_628 0x00270000 ///< LM3S628 00178 #define SYSCTL_DID1_PRTNO_800 0x00380000 ///< LM3S800 00179 #define SYSCTL_DID1_PRTNO_801 0x00310000 ///< LM3S801 00180 #define SYSCTL_DID1_PRTNO_808 0x00390000 ///< LM3S808 00181 #define SYSCTL_DID1_PRTNO_811 0x00320000 ///< LM3S811 00182 #define SYSCTL_DID1_PRTNO_812 0x00330000 ///< LM3S812 00183 #define SYSCTL_DID1_PRTNO_815 0x00340000 ///< LM3S815 00184 #define SYSCTL_DID1_PRTNO_817 0x00360000 ///< LM3S817 00185 #define SYSCTL_DID1_PRTNO_818 0x00370000 ///< LM3S818 00186 #define SYSCTL_DID1_PRTNO_828 0x00350000 ///< LM3S828 00187 #define SYSCTL_DID1_PRTNO_1110 0x00BF0000 ///< LM3S1110 00188 #define SYSCTL_DID1_PRTNO_1133 0x00C30000 ///< LM3S1133 00189 #define SYSCTL_DID1_PRTNO_1138 0x00C50000 ///< LM3S1138 00190 #define SYSCTL_DID1_PRTNO_1150 0x00C10000 ///< LM3S1150 00191 #define SYSCTL_DID1_PRTNO_1162 0x00C40000 ///< LM3S1162 00192 #define SYSCTL_DID1_PRTNO_1165 0x00C20000 ///< LM3S1165 00193 #define SYSCTL_DID1_PRTNO_1332 0x00C60000 ///< LM3S1332 00194 #define SYSCTL_DID1_PRTNO_1435 0x00BC0000 ///< LM3S1435 00195 #define SYSCTL_DID1_PRTNO_1439 0x00BA0000 ///< LM3S1439 00196 #define SYSCTL_DID1_PRTNO_1512 0x00BB0000 ///< LM3S1512 00197 #define SYSCTL_DID1_PRTNO_1538 0x00C70000 ///< LM3S1538 00198 #define SYSCTL_DID1_PRTNO_1601 0x00DB0000 ///< LM3S1601 00199 #define SYSCTL_DID1_PRTNO_1607 0x00060000 ///< LM3S1607 00200 #define SYSCTL_DID1_PRTNO_1608 0x00DA0000 ///< LM3S1608 00201 #define SYSCTL_DID1_PRTNO_1620 0x00C00000 ///< LM3S1620 00202 #define SYSCTL_DID1_PRTNO_1625 0x00030000 ///< LM3S1625 00203 #define SYSCTL_DID1_PRTNO_1626 0x00040000 ///< LM3S1626 00204 #define SYSCTL_DID1_PRTNO_1627 0x00050000 ///< LM3S1627 00205 #define SYSCTL_DID1_PRTNO_1635 0x00B30000 ///< LM3S1635 00206 #define SYSCTL_DID1_PRTNO_1637 0x00BD0000 ///< LM3S1637 00207 #define SYSCTL_DID1_PRTNO_1751 0x00B90000 ///< LM3S1751 00208 #define SYSCTL_DID1_PRTNO_1776 0x00100000 ///< LM3S1776 00209 #define SYSCTL_DID1_PRTNO_1811 0x00160000 ///< LM3S1811 00210 #define SYSCTL_DID1_PRTNO_1816 0x003D0000 ///< LM3S1816 00211 #define SYSCTL_DID1_PRTNO_1850 0x00B40000 ///< LM3S1850 00212 #define SYSCTL_DID1_PRTNO_1911 0x00DD0000 ///< LM3S1911 00213 #define SYSCTL_DID1_PRTNO_1918 0x00DC0000 ///< LM3S1918 00214 #define SYSCTL_DID1_PRTNO_1937 0x00B70000 ///< LM3S1937 00215 #define SYSCTL_DID1_PRTNO_1958 0x00BE0000 ///< LM3S1958 00216 #define SYSCTL_DID1_PRTNO_1960 0x00B50000 ///< LM3S1960 00217 #define SYSCTL_DID1_PRTNO_1968 0x00B80000 ///< LM3S1968 00218 #define SYSCTL_DID1_PRTNO_1J11 0x000F0000 ///< LM3S1J11 00219 #define SYSCTL_DID1_PRTNO_1J16 0x003C0000 ///< LM3S1J16 00220 #define SYSCTL_DID1_PRTNO_1N11 0x000E0000 ///< LM3S1N11 00221 #define SYSCTL_DID1_PRTNO_1N16 0x003B0000 ///< LM3S1N16 00222 #define SYSCTL_DID1_PRTNO_1W16 0x00300000 ///< LM3S1W16 00223 #define SYSCTL_DID1_PRTNO_1Z16 0x002F0000 ///< LM3S1Z16 00224 #define SYSCTL_DID1_PRTNO_2110 0x00510000 ///< LM3S2110 00225 #define SYSCTL_DID1_PRTNO_2139 0x00840000 ///< LM3S2139 00226 #define SYSCTL_DID1_PRTNO_2276 0x00390000 ///< LM3S2276 00227 #define SYSCTL_DID1_PRTNO_2410 0x00A20000 ///< LM3S2410 00228 #define SYSCTL_DID1_PRTNO_2412 0x00590000 ///< LM3S2412 00229 #define SYSCTL_DID1_PRTNO_2432 0x00560000 ///< LM3S2432 00230 #define SYSCTL_DID1_PRTNO_2533 0x005A0000 ///< LM3S2533 00231 #define SYSCTL_DID1_PRTNO_2601 0x00E10000 ///< LM3S2601 00232 #define SYSCTL_DID1_PRTNO_2608 0x00E00000 ///< LM3S2608 00233 #define SYSCTL_DID1_PRTNO_2616 0x00330000 ///< LM3S2616 00234 #define SYSCTL_DID1_PRTNO_2620 0x00570000 ///< LM3S2620 00235 #define SYSCTL_DID1_PRTNO_2637 0x00850000 ///< LM3S2637 00236 #define SYSCTL_DID1_PRTNO_2651 0x00530000 ///< LM3S2651 00237 #define SYSCTL_DID1_PRTNO_2671 0x00800000 ///< LM3S2671 00238 #define SYSCTL_DID1_PRTNO_2678 0x00500000 ///< LM3S2678 00239 #define SYSCTL_DID1_PRTNO_2730 0x00A40000 ///< LM3S2730 00240 #define SYSCTL_DID1_PRTNO_2739 0x00520000 ///< LM3S2739 00241 #define SYSCTL_DID1_PRTNO_2776 0x003A0000 ///< LM3S2776 00242 #define SYSCTL_DID1_PRTNO_2793 0x006D0000 ///< LM3S2793 00243 #define SYSCTL_DID1_PRTNO_2911 0x00E30000 ///< LM3S2911 00244 #define SYSCTL_DID1_PRTNO_2918 0x00E20000 ///< LM3S2918 00245 #define SYSCTL_DID1_PRTNO_2939 0x00540000 ///< LM3S2939 00246 #define SYSCTL_DID1_PRTNO_2948 0x008F0000 ///< LM3S2948 00247 #define SYSCTL_DID1_PRTNO_2950 0x00580000 ///< LM3S2950 00248 #define SYSCTL_DID1_PRTNO_2965 0x00550000 ///< LM3S2965 00249 #define SYSCTL_DID1_PRTNO_2B93 0x006C0000 ///< LM3S2B93 00250 #define SYSCTL_DID1_PRTNO_3651 0x00430000 ///< LM3S3651 00251 #define SYSCTL_DID1_PRTNO_3739 0x00440000 ///< LM3S3739 00252 #define SYSCTL_DID1_PRTNO_3748 0x00490000 ///< LM3S3748 00253 #define SYSCTL_DID1_PRTNO_3749 0x00450000 ///< LM3S3749 00254 #define SYSCTL_DID1_PRTNO_3826 0x00420000 ///< LM3S3826 00255 #define SYSCTL_DID1_PRTNO_3J26 0x00410000 ///< LM3S3J26 00256 #define SYSCTL_DID1_PRTNO_3N26 0x00400000 ///< LM3S3N26 00257 #define SYSCTL_DID1_PRTNO_3W26 0x003F0000 ///< LM3S3W26 00258 #define SYSCTL_DID1_PRTNO_3Z26 0x003E0000 ///< LM3S3Z26 00259 #define SYSCTL_DID1_PRTNO_5632 0x00810000 ///< LM3S5632 00260 #define SYSCTL_DID1_PRTNO_5651 0x000C0000 ///< LM3S5651 00261 #define SYSCTL_DID1_PRTNO_5652 0x008A0000 ///< LM3S5652 00262 #define SYSCTL_DID1_PRTNO_5656 0x004D0000 ///< LM3S5656 00263 #define SYSCTL_DID1_PRTNO_5662 0x00910000 ///< LM3S5662 00264 #define SYSCTL_DID1_PRTNO_5732 0x00960000 ///< LM3S5732 00265 #define SYSCTL_DID1_PRTNO_5737 0x00970000 ///< LM3S5737 00266 #define SYSCTL_DID1_PRTNO_5739 0x00A00000 ///< LM3S5739 00267 #define SYSCTL_DID1_PRTNO_5747 0x00990000 ///< LM3S5747 00268 #define SYSCTL_DID1_PRTNO_5749 0x00A70000 ///< LM3S5749 00269 #define SYSCTL_DID1_PRTNO_5752 0x009A0000 ///< LM3S5752 00270 #define SYSCTL_DID1_PRTNO_5762 0x009C0000 ///< LM3S5762 00271 #define SYSCTL_DID1_PRTNO_5791 0x00690000 ///< LM3S5791 00272 #define SYSCTL_DID1_PRTNO_5951 0x000B0000 ///< LM3S5951 00273 #define SYSCTL_DID1_PRTNO_5956 0x004E0000 ///< LM3S5956 00274 #define SYSCTL_DID1_PRTNO_5B91 0x00680000 ///< LM3S5B91 00275 #define SYSCTL_DID1_PRTNO_5K31 0x00090000 ///< LM3S5K31 00276 #define SYSCTL_DID1_PRTNO_5K36 0x004A0000 ///< LM3S5K36 00277 #define SYSCTL_DID1_PRTNO_5P31 0x000A0000 ///< LM3S5P31 00278 #define SYSCTL_DID1_PRTNO_5P36 0x00480000 ///< LM3S5P36 00279 #define SYSCTL_DID1_PRTNO_5P51 0x000D0000 ///< LM3S5P51 00280 #define SYSCTL_DID1_PRTNO_5P56 0x004C0000 ///< LM3S5P56 00281 #define SYSCTL_DID1_PRTNO_5R31 0x00070000 ///< LM3S5R31 00282 #define SYSCTL_DID1_PRTNO_5R36 0x004B0000 ///< LM3S5R36 00283 #define SYSCTL_DID1_PRTNO_5T36 0x00470000 ///< LM3S5T36 00284 #define SYSCTL_DID1_PRTNO_5Y36 0x00460000 ///< LM3S5Y36 00285 #define SYSCTL_DID1_PRTNO_6100 0x00A10000 ///< LM3S6100 00286 #define SYSCTL_DID1_PRTNO_6110 0x00740000 ///< LM3S6110 00287 #define SYSCTL_DID1_PRTNO_6420 0x00A50000 ///< LM3S6420 00288 #define SYSCTL_DID1_PRTNO_6422 0x00820000 ///< LM3S6422 00289 #define SYSCTL_DID1_PRTNO_6432 0x00750000 ///< LM3S6432 00290 #define SYSCTL_DID1_PRTNO_6537 0x00760000 ///< LM3S6537 00291 #define SYSCTL_DID1_PRTNO_6610 0x00710000 ///< LM3S6610 00292 #define SYSCTL_DID1_PRTNO_6611 0x00E70000 ///< LM3S6611 00293 #define SYSCTL_DID1_PRTNO_6618 0x00E60000 ///< LM3S6618 00294 #define SYSCTL_DID1_PRTNO_6633 0x00830000 ///< LM3S6633 00295 #define SYSCTL_DID1_PRTNO_6637 0x008B0000 ///< LM3S6637 00296 #define SYSCTL_DID1_PRTNO_6730 0x00A30000 ///< LM3S6730 00297 #define SYSCTL_DID1_PRTNO_6753 0x00770000 ///< LM3S6753 00298 #define SYSCTL_DID1_PRTNO_6911 0x00E90000 ///< LM3S6911 00299 #define SYSCTL_DID1_PRTNO_6918 0x00E80000 ///< LM3S6918 00300 #define SYSCTL_DID1_PRTNO_6938 0x00890000 ///< LM3S6938 00301 #define SYSCTL_DID1_PRTNO_6950 0x00720000 ///< LM3S6950 00302 #define SYSCTL_DID1_PRTNO_6952 0x00780000 ///< LM3S6952 00303 #define SYSCTL_DID1_PRTNO_6965 0x00730000 ///< LM3S6965 00304 #define SYSCTL_DID1_PRTNO_8530 0x00640000 ///< LM3S8530 00305 #define SYSCTL_DID1_PRTNO_8538 0x008E0000 ///< LM3S8538 00306 #define SYSCTL_DID1_PRTNO_8630 0x00610000 ///< LM3S8630 00307 #define SYSCTL_DID1_PRTNO_8730 0x00630000 ///< LM3S8730 00308 #define SYSCTL_DID1_PRTNO_8733 0x008D0000 ///< LM3S8733 00309 #define SYSCTL_DID1_PRTNO_8738 0x00860000 ///< LM3S8738 00310 #define SYSCTL_DID1_PRTNO_8930 0x00650000 ///< LM3S8930 00311 #define SYSCTL_DID1_PRTNO_8933 0x008C0000 ///< LM3S8933 00312 #define SYSCTL_DID1_PRTNO_8938 0x00880000 ///< LM3S8938 00313 #define SYSCTL_DID1_PRTNO_8962 0x00A60000 ///< LM3S8962 00314 #define SYSCTL_DID1_PRTNO_8970 0x00620000 ///< LM3S8970 00315 #define SYSCTL_DID1_PRTNO_8971 0x00D70000 ///< LM3S8971 00316 #define SYSCTL_DID1_PRTNO_9790 0x00670000 ///< LM3S9790 00317 #define SYSCTL_DID1_PRTNO_9792 0x006B0000 ///< LM3S9792 00318 #define SYSCTL_DID1_PRTNO_9997 0x00200000 ///< LM3S9997 00319 #define SYSCTL_DID1_PRTNO_9B90 0x00660000 ///< LM3S9B90 00320 #define SYSCTL_DID1_PRTNO_9B92 0x006A0000 ///< LM3S9B92 00321 #define SYSCTL_DID1_PRTNO_9B95 0x006E0000 ///< LM3S9B95 00322 #define SYSCTL_DID1_PRTNO_9B96 0x006F0000 ///< LM3S9B96 00323 #define SYSCTL_DID1_PRTNO_9L97 0x00180000 ///< LM3S9L97 00324 #define SYSCTL_DID1_PINCNT_M 0x0000E000 ///< Package Pin Count 00325 #define SYSCTL_DID1_PINCNT_28 0x00000000 ///< 28 pin package 00326 #define SYSCTL_DID1_PINCNT_48 0x00002000 ///< 48 pin package 00327 #define SYSCTL_DID1_PINCNT_100 0x00004000 ///< 100-pin package 00328 #define SYSCTL_DID1_PINCNT_64 0x00006000 ///< 64-pin package 00329 #define SYSCTL_DID1_TEMP_M 0x000000E0 ///< Temperature Range 00330 #define SYSCTL_DID1_TEMP_C 0x00000000 ///< Commercial temperature range (0C 00331 00332 #define SYSCTL_DID1_TEMP_I 0x00000020 ///< Industrial temperature range 00333 00334 #define SYSCTL_DID1_TEMP_E 0x00000040 ///< Extended temperature range (-40C 00335 00336 #define SYSCTL_DID1_PKG_M 0x00000018 ///< Package Type 00337 #define SYSCTL_DID1_PKG_SOIC 0x00000000 ///< SOIC package 00338 #define SYSCTL_DID1_PKG_QFP 0x00000008 ///< LQFP package 00339 #define SYSCTL_DID1_PKG_BGA 0x00000010 ///< BGA package 00340 #define SYSCTL_DID1_PKG_QFN 0x00000018 ///< QFN package 00341 #define SYSCTL_DID1_ROHS 0x00000004 ///< RoHS-Compliance 00342 #define SYSCTL_DID1_QUAL_M 0x00000003 ///< Qualification Status 00343 #define SYSCTL_DID1_QUAL_ES 0x00000000 ///< Engineering Sample (unqualified) 00344 #define SYSCTL_DID1_QUAL_PP 0x00000001 ///< Pilot Production (unqualified) 00345 #define SYSCTL_DID1_QUAL_FQ 0x00000002 ///< Fully Qualified 00346 #define SYSCTL_DID1_PRTNO_S 16 ///< Part number shift 00347 /*\}*/ 00348 00352 /*\{*/ 00353 #define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 ///< SRAM Size 00354 #define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 ///< 2 KB of SRAM 00355 #define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 ///< 4 KB of SRAM 00356 #define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 ///< 6 KB of SRAM 00357 #define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 ///< 8 KB of SRAM 00358 #define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 ///< 12 KB of SRAM 00359 #define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 ///< 16 KB of SRAM 00360 #define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 ///< 20 KB of SRAM 00361 #define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 ///< 24 KB of SRAM 00362 #define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 ///< 32 KB of SRAM 00363 #define SYSCTL_DC0_SRAMSZ_48KB 0x00BF0000 ///< 48 KB of SRAM 00364 #define SYSCTL_DC0_SRAMSZ_64KB 0x00FF0000 ///< 64 KB of SRAM 00365 #define SYSCTL_DC0_SRAMSZ_96KB 0x017F0000 ///< 96 KB of SRAM 00366 #define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF ///< Flash Size 00367 #define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 ///< 8 KB of Flash 00368 #define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 ///< 16 KB of Flash 00369 #define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F ///< 32 KB of Flash 00370 #define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F ///< 64 KB of Flash 00371 #define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F ///< 96 KB of Flash 00372 #define SYSCTL_DC0_FLASHSZ_128K 0x0000003F ///< 128 KB of Flash 00373 #define SYSCTL_DC0_FLASHSZ_256K 0x0000007F ///< 256 KB of Flash 00374 #define SYSCTL_DC0_SRAMSZ_S 16 ///< SRAM size shift 00375 #define SYSCTL_DC0_FLASHSZ_S 0 ///< Flash size shift 00376 /*\}*/ 00377 00381 /*\{*/ 00382 #define SYSCTL_DC1_WDT1 0x10000000 ///< Watchdog Timer1 Present 00383 #define SYSCTL_DC1_CAN2 0x04000000 ///< CAN Module 2 Present 00384 #define SYSCTL_DC1_CAN1 0x02000000 ///< CAN Module 1 Present 00385 #define SYSCTL_DC1_CAN0 0x01000000 ///< CAN Module 0 Present 00386 #define SYSCTL_DC1_PWM 0x00100000 ///< PWM Module Present 00387 #define SYSCTL_DC1_ADC1 0x00020000 ///< ADC Module 1 Present 00388 #define SYSCTL_DC1_ADC0 0x00010000 ///< ADC Module 0 Present 00389 #define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 ///< System Clock Divider 00390 #define SYSCTL_DC1_MINSYSDIV_100 \ 00391 0x00001000 ///< Divide VCO (400MHZ) by 5 minimum 00392 #define SYSCTL_DC1_MINSYSDIV_66 0x00002000 ///< Divide VCO (400MHZ) by 2*2 + 2 = 00393 00394 #define SYSCTL_DC1_MINSYSDIV_50 0x00003000 ///< Specifies a 50-MHz CPU clock 00395 00396 #define SYSCTL_DC1_MINSYSDIV_25 0x00007000 ///< Specifies a 25-MHz clock with a 00397 00398 #define SYSCTL_DC1_MINSYSDIV_20 0x00009000 ///< Specifies a 20-MHz clock with a 00399 00400 #define SYSCTL_DC1_ADCSPD_M 0x00000F00 ///< Max ADC Speed 00401 #define SYSCTL_DC1_ADCSPD_125K 0x00000000 ///< 125Ksps ADC 00402 #define SYSCTL_DC1_ADCSPD_250K 0x00000100 ///< 250K samples/second 00403 #define SYSCTL_DC1_ADCSPD_500K 0x00000200 ///< 500K samples/second 00404 #define SYSCTL_DC1_ADCSPD_1M 0x00000300 ///< 1M samples/second 00405 #define SYSCTL_DC1_ADC1SPD_M 0x00000C00 ///< Max ADC1 Speed 00406 #define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 ///< 1M samples/second 00407 #define SYSCTL_DC1_ADC0SPD_M 0x00000300 ///< Max ADC0 Speed 00408 #define SYSCTL_DC1_ADC0SPD_1M 0x00000300 ///< 1M samples/second 00409 #define SYSCTL_DC1_MPU 0x00000080 ///< MPU Present 00410 #define SYSCTL_DC1_HIB 0x00000040 ///< Hibernation Module Present 00411 #define SYSCTL_DC1_TEMP 0x00000020 ///< Temp Sensor Present 00412 #define SYSCTL_DC1_PLL 0x00000010 ///< PLL Present 00413 #define SYSCTL_DC1_WDT0 0x00000008 ///< Watchdog Timer 0 Present 00414 #define SYSCTL_DC1_SWO 0x00000004 ///< SWO Trace Port Present 00415 #define SYSCTL_DC1_SWD 0x00000002 ///< SWD Present 00416 #define SYSCTL_DC1_JTAG 0x00000001 ///< JTAG Present 00417 /*\}*/ 00418 00422 /*\{*/ 00423 #define SYSCTL_DC2_EPI0 0x40000000 ///< EPI Module 0 Present 00424 #define SYSCTL_DC2_I2S0 0x10000000 ///< I2S Module 0 Present 00425 #define SYSCTL_DC2_COMP2 0x04000000 ///< Analog Comparator 2 Present 00426 #define SYSCTL_DC2_COMP1 0x02000000 ///< Analog Comparator 1 Present 00427 #define SYSCTL_DC2_COMP0 0x01000000 ///< Analog Comparator 0 Present 00428 #define SYSCTL_DC2_TIMER3 0x00080000 ///< Timer Module 3 Present 00429 #define SYSCTL_DC2_TIMER2 0x00040000 ///< Timer Module 2 Present 00430 #define SYSCTL_DC2_TIMER1 0x00020000 ///< Timer Module 1 Present 00431 #define SYSCTL_DC2_TIMER0 0x00010000 ///< Timer Module 0 Present 00432 #define SYSCTL_DC2_I2C1 0x00004000 ///< I2C Module 1 Present 00433 #define SYSCTL_DC2_I2C0 0x00001000 ///< I2C Module 0 Present 00434 #define SYSCTL_DC2_QEI1 0x00000200 ///< QEI Module 1 Present 00435 #define SYSCTL_DC2_QEI0 0x00000100 ///< QEI Module 0 Present 00436 #define SYSCTL_DC2_SSI1 0x00000020 ///< SSI Module 1 Present 00437 #define SYSCTL_DC2_SSI0 0x00000010 ///< SSI Module 0 Present 00438 #define SYSCTL_DC2_UART2 0x00000004 ///< UART Module 2 Present 00439 #define SYSCTL_DC2_UART1 0x00000002 ///< UART Module 1 Present 00440 #define SYSCTL_DC2_UART0 0x00000001 ///< UART Module 0 Present 00441 /*\}*/ 00442 00446 /*\{*/ 00447 #define SYSCTL_DC3_32KHZ 0x80000000 ///< 32KHz Input Clock Available 00448 #define SYSCTL_DC3_CCP5 0x20000000 ///< CCP5 Pin Present 00449 #define SYSCTL_DC3_CCP4 0x10000000 ///< CCP4 Pin Present 00450 #define SYSCTL_DC3_CCP3 0x08000000 ///< CCP3 Pin Present 00451 #define SYSCTL_DC3_CCP2 0x04000000 ///< CCP2 Pin Present 00452 #define SYSCTL_DC3_CCP1 0x02000000 ///< CCP1 Pin Present 00453 #define SYSCTL_DC3_CCP0 0x01000000 ///< CCP0 Pin Present 00454 #define SYSCTL_DC3_ADC0AIN7 0x00800000 ///< ADC Module 0 AIN7 Pin Present 00455 #define SYSCTL_DC3_ADC0AIN6 0x00400000 ///< ADC Module 0 AIN6 Pin Present 00456 #define SYSCTL_DC3_ADC0AIN5 0x00200000 ///< ADC Module 0 AIN5 Pin Present 00457 #define SYSCTL_DC3_ADC0AIN4 0x00100000 ///< ADC Module 0 AIN4 Pin Present 00458 #define SYSCTL_DC3_ADC0AIN3 0x00080000 ///< ADC Module 0 AIN3 Pin Present 00459 #define SYSCTL_DC3_ADC0AIN2 0x00040000 ///< ADC Module 0 AIN2 Pin Present 00460 #define SYSCTL_DC3_ADC0AIN1 0x00020000 ///< ADC Module 0 AIN1 Pin Present 00461 #define SYSCTL_DC3_ADC0AIN0 0x00010000 ///< ADC Module 0 AIN0 Pin Present 00462 #define SYSCTL_DC3_PWMFAULT 0x00008000 ///< PWM Fault Pin Present 00463 #define SYSCTL_DC3_C2O 0x00004000 ///< C2o Pin Present 00464 #define SYSCTL_DC3_C2PLUS 0x00002000 ///< C2+ Pin Present 00465 #define SYSCTL_DC3_C2MINUS 0x00001000 ///< C2- Pin Present 00466 #define SYSCTL_DC3_C1O 0x00000800 ///< C1o Pin Present 00467 #define SYSCTL_DC3_C1PLUS 0x00000400 ///< C1+ Pin Present 00468 #define SYSCTL_DC3_C1MINUS 0x00000200 ///< C1- Pin Present 00469 #define SYSCTL_DC3_C0O 0x00000100 ///< C0o Pin Present 00470 #define SYSCTL_DC3_C0PLUS 0x00000080 ///< C0+ Pin Present 00471 #define SYSCTL_DC3_C0MINUS 0x00000040 ///< C0- Pin Present 00472 #define SYSCTL_DC3_PWM5 0x00000020 ///< PWM5 Pin Present 00473 #define SYSCTL_DC3_PWM4 0x00000010 ///< PWM4 Pin Present 00474 #define SYSCTL_DC3_PWM3 0x00000008 ///< PWM3 Pin Present 00475 #define SYSCTL_DC3_PWM2 0x00000004 ///< PWM2 Pin Present 00476 #define SYSCTL_DC3_PWM1 0x00000002 ///< PWM1 Pin Present 00477 #define SYSCTL_DC3_PWM0 0x00000001 ///< PWM0 Pin Present 00478 /*\}*/ 00479 00483 /*\{*/ 00484 #define SYSCTL_DC4_ETH 0x50000000 ///< Ethernet present 00485 #define SYSCTL_DC4_EPHY0 0x40000000 ///< Ethernet PHY Layer 0 Present 00486 #define SYSCTL_DC4_EMAC0 0x10000000 ///< Ethernet MAC Layer 0 Present 00487 #define SYSCTL_DC4_E1588 0x01000000 ///< 1588 Capable 00488 #define SYSCTL_DC4_PICAL 0x00040000 ///< PIOSC Calibrate 00489 #define SYSCTL_DC4_CCP7 0x00008000 ///< CCP7 Pin Present 00490 #define SYSCTL_DC4_CCP6 0x00004000 ///< CCP6 Pin Present 00491 #define SYSCTL_DC4_UDMA 0x00002000 ///< Micro-DMA Module Present 00492 #define SYSCTL_DC4_ROM 0x00001000 ///< Internal Code ROM Present 00493 #define SYSCTL_DC4_GPIOJ 0x00000100 ///< GPIO Port J Present 00494 #define SYSCTL_DC4_GPIOH 0x00000080 ///< GPIO Port H Present 00495 #define SYSCTL_DC4_GPIOG 0x00000040 ///< GPIO Port G Present 00496 #define SYSCTL_DC4_GPIOF 0x00000020 ///< GPIO Port F Present 00497 #define SYSCTL_DC4_GPIOE 0x00000010 ///< GPIO Port E Present 00498 #define SYSCTL_DC4_GPIOD 0x00000008 ///< GPIO Port D Present 00499 #define SYSCTL_DC4_GPIOC 0x00000004 ///< GPIO Port C Present 00500 #define SYSCTL_DC4_GPIOB 0x00000002 ///< GPIO Port B Present 00501 #define SYSCTL_DC4_GPIOA 0x00000001 ///< GPIO Port A Present 00502 /*\}*/ 00503 00507 /*\{*/ 00508 #define SYSCTL_DC5_PWMFAULT3 0x08000000 ///< PWM Fault 3 Pin Present 00509 #define SYSCTL_DC5_PWMFAULT2 0x04000000 ///< PWM Fault 2 Pin Present 00510 #define SYSCTL_DC5_PWMFAULT1 0x02000000 ///< PWM Fault 1 Pin Present 00511 #define SYSCTL_DC5_PWMFAULT0 0x01000000 ///< PWM Fault 0 Pin Present 00512 #define SYSCTL_DC5_PWMEFLT 0x00200000 ///< PWM Extended Fault Active 00513 #define SYSCTL_DC5_PWMESYNC 0x00100000 ///< PWM Extended SYNC Active 00514 #define SYSCTL_DC5_PWM7 0x00000080 ///< PWM7 Pin Present 00515 #define SYSCTL_DC5_PWM6 0x00000040 ///< PWM6 Pin Present 00516 #define SYSCTL_DC5_PWM5 0x00000020 ///< PWM5 Pin Present 00517 #define SYSCTL_DC5_PWM4 0x00000010 ///< PWM4 Pin Present 00518 #define SYSCTL_DC5_PWM3 0x00000008 ///< PWM3 Pin Present 00519 #define SYSCTL_DC5_PWM2 0x00000004 ///< PWM2 Pin Present 00520 #define SYSCTL_DC5_PWM1 0x00000002 ///< PWM1 Pin Present 00521 #define SYSCTL_DC5_PWM0 0x00000001 ///< PWM0 Pin Present 00522 /*\}*/ 00523 00527 /*\{*/ 00528 #define SYSCTL_DC6_USB0PHY 0x00000010 ///< USB Module 0 PHY Present 00529 #define SYSCTL_DC6_USB0_M 0x00000003 ///< USB Module 0 Present 00530 #define SYSCTL_DC6_USB0_DEV 0x00000001 ///< USB0 is Device Only 00531 #define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 ///< USB is Device or Host 00532 #define SYSCTL_DC6_USB0_OTG 0x00000003 ///< USB0 is OTG 00533 /*\}*/ 00534 00538 /*\{*/ 00539 #define SYSCTL_DC7_DMACH30 0x40000000 ///< SW 00540 #define SYSCTL_DC7_DMACH29 0x20000000 ///< I2S0_TX / CAN1_TX 00541 #define SYSCTL_DC7_DMACH28 0x10000000 ///< I2S0_RX / CAN1_RX 00542 #define SYSCTL_DC7_DMACH27 0x08000000 ///< CAN1_TX / ADC1_SS3 00543 #define SYSCTL_DC7_DMACH26 0x04000000 ///< CAN1_RX / ADC1_SS2 00544 #define SYSCTL_DC7_DMACH25 0x02000000 ///< SSI1_TX / ADC1_SS1 00545 #define SYSCTL_DC7_SSI1_TX 0x02000000 ///< SSI1 TX on uDMA Ch25 00546 #define SYSCTL_DC7_SSI1_RX 0x01000000 ///< SSI1 RX on uDMA Ch24 00547 #define SYSCTL_DC7_DMACH24 0x01000000 ///< SSI1_RX / ADC1_SS0 00548 #define SYSCTL_DC7_UART1_TX 0x00800000 ///< UART1 TX on uDMA Ch23 00549 #define SYSCTL_DC7_DMACH23 0x00800000 ///< UART1_TX / CAN2_TX 00550 #define SYSCTL_DC7_DMACH22 0x00400000 ///< UART1_RX / CAN2_RX 00551 #define SYSCTL_DC7_UART1_RX 0x00400000 ///< UART1 RX on uDMA Ch22 00552 #define SYSCTL_DC7_DMACH21 0x00200000 ///< Timer1B / EPI0_WFIFO 00553 #define SYSCTL_DC7_DMACH20 0x00100000 ///< Timer1A / EPI0_NBRFIFO 00554 #define SYSCTL_DC7_DMACH19 0x00080000 ///< Timer0B / Timer1B 00555 #define SYSCTL_DC7_DMACH18 0x00040000 ///< Timer0A / Timer1A 00556 #define SYSCTL_DC7_DMACH17 0x00020000 ///< ADC0_SS3 00557 #define SYSCTL_DC7_DMACH16 0x00010000 ///< ADC0_SS2 00558 #define SYSCTL_DC7_DMACH15 0x00008000 ///< ADC0_SS1 / Timer2B 00559 #define SYSCTL_DC7_DMACH14 0x00004000 ///< ADC0_SS0 / Timer2A 00560 #define SYSCTL_DC7_DMACH13 0x00002000 ///< CAN0_TX / UART2_TX 00561 #define SYSCTL_DC7_DMACH12 0x00001000 ///< CAN0_RX / UART2_RX 00562 #define SYSCTL_DC7_SSI0_TX 0x00000800 ///< SSI0 TX on uDMA Ch11 00563 #define SYSCTL_DC7_DMACH11 0x00000800 ///< SSI0_TX / SSI1_TX 00564 #define SYSCTL_DC7_SSI0_RX 0x00000400 ///< SSI0 RX on uDMA Ch10 00565 #define SYSCTL_DC7_DMACH10 0x00000400 ///< SSI0_RX / SSI1_RX 00566 #define SYSCTL_DC7_UART0_TX 0x00000200 ///< UART0 TX on uDMA Ch9 00567 #define SYSCTL_DC7_DMACH9 0x00000200 ///< UART0_TX / UART1_TX 00568 #define SYSCTL_DC7_DMACH8 0x00000100 ///< UART0_RX / UART1_RX 00569 #define SYSCTL_DC7_UART0_RX 0x00000100 ///< UART0 RX on uDMA Ch8 00570 #define SYSCTL_DC7_DMACH7 0x00000080 ///< ETH_TX / Timer2B 00571 #define SYSCTL_DC7_DMACH6 0x00000040 ///< ETH_RX / Timer2A 00572 #define SYSCTL_DC7_DMACH5 0x00000020 ///< USB_EP3_TX / Timer2B 00573 #define SYSCTL_DC7_USB_EP3_TX 0x00000020 ///< USB EP3 TX on uDMA Ch5 00574 #define SYSCTL_DC7_USB_EP3_RX 0x00000010 ///< USB EP3 RX on uDMA Ch4 00575 #define SYSCTL_DC7_DMACH4 0x00000010 ///< USB_EP3_RX / Timer2A 00576 #define SYSCTL_DC7_USB_EP2_TX 0x00000008 ///< USB EP2 TX on uDMA Ch3 00577 #define SYSCTL_DC7_DMACH3 0x00000008 ///< USB_EP2_TX / Timer3B 00578 #define SYSCTL_DC7_USB_EP2_RX 0x00000004 ///< USB EP2 RX on uDMA Ch2 00579 #define SYSCTL_DC7_DMACH2 0x00000004 ///< USB_EP2_RX / Timer3A 00580 #define SYSCTL_DC7_USB_EP1_TX 0x00000002 ///< USB EP1 TX on uDMA Ch1 00581 #define SYSCTL_DC7_DMACH1 0x00000002 ///< USB_EP1_TX / UART2_TX 00582 #define SYSCTL_DC7_DMACH0 0x00000001 ///< USB_EP1_RX / UART2_RX 00583 #define SYSCTL_DC7_USB_EP1_RX 0x00000001 ///< USB EP1 RX on uDMA Ch0 00584 /*\}*/ 00585 00589 /*\{*/ 00590 #define SYSCTL_DC8_ADC1AIN15 0x80000000 ///< ADC Module 1 AIN15 Pin Present 00591 #define SYSCTL_DC8_ADC1AIN14 0x40000000 ///< ADC Module 1 AIN14 Pin Present 00592 #define SYSCTL_DC8_ADC1AIN13 0x20000000 ///< ADC Module 1 AIN13 Pin Present 00593 #define SYSCTL_DC8_ADC1AIN12 0x10000000 ///< ADC Module 1 AIN12 Pin Present 00594 #define SYSCTL_DC8_ADC1AIN11 0x08000000 ///< ADC Module 1 AIN11 Pin Present 00595 #define SYSCTL_DC8_ADC1AIN10 0x04000000 ///< ADC Module 1 AIN10 Pin Present 00596 #define SYSCTL_DC8_ADC1AIN9 0x02000000 ///< ADC Module 1 AIN9 Pin Present 00597 #define SYSCTL_DC8_ADC1AIN8 0x01000000 ///< ADC Module 1 AIN8 Pin Present 00598 #define SYSCTL_DC8_ADC1AIN7 0x00800000 ///< ADC Module 1 AIN7 Pin Present 00599 #define SYSCTL_DC8_ADC1AIN6 0x00400000 ///< ADC Module 1 AIN6 Pin Present 00600 #define SYSCTL_DC8_ADC1AIN5 0x00200000 ///< ADC Module 1 AIN5 Pin Present 00601 #define SYSCTL_DC8_ADC1AIN4 0x00100000 ///< ADC Module 1 AIN4 Pin Present 00602 #define SYSCTL_DC8_ADC1AIN3 0x00080000 ///< ADC Module 1 AIN3 Pin Present 00603 #define SYSCTL_DC8_ADC1AIN2 0x00040000 ///< ADC Module 1 AIN2 Pin Present 00604 #define SYSCTL_DC8_ADC1AIN1 0x00020000 ///< ADC Module 1 AIN1 Pin Present 00605 #define SYSCTL_DC8_ADC1AIN0 0x00010000 ///< ADC Module 1 AIN0 Pin Present 00606 #define SYSCTL_DC8_ADC0AIN15 0x00008000 ///< ADC Module 0 AIN15 Pin Present 00607 #define SYSCTL_DC8_ADC0AIN14 0x00004000 ///< ADC Module 0 AIN14 Pin Present 00608 #define SYSCTL_DC8_ADC0AIN13 0x00002000 ///< ADC Module 0 AIN13 Pin Present 00609 #define SYSCTL_DC8_ADC0AIN12 0x00001000 ///< ADC Module 0 AIN12 Pin Present 00610 #define SYSCTL_DC8_ADC0AIN11 0x00000800 ///< ADC Module 0 AIN11 Pin Present 00611 #define SYSCTL_DC8_ADC0AIN10 0x00000400 ///< ADC Module 0 AIN10 Pin Present 00612 #define SYSCTL_DC8_ADC0AIN9 0x00000200 ///< ADC Module 0 AIN9 Pin Present 00613 #define SYSCTL_DC8_ADC0AIN8 0x00000100 ///< ADC Module 0 AIN8 Pin Present 00614 #define SYSCTL_DC8_ADC0AIN7 0x00000080 ///< ADC Module 0 AIN7 Pin Present 00615 #define SYSCTL_DC8_ADC0AIN6 0x00000040 ///< ADC Module 0 AIN6 Pin Present 00616 #define SYSCTL_DC8_ADC0AIN5 0x00000020 ///< ADC Module 0 AIN5 Pin Present 00617 #define SYSCTL_DC8_ADC0AIN4 0x00000010 ///< ADC Module 0 AIN4 Pin Present 00618 #define SYSCTL_DC8_ADC0AIN3 0x00000008 ///< ADC Module 0 AIN3 Pin Present 00619 #define SYSCTL_DC8_ADC0AIN2 0x00000004 ///< ADC Module 0 AIN2 Pin Present 00620 #define SYSCTL_DC8_ADC0AIN1 0x00000002 ///< ADC Module 0 AIN1 Pin Present 00621 #define SYSCTL_DC8_ADC0AIN0 0x00000001 ///< ADC Module 0 AIN0 Pin Present 00622 /*\}*/ 00623 00627 /*\{*/ 00628 #define SYSCTL_PBORCTL_BORTIM_M 0x0000FFFC ///< BOR Time Delay 00629 #define SYSCTL_PBORCTL_BORIOR 0x00000002 ///< BOR Interrupt or Reset 00630 #define SYSCTL_PBORCTL_BORWT 0x00000001 ///< BOR Wait and Check for Noise 00631 #define SYSCTL_PBORCTL_BORTIM_S 2 00632 /*\}*/ 00633 00637 /*\{*/ 00638 #define SYSCTL_LDOPCTL_M 0x0000003F ///< LDO Output Voltage 00639 #define SYSCTL_LDOPCTL_2_50V 0x00000000 ///< 2.50 00640 #define SYSCTL_LDOPCTL_2_45V 0x00000001 ///< 2.45 00641 #define SYSCTL_LDOPCTL_2_40V 0x00000002 ///< 2.40 00642 #define SYSCTL_LDOPCTL_2_35V 0x00000003 ///< 2.35 00643 #define SYSCTL_LDOPCTL_2_30V 0x00000004 ///< 2.30 00644 #define SYSCTL_LDOPCTL_2_25V 0x00000005 ///< 2.25 00645 #define SYSCTL_LDOPCTL_2_75V 0x0000001B ///< 2.75 00646 #define SYSCTL_LDOPCTL_2_70V 0x0000001C ///< 2.70 00647 #define SYSCTL_LDOPCTL_2_65V 0x0000001D ///< 2.65 00648 #define SYSCTL_LDOPCTL_2_60V 0x0000001E ///< 2.60 00649 #define SYSCTL_LDOPCTL_2_55V 0x0000001F ///< 2.55 00650 /*\}*/ 00651 00655 /*\{*/ 00656 #define SYSCTL_SRCR0_WDT1 0x10000000 ///< WDT1 Reset Control 00657 #define SYSCTL_SRCR0_CAN2 0x04000000 ///< CAN2 Reset Control 00658 #define SYSCTL_SRCR0_CAN1 0x02000000 ///< CAN1 Reset Control 00659 #define SYSCTL_SRCR0_CAN0 0x01000000 ///< CAN0 Reset Control 00660 #define SYSCTL_SRCR0_PWM 0x00100000 ///< PWM Reset Control 00661 #define SYSCTL_SRCR0_ADC1 0x00020000 ///< ADC1 Reset Control 00662 #define SYSCTL_SRCR0_ADC0 0x00010000 ///< ADC0 Reset Control 00663 #define SYSCTL_SRCR0_HIB 0x00000040 ///< HIB Reset Control 00664 #define SYSCTL_SRCR0_WDT0 0x00000008 ///< WDT0 Reset Control 00665 /*\}*/ 00666 00670 /*\{*/ 00671 #define SYSCTL_SRCR1_EPI0 0x40000000 ///< EPI0 Reset Control 00672 #define SYSCTL_SRCR1_I2S0 0x10000000 ///< I2S0 Reset Control 00673 #define SYSCTL_SRCR1_COMP2 0x04000000 ///< Analog Comp 2 Reset Control 00674 #define SYSCTL_SRCR1_COMP1 0x02000000 ///< Analog Comp 1 Reset Control 00675 #define SYSCTL_SRCR1_COMP0 0x01000000 ///< Analog Comp 0 Reset Control 00676 #define SYSCTL_SRCR1_TIMER3 0x00080000 ///< Timer 3 Reset Control 00677 #define SYSCTL_SRCR1_TIMER2 0x00040000 ///< Timer 2 Reset Control 00678 #define SYSCTL_SRCR1_TIMER1 0x00020000 ///< Timer 1 Reset Control 00679 #define SYSCTL_SRCR1_TIMER0 0x00010000 ///< Timer 0 Reset Control 00680 #define SYSCTL_SRCR1_I2C1 0x00004000 ///< I2C1 Reset Control 00681 #define SYSCTL_SRCR1_I2C0 0x00001000 ///< I2C0 Reset Control 00682 #define SYSCTL_SRCR1_QEI1 0x00000200 ///< QEI1 Reset Control 00683 #define SYSCTL_SRCR1_QEI0 0x00000100 ///< QEI0 Reset Control 00684 #define SYSCTL_SRCR1_SSI1 0x00000020 ///< SSI1 Reset Control 00685 #define SYSCTL_SRCR1_SSI0 0x00000010 ///< SSI0 Reset Control 00686 #define SYSCTL_SRCR1_UART2 0x00000004 ///< UART2 Reset Control 00687 #define SYSCTL_SRCR1_UART1 0x00000002 ///< UART1 Reset Control 00688 #define SYSCTL_SRCR1_UART0 0x00000001 ///< UART0 Reset Control 00689 /*\}*/ 00690 00694 /*\{*/ 00695 #define SYSCTL_SRCR2_EPHY0 0x40000000 ///< PHY0 Reset Control 00696 #define SYSCTL_SRCR2_EMAC0 0x10000000 ///< MAC0 Reset Control 00697 #define SYSCTL_SRCR2_USB0 0x00010000 ///< USB0 Reset Control 00698 #define SYSCTL_SRCR2_UDMA 0x00002000 ///< Micro-DMA Reset Control 00699 #define SYSCTL_SRCR2_GPIOJ 0x00000100 ///< Port J Reset Control 00700 #define SYSCTL_SRCR2_GPIOH 0x00000080 ///< Port H Reset Control 00701 #define SYSCTL_SRCR2_GPIOG 0x00000040 ///< Port G Reset Control 00702 #define SYSCTL_SRCR2_GPIOF 0x00000020 ///< Port F Reset Control 00703 #define SYSCTL_SRCR2_GPIOE 0x00000010 ///< Port E Reset Control 00704 #define SYSCTL_SRCR2_GPIOD 0x00000008 ///< Port D Reset Control 00705 #define SYSCTL_SRCR2_GPIOC 0x00000004 ///< Port C Reset Control 00706 #define SYSCTL_SRCR2_GPIOB 0x00000002 ///< Port B Reset Control 00707 #define SYSCTL_SRCR2_GPIOA 0x00000001 ///< Port A Reset Control 00708 /*\}*/ 00709 00713 /*\{*/ 00714 #define SYSCTL_RIS_MOSCPUPRIS 0x00000100 ///< MOSC Power Up Raw Interrupt 00715 00716 #define SYSCTL_RIS_USBPLLLRIS 0x00000080 ///< USB PLL Lock Raw Interrupt 00717 00718 #define SYSCTL_RIS_PLLLRIS 0x00000040 ///< PLL Lock Raw Interrupt Status 00719 #define SYSCTL_RIS_CLRIS 0x00000020 ///< Current Limit Raw Interrupt 00720 00721 #define SYSCTL_RIS_IOFRIS 0x00000010 ///< Internal Oscillator Fault Raw 00722 00723 #define SYSCTL_RIS_MOFRIS 0x00000008 ///< Main Oscillator Fault Raw 00724 00725 #define SYSCTL_RIS_LDORIS 0x00000004 ///< LDO Power Unregulated Raw 00726 00727 #define SYSCTL_RIS_BORRIS 0x00000002 ///< Brown-Out Reset Raw Interrupt 00728 00729 #define SYSCTL_RIS_PLLFRIS 0x00000001 ///< PLL Fault Raw Interrupt Status 00730 /*\}*/ 00731 00735 /*\{*/ 00736 #define SYSCTL_IMC_MOSCPUPIM 0x00000100 ///< MOSC Power Up Interrupt Mask 00737 #define SYSCTL_IMC_USBPLLLIM 0x00000080 ///< USB PLL Lock Interrupt Mask 00738 #define SYSCTL_IMC_PLLLIM 0x00000040 ///< PLL Lock Interrupt Mask 00739 #define SYSCTL_IMC_CLIM 0x00000020 ///< Current Limit Interrupt Mask 00740 #define SYSCTL_IMC_IOFIM 0x00000010 ///< Internal Oscillator Fault 00741 00742 #define SYSCTL_IMC_MOFIM 0x00000008 ///< Main Oscillator Fault Interrupt 00743 00744 #define SYSCTL_IMC_LDOIM 0x00000004 ///< LDO Power Unregulated Interrupt 00745 00746 #define SYSCTL_IMC_BORIM 0x00000002 ///< Brown-Out Reset Interrupt Mask 00747 #define SYSCTL_IMC_PLLFIM 0x00000001 ///< PLL Fault Interrupt Mask 00748 /*\}*/ 00749 00753 /*\{*/ 00754 #define SYSCTL_MISC_MOSCPUPMIS 0x00000100 ///< MOSC Power Up Masked Interrupt 00755 00756 #define SYSCTL_MISC_USBPLLLMIS 0x00000080 ///< USB PLL Lock Masked Interrupt 00757 00758 #define SYSCTL_MISC_PLLLMIS 0x00000040 ///< PLL Lock Masked Interrupt Status 00759 #define SYSCTL_MISC_CLMIS 0x00000020 ///< Current Limit Masked Interrupt 00760 00761 #define SYSCTL_MISC_IOFMIS 0x00000010 ///< Internal Oscillator Fault Masked 00762 00763 #define SYSCTL_MISC_MOFMIS 0x00000008 ///< Main Oscillator Fault Masked 00764 00765 #define SYSCTL_MISC_LDOMIS 0x00000004 ///< LDO Power Unregulated Masked 00766 00767 #define SYSCTL_MISC_BORMIS 0x00000002 ///< BOR Masked Interrupt Status 00768 /*\}*/ 00769 00773 /*\{*/ 00774 #define SYSCTL_RESC_MOSCFAIL 0x00010000 ///< MOSC Failure Reset 00775 #define SYSCTL_RESC_LDO 0x00000020 ///< LDO Reset 00776 #define SYSCTL_RESC_WDT1 0x00000020 ///< Watchdog Timer 1 Reset 00777 #define SYSCTL_RESC_SW 0x00000010 ///< Software Reset 00778 #define SYSCTL_RESC_WDT0 0x00000008 ///< Watchdog Timer 0 Reset 00779 #define SYSCTL_RESC_BOR 0x00000004 ///< Brown-Out Reset 00780 #define SYSCTL_RESC_POR 0x00000002 ///< Power-On Reset 00781 #define SYSCTL_RESC_EXT 0x00000001 ///< External Reset 00782 /*\}*/ 00783 00787 /*\{*/ 00788 #define SYSCTL_RCC_ACG 0x08000000 ///< Auto Clock Gating 00789 #define SYSCTL_RCC_SYSDIV_M 0x07800000 ///< System Clock Divisor 00790 #define SYSCTL_RCC_SYSDIV_2 0x00800000 ///< System clock /2 00791 #define SYSCTL_RCC_SYSDIV_3 0x01000000 ///< System clock /3 00792 #define SYSCTL_RCC_SYSDIV_4 0x01800000 ///< System clock /4 00793 #define SYSCTL_RCC_SYSDIV_5 0x02000000 ///< System clock /5 00794 #define SYSCTL_RCC_SYSDIV_6 0x02800000 ///< System clock /6 00795 #define SYSCTL_RCC_SYSDIV_7 0x03000000 ///< System clock /7 00796 #define SYSCTL_RCC_SYSDIV_8 0x03800000 ///< System clock /8 00797 #define SYSCTL_RCC_SYSDIV_9 0x04000000 ///< System clock /9 00798 #define SYSCTL_RCC_SYSDIV_10 0x04800000 ///< System clock /10 00799 #define SYSCTL_RCC_SYSDIV_11 0x05000000 ///< System clock /11 00800 #define SYSCTL_RCC_SYSDIV_12 0x05800000 ///< System clock /12 00801 #define SYSCTL_RCC_SYSDIV_13 0x06000000 ///< System clock /13 00802 #define SYSCTL_RCC_SYSDIV_14 0x06800000 ///< System clock /14 00803 #define SYSCTL_RCC_SYSDIV_15 0x07000000 ///< System clock /15 00804 #define SYSCTL_RCC_SYSDIV_16 0x07800000 ///< System clock /16 00805 #define SYSCTL_RCC_USESYSDIV 0x00400000 ///< Enable System Clock Divider 00806 #define SYSCTL_RCC_USEPWMDIV 0x00100000 ///< Enable PWM Clock Divisor 00807 #define SYSCTL_RCC_PWMDIV_M 0x000E0000 ///< PWM Unit Clock Divisor 00808 #define SYSCTL_RCC_PWMDIV_2 0x00000000 ///< PWM clock /2 00809 #define SYSCTL_RCC_PWMDIV_4 0x00020000 ///< PWM clock /4 00810 #define SYSCTL_RCC_PWMDIV_8 0x00040000 ///< PWM clock /8 00811 #define SYSCTL_RCC_PWMDIV_16 0x00060000 ///< PWM clock /16 00812 #define SYSCTL_RCC_PWMDIV_32 0x00080000 ///< PWM clock /32 00813 #define SYSCTL_RCC_PWMDIV_64 0x000A0000 ///< PWM clock /64 00814 #define SYSCTL_RCC_PWRDN 0x00002000 ///< PLL Power Down 00815 #define SYSCTL_RCC_OEN 0x00001000 ///< PLL Output Enable 00816 #define SYSCTL_RCC_BYPASS 0x00000800 ///< PLL Bypass 00817 #define SYSCTL_RCC_XTAL_M 0x000007C0 ///< Crystal Value 00818 #define SYSCTL_RCC_XTAL_1MHZ 0x00000000 ///< 1 MHz 00819 #define SYSCTL_RCC_XTAL_1_84MHZ 0x00000040 ///< 1.8432 MHz 00820 #define SYSCTL_RCC_XTAL_2MHZ 0x00000080 ///< 2 MHz 00821 #define SYSCTL_RCC_XTAL_2_45MHZ 0x000000C0 ///< 2.4576 MHz 00822 #define SYSCTL_RCC_XTAL_3_57MHZ 0x00000100 ///< 3.579545 MHz 00823 #define SYSCTL_RCC_XTAL_3_68MHZ 0x00000140 ///< 3.6864 MHz 00824 #define SYSCTL_RCC_XTAL_4MHZ 0x00000180 ///< 4 MHz 00825 #define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 ///< 4.096 MHz 00826 #define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 ///< 4.9152 MHz 00827 #define SYSCTL_RCC_XTAL_5MHZ 0x00000240 ///< 5 MHz 00828 #define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 ///< 5.12 MHz 00829 #define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 ///< 6 MHz 00830 #define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 ///< 6.144 MHz 00831 #define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 ///< 7.3728 MHz 00832 #define SYSCTL_RCC_XTAL_8MHZ 0x00000380 ///< 8 MHz 00833 #define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 ///< 8.192 MHz 00834 #define SYSCTL_RCC_XTAL_10MHZ 0x00000400 ///< 10 MHz 00835 #define SYSCTL_RCC_XTAL_12MHZ 0x00000440 ///< 12 MHz 00836 #define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 ///< 12.288 MHz 00837 #define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 ///< 13.56 MHz 00838 #define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 ///< 14.31818 MHz 00839 #define SYSCTL_RCC_XTAL_16MHZ 0x00000540 ///< 16 MHz 00840 #define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 ///< 16.384 MHz 00841 #define SYSCTL_RCC_PLLVER 0x00000400 ///< PLL Verification 00842 #define SYSCTL_RCC_OSCSRC_M 0x00000030 ///< Oscillator Source 00843 #define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 ///< MOSC 00844 #define SYSCTL_RCC_OSCSRC_INT 0x00000010 ///< IOSC 00845 #define SYSCTL_RCC_OSCSRC_INT4 0x00000020 ///< IOSC/4 00846 #define SYSCTL_RCC_OSCSRC_30 0x00000030 ///< 30 kHz 00847 #define SYSCTL_RCC_IOSCVER 0x00000008 ///< Internal Oscillator Verification 00848 00849 #define SYSCTL_RCC_MOSCVER 0x00000004 ///< Main Oscillator Verification 00850 00851 #define SYSCTL_RCC_IOSCDIS 0x00000002 ///< Internal Oscillator Disable 00852 #define SYSCTL_RCC_MOSCDIS 0x00000001 ///< Main Oscillator Disable 00853 #define SYSCTL_RCC_SYSDIV_S 23 00854 #define SYSCTL_RCC_PWMDIV_S 17 ///< Shift to the PWMDIV field 00855 #define SYSCTL_RCC_XTAL_S 6 ///< Shift to the XTAL field 00856 #define SYSCTL_RCC_OSCSRC_S 4 ///< Shift to the OSCSRC field 00857 /*\}*/ 00858 00862 /*\{*/ 00863 #define SYSCTL_PLLCFG_OD_M 0x0000C000 ///< PLL OD Value 00864 #define SYSCTL_PLLCFG_OD_1 0x00000000 ///< Divide by 1 00865 #define SYSCTL_PLLCFG_OD_2 0x00004000 ///< Divide by 2 00866 #define SYSCTL_PLLCFG_OD_4 0x00008000 ///< Divide by 4 00867 #define SYSCTL_PLLCFG_F_M 0x00003FE0 ///< PLL F Value 00868 #define SYSCTL_PLLCFG_R_M 0x0000001F ///< PLL R Value 00869 #define SYSCTL_PLLCFG_F_S 5 00870 #define SYSCTL_PLLCFG_R_S 0 00871 /*\}*/ 00872 00877 /*\{*/ 00878 #define SYSCTL_GPIOHSCTL_PORTH 0x00000080 ///< Port H High-Speed 00879 #define SYSCTL_GPIOHSCTL_PORTG 0x00000040 ///< Port G High-Speed 00880 #define SYSCTL_GPIOHSCTL_PORTF 0x00000020 ///< Port F High-Speed 00881 #define SYSCTL_GPIOHSCTL_PORTE 0x00000010 ///< Port E High-Speed 00882 #define SYSCTL_GPIOHSCTL_PORTD 0x00000008 ///< Port D High-Speed 00883 #define SYSCTL_GPIOHSCTL_PORTC 0x00000004 ///< Port C High-Speed 00884 #define SYSCTL_GPIOHSCTL_PORTB 0x00000002 ///< Port B High-Speed 00885 #define SYSCTL_GPIOHSCTL_PORTA 0x00000001 ///< Port A High-Speed 00886 /*\}*/ 00887 00892 /*\{*/ 00893 #define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 ///< Port J Advanced High-Performance 00894 00895 #define SYSCTL_GPIOHBCTL_PORTH 0x00000080 ///< Port H Advanced High-Performance 00896 00897 #define SYSCTL_GPIOHBCTL_PORTG 0x00000040 ///< Port G Advanced High-Performance 00898 00899 #define SYSCTL_GPIOHBCTL_PORTF 0x00000020 ///< Port F Advanced High-Performance 00900 00901 #define SYSCTL_GPIOHBCTL_PORTE 0x00000010 ///< Port E Advanced High-Performance 00902 00903 #define SYSCTL_GPIOHBCTL_PORTD 0x00000008 ///< Port D Advanced High-Performance 00904 00905 #define SYSCTL_GPIOHBCTL_PORTC 0x00000004 ///< Port C Advanced High-Performance 00906 00907 #define SYSCTL_GPIOHBCTL_PORTB 0x00000002 ///< Port B Advanced High-Performance 00908 00909 #define SYSCTL_GPIOHBCTL_PORTA 0x00000001 ///< Port A Advanced High-Performance 00910 00911 /*\}*/ 00912 00916 /*\{*/ 00917 #define SYSCTL_RCC2_USERCC2 0x80000000 ///< Use RCC2 00918 #define SYSCTL_RCC2_DIV400 0x40000000 ///< Divide PLL as 400 MHz vs. 200 00919 00920 #define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 ///< System Clock Divisor 2 00921 #define SYSCTL_RCC2_SYSDIV2_2 0x00800000 ///< System clock /2 00922 #define SYSCTL_RCC2_SYSDIV2_3 0x01000000 ///< System clock /3 00923 #define SYSCTL_RCC2_SYSDIV2_4 0x01800000 ///< System clock /4 00924 #define SYSCTL_RCC2_SYSDIV2_5 0x02000000 ///< System clock /5 00925 #define SYSCTL_RCC2_SYSDIV2_6 0x02800000 ///< System clock /6 00926 #define SYSCTL_RCC2_SYSDIV2_7 0x03000000 ///< System clock /7 00927 #define SYSCTL_RCC2_SYSDIV2_8 0x03800000 ///< System clock /8 00928 #define SYSCTL_RCC2_SYSDIV2_9 0x04000000 ///< System clock /9 00929 #define SYSCTL_RCC2_SYSDIV2_10 0x04800000 ///< System clock /10 00930 #define SYSCTL_RCC2_SYSDIV2_11 0x05000000 ///< System clock /11 00931 #define SYSCTL_RCC2_SYSDIV2_12 0x05800000 ///< System clock /12 00932 #define SYSCTL_RCC2_SYSDIV2_13 0x06000000 ///< System clock /13 00933 #define SYSCTL_RCC2_SYSDIV2_14 0x06800000 ///< System clock /14 00934 #define SYSCTL_RCC2_SYSDIV2_15 0x07000000 ///< System clock /15 00935 #define SYSCTL_RCC2_SYSDIV2_16 0x07800000 ///< System clock /16 00936 #define SYSCTL_RCC2_SYSDIV2_17 0x08000000 ///< System clock /17 00937 #define SYSCTL_RCC2_SYSDIV2_18 0x08800000 ///< System clock /18 00938 #define SYSCTL_RCC2_SYSDIV2_19 0x09000000 ///< System clock /19 00939 #define SYSCTL_RCC2_SYSDIV2_20 0x09800000 ///< System clock /20 00940 #define SYSCTL_RCC2_SYSDIV2_21 0x0A000000 ///< System clock /21 00941 #define SYSCTL_RCC2_SYSDIV2_22 0x0A800000 ///< System clock /22 00942 #define SYSCTL_RCC2_SYSDIV2_23 0x0B000000 ///< System clock /23 00943 #define SYSCTL_RCC2_SYSDIV2_24 0x0B800000 ///< System clock /24 00944 #define SYSCTL_RCC2_SYSDIV2_25 0x0C000000 ///< System clock /25 00945 #define SYSCTL_RCC2_SYSDIV2_26 0x0C800000 ///< System clock /26 00946 #define SYSCTL_RCC2_SYSDIV2_27 0x0D000000 ///< System clock /27 00947 #define SYSCTL_RCC2_SYSDIV2_28 0x0D800000 ///< System clock /28 00948 #define SYSCTL_RCC2_SYSDIV2_29 0x0E000000 ///< System clock /29 00949 #define SYSCTL_RCC2_SYSDIV2_30 0x0E800000 ///< System clock /30 00950 #define SYSCTL_RCC2_SYSDIV2_31 0x0F000000 ///< System clock /31 00951 #define SYSCTL_RCC2_SYSDIV2_32 0x0F800000 ///< System clock /32 00952 #define SYSCTL_RCC2_SYSDIV2_33 0x10000000 ///< System clock /33 00953 #define SYSCTL_RCC2_SYSDIV2_34 0x10800000 ///< System clock /34 00954 #define SYSCTL_RCC2_SYSDIV2_35 0x11000000 ///< System clock /35 00955 #define SYSCTL_RCC2_SYSDIV2_36 0x11800000 ///< System clock /36 00956 #define SYSCTL_RCC2_SYSDIV2_37 0x12000000 ///< System clock /37 00957 #define SYSCTL_RCC2_SYSDIV2_38 0x12800000 ///< System clock /38 00958 #define SYSCTL_RCC2_SYSDIV2_39 0x13000000 ///< System clock /39 00959 #define SYSCTL_RCC2_SYSDIV2_40 0x13800000 ///< System clock /40 00960 #define SYSCTL_RCC2_SYSDIV2_41 0x14000000 ///< System clock /41 00961 #define SYSCTL_RCC2_SYSDIV2_42 0x14800000 ///< System clock /42 00962 #define SYSCTL_RCC2_SYSDIV2_43 0x15000000 ///< System clock /43 00963 #define SYSCTL_RCC2_SYSDIV2_44 0x15800000 ///< System clock /44 00964 #define SYSCTL_RCC2_SYSDIV2_45 0x16000000 ///< System clock /45 00965 #define SYSCTL_RCC2_SYSDIV2_46 0x16800000 ///< System clock /46 00966 #define SYSCTL_RCC2_SYSDIV2_47 0x17000000 ///< System clock /47 00967 #define SYSCTL_RCC2_SYSDIV2_48 0x17800000 ///< System clock /48 00968 #define SYSCTL_RCC2_SYSDIV2_49 0x18000000 ///< System clock /49 00969 #define SYSCTL_RCC2_SYSDIV2_50 0x18800000 ///< System clock /50 00970 #define SYSCTL_RCC2_SYSDIV2_51 0x19000000 ///< System clock /51 00971 #define SYSCTL_RCC2_SYSDIV2_52 0x19800000 ///< System clock /52 00972 #define SYSCTL_RCC2_SYSDIV2_53 0x1A000000 ///< System clock /53 00973 #define SYSCTL_RCC2_SYSDIV2_54 0x1A800000 ///< System clock /54 00974 #define SYSCTL_RCC2_SYSDIV2_55 0x1B000000 ///< System clock /55 00975 #define SYSCTL_RCC2_SYSDIV2_56 0x1B800000 ///< System clock /56 00976 #define SYSCTL_RCC2_SYSDIV2_57 0x1C000000 ///< System clock /57 00977 #define SYSCTL_RCC2_SYSDIV2_58 0x1C800000 ///< System clock /58 00978 #define SYSCTL_RCC2_SYSDIV2_59 0x1D000000 ///< System clock /59 00979 #define SYSCTL_RCC2_SYSDIV2_60 0x1D800000 ///< System clock /60 00980 #define SYSCTL_RCC2_SYSDIV2_61 0x1E000000 ///< System clock /61 00981 #define SYSCTL_RCC2_SYSDIV2_62 0x1E800000 ///< System clock /62 00982 #define SYSCTL_RCC2_SYSDIV2_63 0x1F000000 ///< System clock /63 00983 #define SYSCTL_RCC2_SYSDIV2_64 0x1F800000 ///< System clock /64 00984 #define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 ///< Additional LSB for SYSDIV2 00985 #define SYSCTL_RCC2_USBPWRDN 0x00004000 ///< Power-Down USB PLL 00986 #define SYSCTL_RCC2_PWRDN2 0x00002000 ///< Power-Down PLL 2 00987 #define SYSCTL_RCC2_BYPASS2 0x00000800 ///< PLL Bypass 2 00988 #define SYSCTL_RCC2_OSCSRC2_M 0x00000070 ///< Oscillator Source 2 00989 #define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 ///< MOSC 00990 #define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 ///< PIOSC 00991 #define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 ///< PIOSC/4 00992 #define SYSCTL_RCC2_OSCSRC2_30 0x00000030 ///< 30 kHz 00993 #define SYSCTL_RCC2_OSCSRC2_419 0x00000060 ///< 4.194304 MHz 00994 #define SYSCTL_RCC2_OSCSRC2_32 0x00000070 ///< 32.768 kHz 00995 #define SYSCTL_RCC2_SYSDIV2_S 23 00996 /*\}*/ 00997 01001 /*\{*/ 01002 #define SYSCTL_MOSCCTL_CVAL 0x00000001 ///< Clock Validation for MOSC 01003 /*\}*/ 01004 01008 /*\{*/ 01009 #define SYSCTL_RCGC0_WDT1 0x10000000 ///< WDT1 Clock Gating Control 01010 #define SYSCTL_RCGC0_CAN2 0x04000000 ///< CAN2 Clock Gating Control 01011 #define SYSCTL_RCGC0_CAN1 0x02000000 ///< CAN1 Clock Gating Control 01012 #define SYSCTL_RCGC0_CAN0 0x01000000 ///< CAN0 Clock Gating Control 01013 #define SYSCTL_RCGC0_PWM 0x00100000 ///< PWM Clock Gating Control 01014 #define SYSCTL_RCGC0_ADC1 0x00020000 ///< ADC1 Clock Gating Control 01015 #define SYSCTL_RCGC0_ADC0 0x00010000 ///< ADC0 Clock Gating Control 01016 #define SYSCTL_RCGC0_ADCSPD_M 0x00000F00 ///< ADC Sample Speed 01017 #define SYSCTL_RCGC0_ADCSPD125K 0x00000000 ///< 125K samples/second 01018 #define SYSCTL_RCGC0_ADCSPD250K 0x00000100 ///< 250K samples/second 01019 #define SYSCTL_RCGC0_ADCSPD500K 0x00000200 ///< 500K samples/second 01020 #define SYSCTL_RCGC0_ADCSPD1M 0x00000300 ///< 1M samples/second 01021 #define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 ///< ADC1 Sample Speed 01022 #define SYSCTL_RCGC0_ADC1SPD_125K \ 01023 0x00000000 ///< 125K samples/second 01024 #define SYSCTL_RCGC0_ADC1SPD_250K \ 01025 0x00000400 ///< 250K samples/second 01026 #define SYSCTL_RCGC0_ADC1SPD_500K \ 01027 0x00000800 ///< 500K samples/second 01028 #define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 ///< 1M samples/second 01029 #define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 ///< ADC0 Sample Speed 01030 #define SYSCTL_RCGC0_ADC0SPD_125K \ 01031 0x00000000 ///< 125K samples/second 01032 #define SYSCTL_RCGC0_ADC0SPD_250K \ 01033 0x00000100 ///< 250K samples/second 01034 #define SYSCTL_RCGC0_ADC0SPD_500K \ 01035 0x00000200 ///< 500K samples/second 01036 #define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 ///< 1M samples/second 01037 #define SYSCTL_RCGC0_HIB 0x00000040 ///< HIB Clock Gating Control 01038 #define SYSCTL_RCGC0_WDT0 0x00000008 ///< WDT0 Clock Gating Control 01039 /*\}*/ 01040 01044 /*\{*/ 01045 #define SYSCTL_RCGC1_EPI0 0x40000000 ///< EPI0 Clock Gating 01046 #define SYSCTL_RCGC1_I2S0 0x10000000 ///< I2S0 Clock Gating 01047 #define SYSCTL_RCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating 01048 #define SYSCTL_RCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating 01049 #define SYSCTL_RCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating 01050 #define SYSCTL_RCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control 01051 #define SYSCTL_RCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control 01052 #define SYSCTL_RCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control 01053 #define SYSCTL_RCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control 01054 #define SYSCTL_RCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control 01055 #define SYSCTL_RCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control 01056 #define SYSCTL_RCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control 01057 #define SYSCTL_RCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control 01058 #define SYSCTL_RCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control 01059 #define SYSCTL_RCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control 01060 #define SYSCTL_RCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control 01061 #define SYSCTL_RCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control 01062 #define SYSCTL_RCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control 01063 /*\}*/ 01064 01068 /*\{*/ 01069 #define SYSCTL_RCGC2_EPHY0 0x40000000 ///< PHY0 Clock Gating Control 01070 #define SYSCTL_RCGC2_EMAC0 0x10000000 ///< MAC0 Clock Gating Control 01071 #define SYSCTL_RCGC2_USB0 0x00010000 ///< USB0 Clock Gating Control 01072 #define SYSCTL_RCGC2_UDMA 0x00002000 ///< Micro-DMA Clock Gating Control 01073 #define SYSCTL_RCGC2_GPIOJ 0x00000100 ///< Port J Clock Gating Control 01074 #define SYSCTL_RCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control 01075 #define SYSCTL_RCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control 01076 #define SYSCTL_RCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control 01077 #define SYSCTL_RCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control 01078 #define SYSCTL_RCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control 01079 #define SYSCTL_RCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control 01080 #define SYSCTL_RCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control 01081 #define SYSCTL_RCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control 01082 /*\}*/ 01083 01087 /*\{*/ 01088 #define SYSCTL_SCGC0_WDT1 0x10000000 ///< WDT1 Clock Gating Control 01089 #define SYSCTL_SCGC0_CAN2 0x04000000 ///< CAN2 Clock Gating Control 01090 #define SYSCTL_SCGC0_CAN1 0x02000000 ///< CAN1 Clock Gating Control 01091 #define SYSCTL_SCGC0_CAN0 0x01000000 ///< CAN0 Clock Gating Control 01092 #define SYSCTL_SCGC0_PWM 0x00100000 ///< PWM Clock Gating Control 01093 #define SYSCTL_SCGC0_ADC1 0x00020000 ///< ADC1 Clock Gating Control 01094 #define SYSCTL_SCGC0_ADC0 0x00010000 ///< ADC0 Clock Gating Control 01095 #define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 ///< ADC Sample Speed 01096 #define SYSCTL_SCGC0_ADCSPD125K 0x00000000 ///< 125K samples/second 01097 #define SYSCTL_SCGC0_ADCSPD250K 0x00000100 ///< 250K samples/second 01098 #define SYSCTL_SCGC0_ADCSPD500K 0x00000200 ///< 500K samples/second 01099 #define SYSCTL_SCGC0_ADCSPD1M 0x00000300 ///< 1M samples/second 01100 #define SYSCTL_SCGC0_ADC1SPD_M 0x00000C00 ///< ADC1 Sample Speed 01101 #define SYSCTL_SCGC0_ADC1SPD_125K \ 01102 0x00000000 ///< 125K samples/second 01103 #define SYSCTL_SCGC0_ADC1SPD_250K \ 01104 0x00000400 ///< 250K samples/second 01105 #define SYSCTL_SCGC0_ADC1SPD_500K \ 01106 0x00000800 ///< 500K samples/second 01107 #define SYSCTL_SCGC0_ADC1SPD_1M 0x00000C00 ///< 1M samples/second 01108 #define SYSCTL_SCGC0_ADC0SPD_M 0x00000300 ///< ADC0 Sample Speed 01109 #define SYSCTL_SCGC0_ADC0SPD_125K \ 01110 0x00000000 ///< 125K samples/second 01111 #define SYSCTL_SCGC0_ADC0SPD_250K \ 01112 0x00000100 ///< 250K samples/second 01113 #define SYSCTL_SCGC0_ADC0SPD_500K \ 01114 0x00000200 ///< 500K samples/second 01115 #define SYSCTL_SCGC0_ADC0SPD_1M 0x00000300 ///< 1M samples/second 01116 #define SYSCTL_SCGC0_HIB 0x00000040 ///< HIB Clock Gating Control 01117 #define SYSCTL_SCGC0_WDT0 0x00000008 ///< WDT0 Clock Gating Control 01118 /*\}*/ 01119 01123 /*\{*/ 01124 #define SYSCTL_SCGC1_EPI0 0x40000000 ///< EPI0 Clock Gating 01125 #define SYSCTL_SCGC1_I2S0 0x10000000 ///< I2S0 Clock Gating 01126 #define SYSCTL_SCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating 01127 #define SYSCTL_SCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating 01128 #define SYSCTL_SCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating 01129 #define SYSCTL_SCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control 01130 #define SYSCTL_SCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control 01131 #define SYSCTL_SCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control 01132 #define SYSCTL_SCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control 01133 #define SYSCTL_SCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control 01134 #define SYSCTL_SCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control 01135 #define SYSCTL_SCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control 01136 #define SYSCTL_SCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control 01137 #define SYSCTL_SCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control 01138 #define SYSCTL_SCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control 01139 #define SYSCTL_SCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control 01140 #define SYSCTL_SCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control 01141 #define SYSCTL_SCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control 01142 /*\}*/ 01143 01147 /*\{*/ 01148 #define SYSCTL_SCGC2_EPHY0 0x40000000 ///< PHY0 Clock Gating Control 01149 #define SYSCTL_SCGC2_EMAC0 0x10000000 ///< MAC0 Clock Gating Control 01150 #define SYSCTL_SCGC2_USB0 0x00010000 ///< USB0 Clock Gating Control 01151 #define SYSCTL_SCGC2_UDMA 0x00002000 ///< Micro-DMA Clock Gating Control 01152 #define SYSCTL_SCGC2_GPIOJ 0x00000100 ///< Port J Clock Gating Control 01153 #define SYSCTL_SCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control 01154 #define SYSCTL_SCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control 01155 #define SYSCTL_SCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control 01156 #define SYSCTL_SCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control 01157 #define SYSCTL_SCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control 01158 #define SYSCTL_SCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control 01159 #define SYSCTL_SCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control 01160 #define SYSCTL_SCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control 01161 /*\}*/ 01162 01166 /*\{*/ 01167 #define SYSCTL_DCGC0_WDT1 0x10000000 ///< WDT1 Clock Gating Control 01168 #define SYSCTL_DCGC0_CAN2 0x04000000 ///< CAN2 Clock Gating Control 01169 #define SYSCTL_DCGC0_CAN1 0x02000000 ///< CAN1 Clock Gating Control 01170 #define SYSCTL_DCGC0_CAN0 0x01000000 ///< CAN0 Clock Gating Control 01171 #define SYSCTL_DCGC0_PWM 0x00100000 ///< PWM Clock Gating Control 01172 #define SYSCTL_DCGC0_ADC1 0x00020000 ///< ADC1 Clock Gating Control 01173 #define SYSCTL_DCGC0_ADC0 0x00010000 ///< ADC0 Clock Gating Control 01174 #define SYSCTL_DCGC0_HIB 0x00000040 ///< HIB Clock Gating Control 01175 #define SYSCTL_DCGC0_WDT0 0x00000008 ///< WDT0 Clock Gating Control 01176 /*\}*/ 01177 01181 /*\{*/ 01182 #define SYSCTL_DCGC1_EPI0 0x40000000 ///< EPI0 Clock Gating 01183 #define SYSCTL_DCGC1_I2S0 0x10000000 ///< I2S0 Clock Gating 01184 #define SYSCTL_DCGC1_COMP2 0x04000000 ///< Analog Comparator 2 Clock Gating 01185 #define SYSCTL_DCGC1_COMP1 0x02000000 ///< Analog Comparator 1 Clock Gating 01186 #define SYSCTL_DCGC1_COMP0 0x01000000 ///< Analog Comparator 0 Clock Gating 01187 #define SYSCTL_DCGC1_TIMER3 0x00080000 ///< Timer 3 Clock Gating Control 01188 #define SYSCTL_DCGC1_TIMER2 0x00040000 ///< Timer 2 Clock Gating Control 01189 #define SYSCTL_DCGC1_TIMER1 0x00020000 ///< Timer 1 Clock Gating Control 01190 #define SYSCTL_DCGC1_TIMER0 0x00010000 ///< Timer 0 Clock Gating Control 01191 #define SYSCTL_DCGC1_I2C1 0x00004000 ///< I2C1 Clock Gating Control 01192 #define SYSCTL_DCGC1_I2C0 0x00001000 ///< I2C0 Clock Gating Control 01193 #define SYSCTL_DCGC1_QEI1 0x00000200 ///< QEI1 Clock Gating Control 01194 #define SYSCTL_DCGC1_QEI0 0x00000100 ///< QEI0 Clock Gating Control 01195 #define SYSCTL_DCGC1_SSI1 0x00000020 ///< SSI1 Clock Gating Control 01196 #define SYSCTL_DCGC1_SSI0 0x00000010 ///< SSI0 Clock Gating Control 01197 #define SYSCTL_DCGC1_UART2 0x00000004 ///< UART2 Clock Gating Control 01198 #define SYSCTL_DCGC1_UART1 0x00000002 ///< UART1 Clock Gating Control 01199 #define SYSCTL_DCGC1_UART0 0x00000001 ///< UART0 Clock Gating Control 01200 /*\}*/ 01201 01205 /*\{*/ 01206 #define SYSCTL_DCGC2_EPHY0 0x40000000 ///< PHY0 Clock Gating Control 01207 #define SYSCTL_DCGC2_EMAC0 0x10000000 ///< MAC0 Clock Gating Control 01208 #define SYSCTL_DCGC2_USB0 0x00010000 ///< USB0 Clock Gating Control 01209 #define SYSCTL_DCGC2_UDMA 0x00002000 ///< Micro-DMA Clock Gating Control 01210 #define SYSCTL_DCGC2_GPIOJ 0x00000100 ///< Port J Clock Gating Control 01211 #define SYSCTL_DCGC2_GPIOH 0x00000080 ///< Port H Clock Gating Control 01212 #define SYSCTL_DCGC2_GPIOG 0x00000040 ///< Port G Clock Gating Control 01213 #define SYSCTL_DCGC2_GPIOF 0x00000020 ///< Port F Clock Gating Control 01214 #define SYSCTL_DCGC2_GPIOE 0x00000010 ///< Port E Clock Gating Control 01215 #define SYSCTL_DCGC2_GPIOD 0x00000008 ///< Port D Clock Gating Control 01216 #define SYSCTL_DCGC2_GPIOC 0x00000004 ///< Port C Clock Gating Control 01217 #define SYSCTL_DCGC2_GPIOB 0x00000002 ///< Port B Clock Gating Control 01218 #define SYSCTL_DCGC2_GPIOA 0x00000001 ///< Port A Clock Gating Control 01219 /*\}*/ 01220 01225 /*\{*/ 01226 #define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 ///< Divider Field Override 01227 #define SYSCTL_DSLPCLKCFG_D_1 0x00000000 ///< System clock /1 01228 #define SYSCTL_DSLPCLKCFG_D_2 0x00800000 ///< System clock /2 01229 #define SYSCTL_DSLPCLKCFG_D_3 0x01000000 ///< System clock /3 01230 #define SYSCTL_DSLPCLKCFG_D_4 0x01800000 ///< System clock /4 01231 #define SYSCTL_DSLPCLKCFG_D_5 0x02000000 ///< System clock /5 01232 #define SYSCTL_DSLPCLKCFG_D_6 0x02800000 ///< System clock /6 01233 #define SYSCTL_DSLPCLKCFG_D_7 0x03000000 ///< System clock /7 01234 #define SYSCTL_DSLPCLKCFG_D_8 0x03800000 ///< System clock /8 01235 #define SYSCTL_DSLPCLKCFG_D_9 0x04000000 ///< System clock /9 01236 #define SYSCTL_DSLPCLKCFG_D_10 0x04800000 ///< System clock /10 01237 #define SYSCTL_DSLPCLKCFG_D_11 0x05000000 ///< System clock /11 01238 #define SYSCTL_DSLPCLKCFG_D_12 0x05800000 ///< System clock /12 01239 #define SYSCTL_DSLPCLKCFG_D_13 0x06000000 ///< System clock /13 01240 #define SYSCTL_DSLPCLKCFG_D_14 0x06800000 ///< System clock /14 01241 #define SYSCTL_DSLPCLKCFG_D_15 0x07000000 ///< System clock /15 01242 #define SYSCTL_DSLPCLKCFG_D_16 0x07800000 ///< System clock /16 01243 #define SYSCTL_DSLPCLKCFG_D_17 0x08000000 ///< System clock /17 01244 #define SYSCTL_DSLPCLKCFG_D_18 0x08800000 ///< System clock /18 01245 #define SYSCTL_DSLPCLKCFG_D_19 0x09000000 ///< System clock /19 01246 #define SYSCTL_DSLPCLKCFG_D_20 0x09800000 ///< System clock /20 01247 #define SYSCTL_DSLPCLKCFG_D_21 0x0A000000 ///< System clock /21 01248 #define SYSCTL_DSLPCLKCFG_D_22 0x0A800000 ///< System clock /22 01249 #define SYSCTL_DSLPCLKCFG_D_23 0x0B000000 ///< System clock /23 01250 #define SYSCTL_DSLPCLKCFG_D_24 0x0B800000 ///< System clock /24 01251 #define SYSCTL_DSLPCLKCFG_D_25 0x0C000000 ///< System clock /25 01252 #define SYSCTL_DSLPCLKCFG_D_26 0x0C800000 ///< System clock /26 01253 #define SYSCTL_DSLPCLKCFG_D_27 0x0D000000 ///< System clock /27 01254 #define SYSCTL_DSLPCLKCFG_D_28 0x0D800000 ///< System clock /28 01255 #define SYSCTL_DSLPCLKCFG_D_29 0x0E000000 ///< System clock /29 01256 #define SYSCTL_DSLPCLKCFG_D_30 0x0E800000 ///< System clock /30 01257 #define SYSCTL_DSLPCLKCFG_D_31 0x0F000000 ///< System clock /31 01258 #define SYSCTL_DSLPCLKCFG_D_32 0x0F800000 ///< System clock /32 01259 #define SYSCTL_DSLPCLKCFG_D_33 0x10000000 ///< System clock /33 01260 #define SYSCTL_DSLPCLKCFG_D_34 0x10800000 ///< System clock /34 01261 #define SYSCTL_DSLPCLKCFG_D_35 0x11000000 ///< System clock /35 01262 #define SYSCTL_DSLPCLKCFG_D_36 0x11800000 ///< System clock /36 01263 #define SYSCTL_DSLPCLKCFG_D_37 0x12000000 ///< System clock /37 01264 #define SYSCTL_DSLPCLKCFG_D_38 0x12800000 ///< System clock /38 01265 #define SYSCTL_DSLPCLKCFG_D_39 0x13000000 ///< System clock /39 01266 #define SYSCTL_DSLPCLKCFG_D_40 0x13800000 ///< System clock /40 01267 #define SYSCTL_DSLPCLKCFG_D_41 0x14000000 ///< System clock /41 01268 #define SYSCTL_DSLPCLKCFG_D_42 0x14800000 ///< System clock /42 01269 #define SYSCTL_DSLPCLKCFG_D_43 0x15000000 ///< System clock /43 01270 #define SYSCTL_DSLPCLKCFG_D_44 0x15800000 ///< System clock /44 01271 #define SYSCTL_DSLPCLKCFG_D_45 0x16000000 ///< System clock /45 01272 #define SYSCTL_DSLPCLKCFG_D_46 0x16800000 ///< System clock /46 01273 #define SYSCTL_DSLPCLKCFG_D_47 0x17000000 ///< System clock /47 01274 #define SYSCTL_DSLPCLKCFG_D_48 0x17800000 ///< System clock /48 01275 #define SYSCTL_DSLPCLKCFG_D_49 0x18000000 ///< System clock /49 01276 #define SYSCTL_DSLPCLKCFG_D_50 0x18800000 ///< System clock /50 01277 #define SYSCTL_DSLPCLKCFG_D_51 0x19000000 ///< System clock /51 01278 #define SYSCTL_DSLPCLKCFG_D_52 0x19800000 ///< System clock /52 01279 #define SYSCTL_DSLPCLKCFG_D_53 0x1A000000 ///< System clock /53 01280 #define SYSCTL_DSLPCLKCFG_D_54 0x1A800000 ///< System clock /54 01281 #define SYSCTL_DSLPCLKCFG_D_55 0x1B000000 ///< System clock /55 01282 #define SYSCTL_DSLPCLKCFG_D_56 0x1B800000 ///< System clock /56 01283 #define SYSCTL_DSLPCLKCFG_D_57 0x1C000000 ///< System clock /57 01284 #define SYSCTL_DSLPCLKCFG_D_58 0x1C800000 ///< System clock /58 01285 #define SYSCTL_DSLPCLKCFG_D_59 0x1D000000 ///< System clock /59 01286 #define SYSCTL_DSLPCLKCFG_D_60 0x1D800000 ///< System clock /60 01287 #define SYSCTL_DSLPCLKCFG_D_61 0x1E000000 ///< System clock /61 01288 #define SYSCTL_DSLPCLKCFG_D_62 0x1E800000 ///< System clock /62 01289 #define SYSCTL_DSLPCLKCFG_D_63 0x1F000000 ///< System clock /63 01290 #define SYSCTL_DSLPCLKCFG_D_64 0x1F800000 ///< System clock /64 01291 #define SYSCTL_DSLPCLKCFG_O_M 0x00000070 ///< Clock Source 01292 #define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 ///< MOSC 01293 #define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 ///< PIOSC 01294 #define SYSCTL_DSLPCLKCFG_O_30 0x00000030 ///< 30 kHz 01295 #define SYSCTL_DSLPCLKCFG_O_32 0x00000070 ///< 32.768 kHz 01296 #define SYSCTL_DSLPCLKCFG_IOSC 0x00000001 ///< IOSC Clock Source 01297 #define SYSCTL_DSLPCLKCFG_D_S 23 01298 /*\}*/ 01299 01303 /*\{*/ 01304 #define SYSCTL_CLKVCLR_VERCLR 0x00000001 ///< Clock Verification Clear 01305 /*\}*/ 01306 01311 /*\{*/ 01312 #define SYSCTL_PIOSCCAL_UTEN 0x80000000 ///< Use User Trim Value 01313 #define SYSCTL_PIOSCCAL_CAL 0x00000200 ///< Start Calibration 01314 #define SYSCTL_PIOSCCAL_UPDATE 0x00000100 ///< Update Trim 01315 #define SYSCTL_PIOSCCAL_UT_M 0x0000007F ///< User Trim Value 01316 #define SYSCTL_PIOSCCAL_UT_S 0 01317 /*\}*/ 01318 01323 /*\{*/ 01324 #define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 ///< Default Trim Value 01325 #define SYSCTL_PIOSCSTAT_CR_M 0x00000300 ///< Calibration Result 01326 #define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 ///< Calibration has not been 01327 01328 #define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 ///< The last calibration operation 01329 01330 #define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 ///< The last calibration operation 01331 01332 #define SYSCTL_PIOSCSTAT_CT_M 0x0000007F ///< Calibration Trim Value 01333 #define SYSCTL_PIOSCSTAT_DT_S 16 01334 #define SYSCTL_PIOSCSTAT_CT_S 0 01335 /*\}*/ 01336 01340 /*\{*/ 01341 #define SYSCTL_LDOARST_LDOARST 0x00000001 ///< LDO Reset 01342 /*\}*/ 01343 01348 /*\{*/ 01349 #define SYSCTL_I2SMCLKCFG_RXEN 0x80000000 ///< RX Clock Enable 01350 #define SYSCTL_I2SMCLKCFG_RXI_M 0x3FF00000 ///< RX Clock Integer Input 01351 #define SYSCTL_I2SMCLKCFG_RXF_M 0x000F0000 ///< RX Clock Fractional Input 01352 #define SYSCTL_I2SMCLKCFG_TXEN 0x00008000 ///< TX Clock Enable 01353 #define SYSCTL_I2SMCLKCFG_TXI_M 0x00003FF0 ///< TX Clock Integer Input 01354 #define SYSCTL_I2SMCLKCFG_TXF_M 0x0000000F ///< TX Clock Fractional Input 01355 #define SYSCTL_I2SMCLKCFG_RXI_S 20 01356 #define SYSCTL_I2SMCLKCFG_RXF_S 16 01357 #define SYSCTL_I2SMCLKCFG_TXI_S 4 01358 #define SYSCTL_I2SMCLKCFG_TXF_S 0 01359 /*\}*/ 01360 01364 /*\{*/ 01365 #define SYSCTL_DC9_ADC1DC7 0x00800000 ///< ADC1 DC7 Present 01366 #define SYSCTL_DC9_ADC1DC6 0x00400000 ///< ADC1 DC6 Present 01367 #define SYSCTL_DC9_ADC1DC5 0x00200000 ///< ADC1 DC5 Present 01368 #define SYSCTL_DC9_ADC1DC4 0x00100000 ///< ADC1 DC4 Present 01369 #define SYSCTL_DC9_ADC1DC3 0x00080000 ///< ADC1 DC3 Present 01370 #define SYSCTL_DC9_ADC1DC2 0x00040000 ///< ADC1 DC2 Present 01371 #define SYSCTL_DC9_ADC1DC1 0x00020000 ///< ADC1 DC1 Present 01372 #define SYSCTL_DC9_ADC1DC0 0x00010000 ///< ADC1 DC0 Present 01373 #define SYSCTL_DC9_ADC0DC7 0x00000080 ///< ADC0 DC7 Present 01374 #define SYSCTL_DC9_ADC0DC6 0x00000040 ///< ADC0 DC6 Present 01375 #define SYSCTL_DC9_ADC0DC5 0x00000020 ///< ADC0 DC5 Present 01376 #define SYSCTL_DC9_ADC0DC4 0x00000010 ///< ADC0 DC4 Present 01377 #define SYSCTL_DC9_ADC0DC3 0x00000008 ///< ADC0 DC3 Present 01378 #define SYSCTL_DC9_ADC0DC2 0x00000004 ///< ADC0 DC2 Present 01379 #define SYSCTL_DC9_ADC0DC1 0x00000002 ///< ADC0 DC1 Present 01380 #define SYSCTL_DC9_ADC0DC0 0x00000001 ///< ADC0 DC0 Present 01381 /*\}*/ 01382 01386 /*\{*/ 01387 #define SYSCTL_NVMSTAT_TPSW 0x00000010 ///< Third Party Software Present 01388 #define SYSCTL_NVMSTAT_FWB 0x00000001 ///< 32 Word Flash Write Buffer 01389 01390 /*\}*/ 01391 01396 /*\{*/ 01397 #define SYSCTL_USER0 0x400FE1E0 ///< NV User Register 0 01398 #define SYSCTL_USER1 0x400FE1E4 ///< NV User Register 1 01399 /*\}*/ 01400 01405 /*\{*/ 01406 #define SYSCTL_DID0_VER_MASK 0x70000000 ///< DID0 version mask 01407 #define SYSCTL_DID0_CLASS_MASK 0x00FF0000 ///< Device Class 01408 #define SYSCTL_DID0_MAJ_MASK 0x0000FF00 ///< Major revision mask 01409 #define SYSCTL_DID0_MAJ_A 0x00000000 ///< Major revision A 01410 #define SYSCTL_DID0_MAJ_B 0x00000100 ///< Major revision B 01411 #define SYSCTL_DID0_MAJ_C 0x00000200 ///< Major revision C 01412 #define SYSCTL_DID0_MIN_MASK 0x000000FF ///< Minor revision mask 01413 /*\}*/ 01414 01419 /*\{*/ 01420 #define SYSCTL_DID1_VER_MASK 0xF0000000 ///< Register version mask 01421 #define SYSCTL_DID1_FAM_MASK 0x0F000000 ///< Family mask 01422 #define SYSCTL_DID1_FAM_S 0x00000000 ///< Stellaris family 01423 #define SYSCTL_DID1_PRTNO_MASK 0x00FF0000 ///< Part number mask 01424 #define SYSCTL_DID1_PINCNT_MASK 0x0000E000 ///< Pin count 01425 #define SYSCTL_DID1_TEMP_MASK 0x000000E0 ///< Temperature range mask 01426 #define SYSCTL_DID1_PKG_MASK 0x00000018 ///< Package mask 01427 #define SYSCTL_DID1_PKG_48QFP 0x00000008 ///< QFP package 01428 #define SYSCTL_DID1_QUAL_MASK 0x00000003 ///< Qualification status mask 01429 #define SYSCTL_DID1_PKG_28SOIC 0x00000000 ///< SOIC package 01430 #define SYSCTL_DID1_PRTNO_SHIFT 16 01431 /*\}*/ 01432 01437 /*\{*/ 01438 #define SYSCTL_DC0_SRAMSZ_MASK 0xFFFF0000 ///< SRAM size mask 01439 #define SYSCTL_DC0_FLASHSZ_MASK 0x0000FFFF ///< Flash size mask 01440 /*\}*/ 01441 01446 /*\{*/ 01447 #define SYSCTL_DC1_ADC 0x00010000 ///< ADC Module Present 01448 #define SYSCTL_DC1_SYSDIV_MASK 0x0000F000 ///< Minimum system divider mask 01449 #define SYSCTL_DC1_ADCSPD_MASK 0x00000F00 ///< ADC speed mask 01450 #define SYSCTL_DC1_WDOG 0x00000008 ///< Watchdog present 01451 #define SYSCTL_DC1_WDT 0x00000008 ///< Watchdog Timer Present 01452 /*\}*/ 01453 01458 /*\{*/ 01459 #define SYSCTL_DC2_I2C 0x00001000 ///< I2C present 01460 #define SYSCTL_DC2_QEI 0x00000100 ///< QEI present 01461 #define SYSCTL_DC2_SSI 0x00000010 ///< SSI present 01462 /*\}*/ 01463 01468 /*\{*/ 01469 #define SYSCTL_DC3_ADC7 0x00800000 ///< ADC7 Pin Present 01470 #define SYSCTL_DC3_ADC6 0x00400000 ///< ADC6 Pin Present 01471 #define SYSCTL_DC3_ADC5 0x00200000 ///< ADC5 Pin Present 01472 #define SYSCTL_DC3_ADC4 0x00100000 ///< ADC4 Pin Present 01473 #define SYSCTL_DC3_ADC3 0x00080000 ///< ADC3 Pin Present 01474 #define SYSCTL_DC3_ADC2 0x00040000 ///< ADC2 Pin Present 01475 #define SYSCTL_DC3_ADC1 0x00020000 ///< ADC1 Pin Present 01476 #define SYSCTL_DC3_ADC0 0x00010000 ///< ADC0 Pin Present 01477 #define SYSCTL_DC3_MC_FAULT0 0x00008000 ///< MC0 fault pin present 01478 /*\}*/ 01479 01484 /*\{*/ 01485 #define SYSCTL_PBORCTL_BOR_MASK 0x0000FFFC ///< BOR wait timer 01486 #define SYSCTL_PBORCTL_BOR_SH 2 01487 /*\}*/ 01488 01493 /*\{*/ 01494 #define SYSCTL_LDOPCTL_MASK 0x0000003F ///< Voltage adjust mask 01495 /*\}*/ 01496 01501 /*\{*/ 01502 #define SYSCTL_SRCR0_ADC 0x00010000 ///< ADC0 Reset Control 01503 #define SYSCTL_SRCR0_WDT 0x00000008 ///< WDT Reset Control 01504 /*\}*/ 01505 01510 /*\{*/ 01511 #define SYSCTL_RESC_WDOG 0x00000008 ///< Watchdog reset 01512 #define SYSCTL_RESC_WDT 0x00000008 ///< Watchdog Timer Reset 01513 /*\}*/ 01514 01519 /*\{*/ 01520 #define SYSCTL_RCC_SYSDIV_MASK 0x07800000 ///< System clock divider 01521 #define SYSCTL_RCC_USE_SYSDIV 0x00400000 ///< Use sytem clock divider 01522 #define SYSCTL_RCC_USE_PWMDIV 0x00100000 ///< Use PWM clock divider 01523 #define SYSCTL_RCC_PWMDIV_MASK 0x000E0000 ///< PWM clock divider 01524 #define SYSCTL_RCC_OE 0x00001000 ///< PLL output enable 01525 #define SYSCTL_RCC_XTAL_3_68MHz 0x00000140 ///< Using a 3.6864 MHz crystal 01526 #define SYSCTL_RCC_XTAL_4MHz 0x00000180 ///< Using a 4 MHz crystal 01527 #define SYSCTL_RCC_XTAL_MASK 0x000003C0 ///< Crystal attached to main osc 01528 #define SYSCTL_RCC_OSCSRC_MASK 0x00000030 ///< Oscillator input select 01529 #define SYSCTL_RCC_SYSDIV_SHIFT 23 ///< Shift to the SYSDIV field 01530 #define SYSCTL_RCC_PWMDIV_SHIFT 17 ///< Shift to the PWMDIV field 01531 #define SYSCTL_RCC_XTAL_SHIFT 6 ///< Shift to the XTAL field 01532 #define SYSCTL_RCC_OSCSRC_SHIFT 4 ///< Shift to the OSCSRC field 01533 /*\}*/ 01534 01539 /*\{*/ 01540 #define SYSCTL_PLLCFG_OD_MASK 0x0000C000 ///< Output divider 01541 #define SYSCTL_PLLCFG_F_MASK 0x00003FE0 ///< PLL multiplier 01542 #define SYSCTL_PLLCFG_R_MASK 0x0000001F ///< Input predivider 01543 #define SYSCTL_PLLCFG_F_SHIFT 5 01544 #define SYSCTL_PLLCFG_R_SHIFT 0 01545 /*\}*/ 01546 01551 /*\{*/ 01552 #define SYSCTL_RCC2_USEFRACT 0x40000000 ///< Use fractional divider 01553 #define SYSCTL_RCC2_SYSDIV2_MSK 0x1F800000 ///< System clock divider 01554 #define SYSCTL_RCC2_FRACT 0x00400000 ///< Fractional divide 01555 #define SYSCTL_RCC2_OSCSRC2_MSK 0x00000070 ///< Oscillator input select 01556 /*\}*/ 01557 01562 /*\{*/ 01563 #define SYSCTL_RCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control 01564 #define SYSCTL_RCGC0_WDT 0x00000008 ///< WDT Clock Gating Control 01565 /*\}*/ 01566 01571 /*\{*/ 01572 #define SYSCTL_SCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control 01573 #define SYSCTL_SCGC0_WDT 0x00000008 ///< WDT Clock Gating Control 01574 /*\}*/ 01575 01580 /*\{*/ 01581 #define SYSCTL_DCGC0_ADC 0x00010000 ///< ADC0 Clock Gating Control 01582 #define SYSCTL_DCGC0_WDT 0x00000008 ///< WDT Clock Gating Control 01583 /*\}*/ 01584 01589 /*\{*/ 01590 #define SYSCTL_DSLPCLKCFG_D_MSK 0x1F800000 ///< Deep sleep system clock override 01591 #define SYSCTL_DSLPCLKCFG_O_MSK 0x00000070 ///< Deep sleep oscillator override 01592 /*\}*/ 01593 01598 /*\{*/ 01599 #define SYSCTL_CLKVCLR_CLR 0x00000001 ///< Clear clock verification fault 01600 /*\}*/ 01601 01606 /*\{*/ 01607 #define SYSCTL_LDOARST_ARST 0x00000001 ///< Allow LDO to reset device 01608 /*\}*/ 01609 01614 /*\{*/ 01615 #define SYSCTL_SET0_CAN2 0x04000000 ///< CAN 2 module 01616 #define SYSCTL_SET0_CAN1 0x02000000 ///< CAN 1 module 01617 #define SYSCTL_SET0_CAN0 0x01000000 ///< CAN 0 module 01618 #define SYSCTL_SET0_PWM 0x00100000 ///< PWM module 01619 #define SYSCTL_SET0_ADC 0x00010000 ///< ADC module 01620 #define SYSCTL_SET0_ADCSPD_MASK 0x00000F00 ///< ADC speed mask 01621 #define SYSCTL_SET0_ADCSPD_125K 0x00000000 ///< 125Ksps ADC 01622 #define SYSCTL_SET0_ADCSPD_250K 0x00000100 ///< 250Ksps ADC 01623 #define SYSCTL_SET0_ADCSPD_500K 0x00000200 ///< 500Ksps ADC 01624 #define SYSCTL_SET0_ADCSPD_1M 0x00000300 ///< 1Msps ADC 01625 #define SYSCTL_SET0_HIB 0x00000040 ///< Hibernation module 01626 #define SYSCTL_SET0_WDOG 0x00000008 ///< Watchdog module 01627 /*\}*/ 01628 01633 /*\{*/ 01634 #define SYSCTL_SET1_COMP2 0x04000000 ///< Analog comparator module 2 01635 #define SYSCTL_SET1_COMP1 0x02000000 ///< Analog comparator module 1 01636 #define SYSCTL_SET1_COMP0 0x01000000 ///< Analog comparator module 0 01637 #define SYSCTL_SET1_TIMER3 0x00080000 ///< Timer module 3 01638 #define SYSCTL_SET1_TIMER2 0x00040000 ///< Timer module 2 01639 #define SYSCTL_SET1_TIMER1 0x00020000 ///< Timer module 1 01640 #define SYSCTL_SET1_TIMER0 0x00010000 ///< Timer module 0 01641 #define SYSCTL_SET1_I2C1 0x00002000 ///< I2C module 1 01642 #define SYSCTL_SET1_I2C0 0x00001000 ///< I2C module 0 01643 #define SYSCTL_SET1_I2C 0x00001000 ///< I2C module 01644 #define SYSCTL_SET1_QEI1 0x00000200 ///< QEI module 1 01645 #define SYSCTL_SET1_QEI 0x00000100 ///< QEI module 01646 #define SYSCTL_SET1_QEI0 0x00000100 ///< QEI module 0 01647 #define SYSCTL_SET1_SSI1 0x00000020 ///< SSI module 1 01648 #define SYSCTL_SET1_SSI0 0x00000010 ///< SSI module 0 01649 #define SYSCTL_SET1_SSI 0x00000010 ///< SSI module 01650 #define SYSCTL_SET1_UART2 0x00000004 ///< UART module 2 01651 #define SYSCTL_SET1_UART1 0x00000002 ///< UART module 1 01652 #define SYSCTL_SET1_UART0 0x00000001 ///< UART module 0 01653 /*\}*/ 01654 01659 /*\{*/ 01660 #define SYSCTL_SET2_ETH 0x50000000 ///< ETH module 01661 #define SYSCTL_SET2_GPIOH 0x00000080 ///< GPIO H module 01662 #define SYSCTL_SET2_GPIOG 0x00000040 ///< GPIO G module 01663 #define SYSCTL_SET2_GPIOF 0x00000020 ///< GPIO F module 01664 #define SYSCTL_SET2_GPIOE 0x00000010 ///< GPIO E module 01665 #define SYSCTL_SET2_GPIOD 0x00000008 ///< GPIO D module 01666 #define SYSCTL_SET2_GPIOC 0x00000004 ///< GPIO C module 01667 #define SYSCTL_SET2_GPIOB 0x00000002 ///< GPIO B module 01668 #define SYSCTL_SET2_GPIOA 0x00000001 ///< GIPO A module 01669 /*\}*/ 01670 01675 /*\{*/ 01676 #define SYSCTL_INT_PLL_LOCK 0x00000040 ///< PLL lock interrupt 01677 #define SYSCTL_INT_CUR_LIMIT 0x00000020 ///< Current limit interrupt 01678 #define SYSCTL_INT_IOSC_FAIL 0x00000010 ///< Internal oscillator failure int 01679 #define SYSCTL_INT_MOSC_FAIL 0x00000008 ///< Main oscillator failure int 01680 #define SYSCTL_INT_POR 0x00000004 ///< Power on reset interrupt 01681 #define SYSCTL_INT_BOR 0x00000002 ///< Brown out interrupt 01682 #define SYSCTL_INT_PLL_FAIL 0x00000001 ///< PLL failure interrupt 01683 /*\}*/ 01684 01685 #endif /* LM3S_SYSCTL_H */