BeRTOS
lm3s_adc.h
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00001 
00036 #ifndef LM3S_ADC_H
00037 #define LM3S_ADC_H
00038 
00039 
00040 /*
00041  * The following are defines for the ADC register offsets.
00042  */
00043 #define ADC_O_ACTSS             0x00000000  ///< ADC Active Sample Sequencer
00044 #define ADC_O_RIS               0x00000004  ///< ADC Raw Interrupt Status
00045 #define ADC_O_IM                0x00000008  ///< ADC Interrupt Mask
00046 #define ADC_O_ISC               0x0000000C  ///< ADC Interrupt Status and Clear
00047 #define ADC_O_OSTAT             0x00000010  ///< ADC Overflow Status
00048 #define ADC_O_EMUX              0x00000014  ///< ADC Event Multiplexer Select
00049 #define ADC_O_USTAT             0x00000018  ///< ADC Underflow Status
00050 #define ADC_O_SSPRI             0x00000020  ///< ADC Sample Sequencer Priority
00051 #define ADC_O_SPC               0x00000024  ///< ADC Sample Phase Control
00052 #define ADC_O_PSSI              0x00000028  ///< ADC Processor Sample Sequence
00053 
00054 #define ADC_O_SAC               0x00000030  ///< ADC Sample Averaging Control
00055 #define ADC_O_DCISC             0x00000034  ///< ADC Digital Comparator Interrupt
00056 
00057 #define ADC_O_CTL               0x00000038  ///< ADC Control
00058 #define ADC_O_SSMUX0            0x00000040  ///< ADC Sample Sequence Input
00059 
00060 #define ADC_O_SSCTL0            0x00000044  ///< ADC Sample Sequence Control 0
00061 #define ADC_O_SSFIFO0           0x00000048  ///< ADC Sample Sequence Result FIFO
00062 
00063 #define ADC_O_SSFSTAT0          0x0000004C  ///< ADC Sample Sequence FIFO 0
00064 
00065 #define ADC_O_SSOP0             0x00000050  ///< ADC Sample Sequence 0 Operation
00066 #define ADC_O_SSDC0             0x00000054  ///< ADC Sample Sequence 0 Digital
00067 
00068 #define ADC_O_SSMUX1            0x00000060  ///< ADC Sample Sequence Input
00069 
00070 #define ADC_O_SSCTL1            0x00000064  ///< ADC Sample Sequence Control 1
00071 #define ADC_O_SSFIFO1           0x00000068  ///< ADC Sample Sequence Result FIFO
00072 
00073 #define ADC_O_SSFSTAT1          0x0000006C  ///< ADC Sample Sequence FIFO 1
00074 
00075 #define ADC_O_SSOP1             0x00000070  ///< ADC Sample Sequence 1 Operation
00076 #define ADC_O_SSDC1             0x00000074  ///< ADC Sample Sequence 1 Digital
00077 
00078 #define ADC_O_SSMUX2            0x00000080  ///< ADC Sample Sequence Input
00079 
00080 #define ADC_O_SSCTL2            0x00000084  ///< ADC Sample Sequence Control 2
00081 #define ADC_O_SSFIFO2           0x00000088  ///< ADC Sample Sequence Result FIFO
00082 
00083 #define ADC_O_SSFSTAT2          0x0000008C  ///< ADC Sample Sequence FIFO 2
00084 
00085 #define ADC_O_SSOP2             0x00000090  ///< ADC Sample Sequence 2 Operation
00086 #define ADC_O_SSDC2             0x00000094  ///< ADC Sample Sequence 2 Digital
00087 
00088 #define ADC_O_SSMUX3            0x000000A0  ///< ADC Sample Sequence Input
00089 
00090 #define ADC_O_SSCTL3            0x000000A4  ///< ADC Sample Sequence Control 3
00091 #define ADC_O_SSFIFO3           0x000000A8  ///< ADC Sample Sequence Result FIFO
00092 
00093 #define ADC_O_SSFSTAT3          0x000000AC  ///< ADC Sample Sequence FIFO 3
00094 
00095 #define ADC_O_SSOP3             0x000000B0  ///< ADC Sample Sequence 3 Operation
00096 #define ADC_O_SSDC3             0x000000B4  ///< ADC Sample Sequence 3 Digital
00097 
00098 #define ADC_O_TMLB              0x00000100  ///< ADC Test Mode Loopback
00099 #define ADC_O_DCRIC             0x00000D00  ///< ADC Digital Comparator Reset
00100 
00101 #define ADC_O_DCCTL0            0x00000E00  ///< ADC Digital Comparator Control 0
00102 #define ADC_O_DCCTL1            0x00000E04  ///< ADC Digital Comparator Control 1
00103 #define ADC_O_DCCTL2            0x00000E08  ///< ADC Digital Comparator Control 2
00104 #define ADC_O_DCCTL3            0x00000E0C  ///< ADC Digital Comparator Control 3
00105 #define ADC_O_DCCTL4            0x00000E10  ///< ADC Digital Comparator Control 4
00106 #define ADC_O_DCCTL5            0x00000E14  ///< ADC Digital Comparator Control 5
00107 #define ADC_O_DCCTL6            0x00000E18  ///< ADC Digital Comparator Control 6
00108 #define ADC_O_DCCTL7            0x00000E1C  ///< ADC Digital Comparator Control 7
00109 #define ADC_O_DCCMP0            0x00000E40  ///< ADC Digital Comparator Range 0
00110 #define ADC_O_DCCMP1            0x00000E44  ///< ADC Digital Comparator Range 1
00111 #define ADC_O_DCCMP2            0x00000E48  ///< ADC Digital Comparator Range 2
00112 #define ADC_O_DCCMP3            0x00000E4C  ///< ADC Digital Comparator Range 3
00113 #define ADC_O_DCCMP4            0x00000E50  ///< ADC Digital Comparator Range 4
00114 #define ADC_O_DCCMP5            0x00000E54  ///< ADC Digital Comparator Range 5
00115 #define ADC_O_DCCMP6            0x00000E58  ///< ADC Digital Comparator Range 6
00116 #define ADC_O_DCCMP7            0x00000E5C  ///< ADC Digital Comparator Range 7
00117 
00118 
00119 /*
00120  * The following are defines for the bit fields in the ADC_O_ACTSS register.
00121  */
00122 #define ADC_ACTSS_ASEN3         0x00000008  ///< ADC SS3 Enable
00123 #define ADC_ACTSS_ASEN2         0x00000004  ///< ADC SS2 Enable
00124 #define ADC_ACTSS_ASEN1         0x00000002  ///< ADC SS1 Enable
00125 #define ADC_ACTSS_ASEN0         0x00000001  ///< ADC SS0 Enable
00126 
00127 
00128 /*
00129  * The following are defines for the bit fields in the ADC_O_RIS register.
00130  */
00131 #define ADC_RIS_INRDC           0x00010000  ///< Digital Comparator Raw Interrupt
00132 
00133 #define ADC_RIS_INR3            0x00000008  ///< SS3 Raw Interrupt Status
00134 #define ADC_RIS_INR2            0x00000004  ///< SS2 Raw Interrupt Status
00135 #define ADC_RIS_INR1            0x00000002  ///< SS1 Raw Interrupt Status
00136 #define ADC_RIS_INR0            0x00000001  ///< SS0 Raw Interrupt Status
00137 
00138 
00139 /*
00140  * The following are defines for the bit fields in the ADC_O_IM register.
00141  */
00142 #define ADC_IM_DCONSS3          0x00080000  ///< Digital Comparator Interrupt on
00143 
00144 #define ADC_IM_DCONSS2          0x00040000  ///< Digital Comparator Interrupt on
00145 
00146 #define ADC_IM_DCONSS1          0x00020000  ///< Digital Comparator Interrupt on
00147 
00148 #define ADC_IM_DCONSS0          0x00010000  ///< Digital Comparator Interrupt on
00149 
00150 #define ADC_IM_MASK3            0x00000008  ///< SS3 Interrupt Mask
00151 #define ADC_IM_MASK2            0x00000004  ///< SS2 Interrupt Mask
00152 #define ADC_IM_MASK1            0x00000002  ///< SS1 Interrupt Mask
00153 #define ADC_IM_MASK0            0x00000001  ///< SS0 Interrupt Mask
00154 
00155 
00156 /*
00157  * The following are defines for the bit fields in the ADC_O_ISC register.
00158  */
00159 #define ADC_ISC_DCINSS3         0x00080000  ///< Digital Comparator Interrupt
00160 
00161 #define ADC_ISC_DCINSS2         0x00040000  ///< Digital Comparator Interrupt
00162 
00163 #define ADC_ISC_DCINSS1         0x00020000  ///< Digital Comparator Interrupt
00164 
00165 #define ADC_ISC_DCINSS0         0x00010000  ///< Digital Comparator Interrupt
00166 
00167 #define ADC_ISC_IN3             0x00000008  ///< SS3 Interrupt Status and Clear
00168 #define ADC_ISC_IN2             0x00000004  ///< SS2 Interrupt Status and Clear
00169 #define ADC_ISC_IN1             0x00000002  ///< SS1 Interrupt Status and Clear
00170 #define ADC_ISC_IN0             0x00000001  ///< SS0 Interrupt Status and Clear
00171 
00172 
00173 /*
00174  * The following are defines for the bit fields in the ADC_O_OSTAT register.
00175  */
00176 #define ADC_OSTAT_OV3           0x00000008  ///< SS3 FIFO Overflow
00177 #define ADC_OSTAT_OV2           0x00000004  ///< SS2 FIFO Overflow
00178 #define ADC_OSTAT_OV1           0x00000002  ///< SS1 FIFO Overflow
00179 #define ADC_OSTAT_OV0           0x00000001  ///< SS0 FIFO Overflow
00180 
00181 
00182 /*
00183  * The following are defines for the bit fields in the ADC_O_EMUX register.
00184  */
00185 #define ADC_EMUX_EM3_M          0x0000F000  ///< SS3 Trigger Select
00186 #define ADC_EMUX_EM3_PROCESSOR  0x00000000  ///< Processor (default)
00187 #define ADC_EMUX_EM3_COMP0      0x00001000  ///< Analog Comparator 0
00188 #define ADC_EMUX_EM3_COMP1      0x00002000  ///< Analog Comparator 1
00189 #define ADC_EMUX_EM3_COMP2      0x00003000  ///< Analog Comparator 2
00190 #define ADC_EMUX_EM3_EXTERNAL   0x00004000  ///< External (GPIO PB4)
00191 #define ADC_EMUX_EM3_TIMER      0x00005000  ///< Timer
00192 #define ADC_EMUX_EM3_PWM0       0x00006000  ///< PWM0
00193 #define ADC_EMUX_EM3_PWM1       0x00007000  ///< PWM1
00194 #define ADC_EMUX_EM3_PWM2       0x00008000  ///< PWM2
00195 #define ADC_EMUX_EM3_PWM3       0x00009000  ///< PWM3
00196 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  ///< Always (continuously sample)
00197 #define ADC_EMUX_EM2_M          0x00000F00  ///< SS2 Trigger Select
00198 #define ADC_EMUX_EM2_PROCESSOR  0x00000000  ///< Processor (default)
00199 #define ADC_EMUX_EM2_COMP0      0x00000100  ///< Analog Comparator 0
00200 #define ADC_EMUX_EM2_COMP1      0x00000200  ///< Analog Comparator 1
00201 #define ADC_EMUX_EM2_COMP2      0x00000300  ///< Analog Comparator 2
00202 #define ADC_EMUX_EM2_EXTERNAL   0x00000400  ///< External (GPIO PB4)
00203 #define ADC_EMUX_EM2_TIMER      0x00000500  ///< Timer
00204 #define ADC_EMUX_EM2_PWM0       0x00000600  ///< PWM0
00205 #define ADC_EMUX_EM2_PWM1       0x00000700  ///< PWM1
00206 #define ADC_EMUX_EM2_PWM2       0x00000800  ///< PWM2
00207 #define ADC_EMUX_EM2_PWM3       0x00000900  ///< PWM3
00208 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  ///< Always (continuously sample)
00209 #define ADC_EMUX_EM1_M          0x000000F0  ///< SS1 Trigger Select
00210 #define ADC_EMUX_EM1_PROCESSOR  0x00000000  ///< Processor (default)
00211 #define ADC_EMUX_EM1_COMP0      0x00000010  ///< Analog Comparator 0
00212 #define ADC_EMUX_EM1_COMP1      0x00000020  ///< Analog Comparator 1
00213 #define ADC_EMUX_EM1_COMP2      0x00000030  ///< Analog Comparator 2
00214 #define ADC_EMUX_EM1_EXTERNAL   0x00000040  ///< External (GPIO PB4)
00215 #define ADC_EMUX_EM1_TIMER      0x00000050  ///< Timer
00216 #define ADC_EMUX_EM1_PWM0       0x00000060  ///< PWM0
00217 #define ADC_EMUX_EM1_PWM1       0x00000070  ///< PWM1
00218 #define ADC_EMUX_EM1_PWM2       0x00000080  ///< PWM2
00219 #define ADC_EMUX_EM1_PWM3       0x00000090  ///< PWM3
00220 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  ///< Always (continuously sample)
00221 #define ADC_EMUX_EM0_M          0x0000000F  ///< SS0 Trigger Select
00222 #define ADC_EMUX_EM0_PROCESSOR  0x00000000  ///< Processor (default)
00223 #define ADC_EMUX_EM0_COMP0      0x00000001  ///< Analog Comparator 0
00224 #define ADC_EMUX_EM0_COMP1      0x00000002  ///< Analog Comparator 1
00225 #define ADC_EMUX_EM0_COMP2      0x00000003  ///< Analog Comparator 2
00226 #define ADC_EMUX_EM0_EXTERNAL   0x00000004  ///< External (GPIO PB4)
00227 #define ADC_EMUX_EM0_TIMER      0x00000005  ///< Timer
00228 #define ADC_EMUX_EM0_PWM0       0x00000006  ///< PWM0
00229 #define ADC_EMUX_EM0_PWM1       0x00000007  ///< PWM1
00230 #define ADC_EMUX_EM0_PWM2       0x00000008  ///< PWM2
00231 #define ADC_EMUX_EM0_PWM3       0x00000009  ///< PWM3
00232 #define ADC_EMUX_EM0_ALWAYS     0x0000000F  ///< Always (continuously sample)
00233 
00234 
00235 /*
00236  * The following are defines for the bit fields in the ADC_O_USTAT register.
00237  */
00238 #define ADC_USTAT_UV3           0x00000008  ///< SS3 FIFO Underflow
00239 #define ADC_USTAT_UV2           0x00000004  ///< SS2 FIFO Underflow
00240 #define ADC_USTAT_UV1           0x00000002  ///< SS1 FIFO Underflow
00241 #define ADC_USTAT_UV0           0x00000001  ///< SS0 FIFO Underflow
00242 
00243 
00244 /*
00245  * The following are defines for the bit fields in the ADC_O_SSPRI register.
00246  */
00247 #define ADC_SSPRI_SS3_M         0x00003000  ///< SS3 Priority
00248 #define ADC_SSPRI_SS3_1ST       0x00000000  ///< First priority
00249 #define ADC_SSPRI_SS3_2ND       0x00001000  ///< Second priority
00250 #define ADC_SSPRI_SS3_3RD       0x00002000  ///< Third priority
00251 #define ADC_SSPRI_SS3_4TH       0x00003000  ///< Fourth priority
00252 #define ADC_SSPRI_SS2_M         0x00000300  ///< SS2 Priority
00253 #define ADC_SSPRI_SS2_1ST       0x00000000  ///< First priority
00254 #define ADC_SSPRI_SS2_2ND       0x00000100  ///< Second priority
00255 #define ADC_SSPRI_SS2_3RD       0x00000200  ///< Third priority
00256 #define ADC_SSPRI_SS2_4TH       0x00000300  ///< Fourth priority
00257 #define ADC_SSPRI_SS1_M         0x00000030  ///< SS1 Priority
00258 #define ADC_SSPRI_SS1_1ST       0x00000000  ///< First priority
00259 #define ADC_SSPRI_SS1_2ND       0x00000010  ///< Second priority
00260 #define ADC_SSPRI_SS1_3RD       0x00000020  ///< Third priority
00261 #define ADC_SSPRI_SS1_4TH       0x00000030  ///< Fourth priority
00262 #define ADC_SSPRI_SS0_M         0x00000003  ///< SS0 Priority
00263 #define ADC_SSPRI_SS0_1ST       0x00000000  ///< First priority
00264 #define ADC_SSPRI_SS0_2ND       0x00000001  ///< Second priority
00265 #define ADC_SSPRI_SS0_3RD       0x00000002  ///< Third priority
00266 #define ADC_SSPRI_SS0_4TH       0x00000003  ///< Fourth priority
00267 
00268 
00269 /*
00270  * The following are defines for the bit fields in the ADC_O_SPC register.
00271  */
00272 
00273 #define ADC_SPC_PHASE_M         0x0000000F  ///< Phase Difference
00274 #define ADC_SPC_PHASE_0         0x00000000  ///< ADC sample lags by 0.0
00275 #define ADC_SPC_PHASE_22_5      0x00000001  ///< ADC sample lags by 22.5
00276 #define ADC_SPC_PHASE_45        0x00000002  ///< ADC sample lags by 45.0
00277 #define ADC_SPC_PHASE_67_5      0x00000003  ///< ADC sample lags by 67.5
00278 #define ADC_SPC_PHASE_90        0x00000004  ///< ADC sample lags by 90.0
00279 #define ADC_SPC_PHASE_112_5     0x00000005  ///< ADC sample lags by 112.5
00280 #define ADC_SPC_PHASE_135       0x00000006  ///< ADC sample lags by 135.0
00281 #define ADC_SPC_PHASE_157_5     0x00000007  ///< ADC sample lags by 157.5
00282 #define ADC_SPC_PHASE_180       0x00000008  ///< ADC sample lags by 180.0
00283 #define ADC_SPC_PHASE_202_5     0x00000009  ///< ADC sample lags by 202.5
00284 #define ADC_SPC_PHASE_225       0x0000000A  ///< ADC sample lags by 225.0
00285 #define ADC_SPC_PHASE_247_5     0x0000000B  ///< ADC sample lags by 247.5
00286 #define ADC_SPC_PHASE_270       0x0000000C  ///< ADC sample lags by 270.0
00287 #define ADC_SPC_PHASE_292_5     0x0000000D  ///< ADC sample lags by 292.5
00288 #define ADC_SPC_PHASE_315       0x0000000E  ///< ADC sample lags by 315.0
00289 #define ADC_SPC_PHASE_337_5     0x0000000F  ///< ADC sample lags by 337.5
00290 
00291 
00292 /*
00293  * The following are defines for the bit fields in the ADC_O_PSSI register.
00294  */
00295 #define ADC_PSSI_GSYNC          0x80000000  ///< Global Synchronize
00296 #define ADC_PSSI_SYNCWAIT       0x08000000  ///< Synchronize Wait
00297 #define ADC_PSSI_SS3            0x00000008  ///< SS3 Initiate
00298 #define ADC_PSSI_SS2            0x00000004  ///< SS2 Initiate
00299 #define ADC_PSSI_SS1            0x00000002  ///< SS1 Initiate
00300 #define ADC_PSSI_SS0            0x00000001  ///< SS0 Initiate
00301 
00302 
00303 /*
00304  * The following are defines for the bit fields in the ADC_O_SAC register.
00305  */
00306 #define ADC_SAC_AVG_M           0x00000007  ///< Hardware Averaging Control
00307 #define ADC_SAC_AVG_OFF         0x00000000  ///< No hardware oversampling
00308 #define ADC_SAC_AVG_2X          0x00000001  ///< 2x hardware oversampling
00309 #define ADC_SAC_AVG_4X          0x00000002  ///< 4x hardware oversampling
00310 #define ADC_SAC_AVG_8X          0x00000003  ///< 8x hardware oversampling
00311 #define ADC_SAC_AVG_16X         0x00000004  ///< 16x hardware oversampling
00312 #define ADC_SAC_AVG_32X         0x00000005  ///< 32x hardware oversampling
00313 #define ADC_SAC_AVG_64X         0x00000006  ///< 64x hardware oversampling
00314 
00315 
00316 /*
00317  * The following are defines for the bit fields in the ADC_O_DCISC register.
00318  */
00319 #define ADC_DCISC_DCINT7        0x00000080  ///< Digital Comparator 7 Interrupt
00320 
00321 #define ADC_DCISC_DCINT6        0x00000040  ///< Digital Comparator 6 Interrupt
00322 
00323 #define ADC_DCISC_DCINT5        0x00000020  ///< Digital Comparator 5 Interrupt
00324 
00325 #define ADC_DCISC_DCINT4        0x00000010  ///< Digital Comparator 4 Interrupt
00326 
00327 #define ADC_DCISC_DCINT3        0x00000008  ///< Digital Comparator 3 Interrupt
00328 
00329 #define ADC_DCISC_DCINT2        0x00000004  ///< Digital Comparator 2 Interrupt
00330 
00331 #define ADC_DCISC_DCINT1        0x00000002  ///< Digital Comparator 1 Interrupt
00332 
00333 #define ADC_DCISC_DCINT0        0x00000001  ///< Digital Comparator 0 Interrupt
00334 
00335 
00336 
00337 /*
00338  * The following are defines for the bit fields in the ADC_O_CTL register.
00339  */
00340 #define ADC_CTL_VREF            0x00000001  ///< Voltage Reference Select
00341 
00342 
00343 
00347 /*\{*/
00348 #define ADC_ACTSS_ASEN3         0x00000008  ///< ADC SS3 Enable
00349 #define ADC_ACTSS_ASEN2         0x00000004  ///< ADC SS2 Enable
00350 #define ADC_ACTSS_ASEN1         0x00000002  ///< ADC SS1 Enable
00351 #define ADC_ACTSS_ASEN0         0x00000001  ///< ADC SS0 Enable
00352 /*\}*/
00353 
00357 /*\{*/
00358 #define ADC_RIS_INR3            0x00000008  ///< SS3 Raw Interrupt Status
00359 #define ADC_RIS_INR2            0x00000004  ///< SS2 Raw Interrupt Status
00360 #define ADC_RIS_INR1            0x00000002  ///< SS1 Raw Interrupt Status
00361 #define ADC_RIS_INR0            0x00000001  ///< SS0 Raw Interrupt Status
00362 /*\}*/
00363 
00367 /*\{*/
00368 #define ADC_IM_MASK3            0x00000008  ///< SS3 Interrupt Mask
00369 #define ADC_IM_MASK2            0x00000004  ///< SS2 Interrupt Mask
00370 #define ADC_IM_MASK1            0x00000002  ///< SS1 Interrupt Mask
00371 #define ADC_IM_MASK0            0x00000001  ///< SS0 Interrupt Mask
00372 /*\}*/
00373 
00377 /*\{*/
00378 #define ADC_ISC_IN3             0x00000008  ///< SS3 Interrupt Status and Clear
00379 #define ADC_ISC_IN2             0x00000004  ///< SS2 Interrupt Status and Clear
00380 #define ADC_ISC_IN1             0x00000002  ///< SS1 Interrupt Status and Clear
00381 #define ADC_ISC_IN0             0x00000001  ///< SS0 Interrupt Status and Clear
00382 /*\}*/
00383 
00387 /*\{*/
00388 #define ADC_OSTAT_OV3           0x00000008  ///< SS3 FIFO Overflow
00389 #define ADC_OSTAT_OV2           0x00000004  ///< SS2 FIFO Overflow
00390 #define ADC_OSTAT_OV1           0x00000002  ///< SS1 FIFO Overflow
00391 #define ADC_OSTAT_OV0           0x00000001  ///< SS0 FIFO Overflow
00392 /*\}*/
00393 
00397 /*\{*/
00398 #define ADC_EMUX_EM3_M          0x0000F000  ///< SS3 Trigger Select
00399 #define ADC_EMUX_EM3_PROCESSOR  0x00000000  ///< Processor (default)
00400 #define ADC_EMUX_EM3_COMP0      0x00001000  ///< Analog Comparator 0
00401 #define ADC_EMUX_EM3_COMP1      0x00002000  ///< Analog Comparator 1
00402 #define ADC_EMUX_EM3_COMP2      0x00003000  ///< Analog Comparator 2
00403 #define ADC_EMUX_EM3_EXTERNAL   0x00004000  ///< External (GPIO PB4)
00404 #define ADC_EMUX_EM3_TIMER      0x00005000  ///< Timer
00405 #define ADC_EMUX_EM3_PWM0       0x00006000  ///< PWM0
00406 #define ADC_EMUX_EM3_PWM1       0x00007000  ///< PWM1
00407 #define ADC_EMUX_EM3_PWM2       0x00008000  ///< PWM2
00408 #define ADC_EMUX_EM3_ALWAYS     0x0000F000  ///< Always (continuously sample)
00409 #define ADC_EMUX_EM2_M          0x00000F00  ///< SS2 Trigger Select
00410 #define ADC_EMUX_EM2_PROCESSOR  0x00000000  ///< Processor (default)
00411 #define ADC_EMUX_EM2_COMP0      0x00000100  ///< Analog Comparator 0
00412 #define ADC_EMUX_EM2_COMP1      0x00000200  ///< Analog Comparator 1
00413 #define ADC_EMUX_EM2_COMP2      0x00000300  ///< Analog Comparator 2
00414 #define ADC_EMUX_EM2_EXTERNAL   0x00000400  ///< External (GPIO PB4)
00415 #define ADC_EMUX_EM2_TIMER      0x00000500  ///< Timer
00416 #define ADC_EMUX_EM2_PWM0       0x00000600  ///< PWM0
00417 #define ADC_EMUX_EM2_PWM1       0x00000700  ///< PWM1
00418 #define ADC_EMUX_EM2_PWM2       0x00000800  ///< PWM2
00419 #define ADC_EMUX_EM2_ALWAYS     0x00000F00  ///< Always (continuously sample)
00420 #define ADC_EMUX_EM1_M          0x000000F0  ///< SS1 Trigger Select
00421 #define ADC_EMUX_EM1_PROCESSOR  0x00000000  ///< Processor (default)
00422 #define ADC_EMUX_EM1_COMP0      0x00000010  ///< Analog Comparator 0
00423 #define ADC_EMUX_EM1_COMP1      0x00000020  ///< Analog Comparator 1
00424 #define ADC_EMUX_EM1_COMP2      0x00000030  ///< Analog Comparator 2
00425 #define ADC_EMUX_EM1_EXTERNAL   0x00000040  ///< External (GPIO PB4)
00426 #define ADC_EMUX_EM1_TIMER      0x00000050  ///< Timer
00427 #define ADC_EMUX_EM1_PWM0       0x00000060  ///< PWM0
00428 #define ADC_EMUX_EM1_PWM1       0x00000070  ///< PWM1
00429 #define ADC_EMUX_EM1_PWM2       0x00000080  ///< PWM2
00430 #define ADC_EMUX_EM1_ALWAYS     0x000000F0  ///< Always (continuously sample)
00431 #define ADC_EMUX_EM0_M          0x0000000F  ///< SS0 Trigger Select
00432 #define ADC_EMUX_EM0_PROCESSOR  0x00000000  ///< Processor (default)
00433 #define ADC_EMUX_EM0_COMP0      0x00000001  ///< Analog Comparator 0
00434 #define ADC_EMUX_EM0_COMP1      0x00000002  ///< Analog Comparator 1
00435 #define ADC_EMUX_EM0_COMP2      0x00000003  ///< Analog Comparator 2
00436 #define ADC_EMUX_EM0_EXTERNAL   0x00000004  ///< External (GPIO PB4)
00437 #define ADC_EMUX_EM0_TIMER      0x00000005  ///< Timer
00438 #define ADC_EMUX_EM0_PWM0       0x00000006  ///< PWM0
00439 #define ADC_EMUX_EM0_PWM1       0x00000007  ///< PWM1
00440 #define ADC_EMUX_EM0_PWM2       0x00000008  ///< PWM2
00441 #define ADC_EMUX_EM0_ALWAYS     0x0000000F  ///< Always (continuously sample)
00442 /*\}*/
00443 
00447 /*\{*/
00448 #define ADC_USTAT_UV3           0x00000008  ///< SS3 FIFO Underflow
00449 #define ADC_USTAT_UV2           0x00000004  ///< SS2 FIFO Underflow
00450 #define ADC_USTAT_UV1           0x00000002  ///< SS1 FIFO Underflow
00451 #define ADC_USTAT_UV0           0x00000001  ///< SS0 FIFO Underflow
00452 /*\}*/
00453 
00457 /*\{*/
00458 #define ADC_SSPRI_SS3_M         0x00003000  ///< SS3 Priority
00459 #define ADC_SSPRI_SS3_1ST       0x00000000  ///< First priority
00460 #define ADC_SSPRI_SS3_2ND       0x00001000  ///< Second priority
00461 #define ADC_SSPRI_SS3_3RD       0x00002000  ///< Third priority
00462 #define ADC_SSPRI_SS3_4TH       0x00003000  ///< Fourth priority
00463 #define ADC_SSPRI_SS2_M         0x00000300  ///< SS2 Priority
00464 #define ADC_SSPRI_SS2_1ST       0x00000000  ///< First priority
00465 #define ADC_SSPRI_SS2_2ND       0x00000100  ///< Second priority
00466 #define ADC_SSPRI_SS2_3RD       0x00000200  ///< Third priority
00467 #define ADC_SSPRI_SS2_4TH       0x00000300  ///< Fourth priority
00468 #define ADC_SSPRI_SS1_M         0x00000030  ///< SS1 Priority
00469 #define ADC_SSPRI_SS1_1ST       0x00000000  ///< First priority
00470 #define ADC_SSPRI_SS1_2ND       0x00000010  ///< Second priority
00471 #define ADC_SSPRI_SS1_3RD       0x00000020  ///< Third priority
00472 #define ADC_SSPRI_SS1_4TH       0x00000030  ///< Fourth priority
00473 #define ADC_SSPRI_SS0_M         0x00000003  ///< SS0 Priority
00474 #define ADC_SSPRI_SS0_1ST       0x00000000  ///< First priority
00475 #define ADC_SSPRI_SS0_2ND       0x00000001  ///< Second priority
00476 #define ADC_SSPRI_SS0_3RD       0x00000002  ///< Third priority
00477 #define ADC_SSPRI_SS0_4TH       0x00000003  ///< Fourth priority
00478 /*\}*/
00479 
00483 /*\{*/
00484 #define ADC_PSSI_SS3            0x00000008  ///< SS3 Initiate
00485 #define ADC_PSSI_SS2            0x00000004  ///< SS2 Initiate
00486 #define ADC_PSSI_SS1            0x00000002  ///< SS1 Initiate
00487 #define ADC_PSSI_SS0            0x00000001  ///< SS0 Initiate
00488 /*\}*/
00489 
00493 /*\{*/
00494 #define ADC_SAC_AVG_M           0x00000007  ///< Hardware Averaging Control
00495 #define ADC_SAC_AVG_OFF         0x00000000  ///< No hardware oversampling
00496 #define ADC_SAC_AVG_2X          0x00000001  ///< 2x hardware oversampling
00497 #define ADC_SAC_AVG_4X          0x00000002  ///< 4x hardware oversampling
00498 #define ADC_SAC_AVG_8X          0x00000003  ///< 8x hardware oversampling
00499 #define ADC_SAC_AVG_16X         0x00000004  ///< 16x hardware oversampling
00500 #define ADC_SAC_AVG_32X         0x00000005  ///< 32x hardware oversampling
00501 #define ADC_SAC_AVG_64X         0x00000006  ///< 64x hardware oversampling
00502 /*\}*/
00503 
00507 /*\{*/
00508 #define ADC_SSMUX0_MUX7_M       0x70000000  ///< 8th Sample Input Select
00509 #define ADC_SSMUX0_MUX6_M       0x07000000  ///< 7th Sample Input Select
00510 #define ADC_SSMUX0_MUX5_M       0x00700000  ///< 6th Sample Input Select
00511 #define ADC_SSMUX0_MUX4_M       0x00070000  ///< 5th Sample Input Select
00512 #define ADC_SSMUX0_MUX3_M       0x00007000  ///< 4th Sample Input Select
00513 #define ADC_SSMUX0_MUX2_M       0x00000700  ///< 3rd Sample Input Select
00514 #define ADC_SSMUX0_MUX1_M       0x00000070  ///< 2nd Sample Input Select
00515 #define ADC_SSMUX0_MUX0_M       0x00000007  ///< 1st Sample Input Select
00516 #define ADC_SSMUX0_MUX7_S       28
00517 #define ADC_SSMUX0_MUX6_S       24
00518 #define ADC_SSMUX0_MUX5_S       20
00519 #define ADC_SSMUX0_MUX4_S       16
00520 #define ADC_SSMUX0_MUX3_S       12
00521 #define ADC_SSMUX0_MUX2_S       8
00522 #define ADC_SSMUX0_MUX1_S       4
00523 #define ADC_SSMUX0_MUX0_S       0
00524 /*\}*/
00525 
00529 /*\{*/
00530 #define ADC_SSCTL0_TS7          0x80000000  ///< 8th Sample Temp Sensor Select
00531 #define ADC_SSCTL0_IE7          0x40000000  ///< 8th Sample Interrupt Enable
00532 #define ADC_SSCTL0_END7         0x20000000  ///< 8th Sample is End of Sequence
00533 #define ADC_SSCTL0_D7           0x10000000  ///< 8th Sample Diff Input Select
00534 #define ADC_SSCTL0_TS6          0x08000000  ///< 7th Sample Temp Sensor Select
00535 #define ADC_SSCTL0_IE6          0x04000000  ///< 7th Sample Interrupt Enable
00536 #define ADC_SSCTL0_END6         0x02000000  ///< 7th Sample is End of Sequence
00537 #define ADC_SSCTL0_D6           0x01000000  ///< 7th Sample Diff Input Select
00538 #define ADC_SSCTL0_TS5          0x00800000  ///< 6th Sample Temp Sensor Select
00539 #define ADC_SSCTL0_IE5          0x00400000  ///< 6th Sample Interrupt Enable
00540 #define ADC_SSCTL0_END5         0x00200000  ///< 6th Sample is End of Sequence
00541 #define ADC_SSCTL0_D5           0x00100000  ///< 6th Sample Diff Input Select
00542 #define ADC_SSCTL0_TS4          0x00080000  ///< 5th Sample Temp Sensor Select
00543 #define ADC_SSCTL0_IE4          0x00040000  ///< 5th Sample Interrupt Enable
00544 #define ADC_SSCTL0_END4         0x00020000  ///< 5th Sample is End of Sequence
00545 #define ADC_SSCTL0_D4           0x00010000  ///< 5th Sample Diff Input Select
00546 #define ADC_SSCTL0_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00547 #define ADC_SSCTL0_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00548 #define ADC_SSCTL0_END3         0x00002000  ///< 4th Sample is End of Sequence
00549 #define ADC_SSCTL0_D3           0x00001000  ///< 4th Sample Diff Input Select
00550 #define ADC_SSCTL0_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00551 #define ADC_SSCTL0_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00552 #define ADC_SSCTL0_END2         0x00000200  ///< 3rd Sample is End of Sequence
00553 #define ADC_SSCTL0_D2           0x00000100  ///< 3rd Sample Diff Input Select
00554 #define ADC_SSCTL0_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00555 #define ADC_SSCTL0_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00556 #define ADC_SSCTL0_END1         0x00000020  ///< 2nd Sample is End of Sequence
00557 #define ADC_SSCTL0_D1           0x00000010  ///< 2nd Sample Diff Input Select
00558 #define ADC_SSCTL0_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00559 #define ADC_SSCTL0_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00560 #define ADC_SSCTL0_END0         0x00000002  ///< 1st Sample is End of Sequence
00561 #define ADC_SSCTL0_D0           0x00000001  ///< 1st Sample Diff Input Select
00562 /*\}*/
00563 
00567 /*\{*/
00568 #define ADC_SSFIFO0_DATA_M      0x000003FF  ///< Conversion Result Data
00569 #define ADC_SSFIFO0_DATA_S      0
00570 /*\}*/
00571 
00575 /*\{*/
00576 #define ADC_SSFSTAT0_FULL       0x00001000  ///< FIFO Full
00577 #define ADC_SSFSTAT0_EMPTY      0x00000100  ///< FIFO Empty
00578 #define ADC_SSFSTAT0_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00579 #define ADC_SSFSTAT0_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00580 #define ADC_SSFSTAT0_HPTR_S     4
00581 #define ADC_SSFSTAT0_TPTR_S     0
00582 /*\}*/
00583 
00587 /*\{*/
00588 #define ADC_SSMUX1_MUX3_M       0x00007000  ///< 4th Sample Input Select
00589 #define ADC_SSMUX1_MUX2_M       0x00000700  ///< 3rd Sample Input Select
00590 #define ADC_SSMUX1_MUX1_M       0x00000070  ///< 2nd Sample Input Select
00591 #define ADC_SSMUX1_MUX0_M       0x00000007  ///< 1st Sample Input Select
00592 #define ADC_SSMUX1_MUX3_S       12
00593 #define ADC_SSMUX1_MUX2_S       8
00594 #define ADC_SSMUX1_MUX1_S       4
00595 #define ADC_SSMUX1_MUX0_S       0
00596 /*\}*/
00597 
00601 /*\{*/
00602 #define ADC_SSCTL1_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00603 #define ADC_SSCTL1_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00604 #define ADC_SSCTL1_END3         0x00002000  ///< 4th Sample is End of Sequence
00605 #define ADC_SSCTL1_D3           0x00001000  ///< 4th Sample Diff Input Select
00606 #define ADC_SSCTL1_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00607 #define ADC_SSCTL1_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00608 #define ADC_SSCTL1_END2         0x00000200  ///< 3rd Sample is End of Sequence
00609 #define ADC_SSCTL1_D2           0x00000100  ///< 3rd Sample Diff Input Select
00610 #define ADC_SSCTL1_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00611 #define ADC_SSCTL1_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00612 #define ADC_SSCTL1_END1         0x00000020  ///< 2nd Sample is End of Sequence
00613 #define ADC_SSCTL1_D1           0x00000010  ///< 2nd Sample Diff Input Select
00614 #define ADC_SSCTL1_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00615 #define ADC_SSCTL1_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00616 #define ADC_SSCTL1_END0         0x00000002  ///< 1st Sample is End of Sequence
00617 #define ADC_SSCTL1_D0           0x00000001  ///< 1st Sample Diff Input Select
00618 /*\}*/
00619 
00623 /*\{*/
00624 #define ADC_SSFIFO1_DATA_M      0x000003FF  ///< Conversion Result Data
00625 #define ADC_SSFIFO1_DATA_S      0
00626 /*\}*/
00627 
00631 /*\{*/
00632 #define ADC_SSFSTAT1_FULL       0x00001000  ///< FIFO Full
00633 #define ADC_SSFSTAT1_EMPTY      0x00000100  ///< FIFO Empty
00634 #define ADC_SSFSTAT1_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00635 #define ADC_SSFSTAT1_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00636 #define ADC_SSFSTAT1_HPTR_S     4
00637 #define ADC_SSFSTAT1_TPTR_S     0
00638 /*\}*/
00639 
00640 
00644 /*\{*/
00645 #define ADC_SSCTL2_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00646 #define ADC_SSCTL2_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00647 #define ADC_SSCTL2_END3         0x00002000  ///< 4th Sample is End of Sequence
00648 #define ADC_SSCTL2_D3           0x00001000  ///< 4th Sample Diff Input Select
00649 #define ADC_SSCTL2_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00650 #define ADC_SSCTL2_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00651 #define ADC_SSCTL2_END2         0x00000200  ///< 3rd Sample is End of Sequence
00652 #define ADC_SSCTL2_D2           0x00000100  ///< 3rd Sample Diff Input Select
00653 #define ADC_SSCTL2_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00654 #define ADC_SSCTL2_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00655 #define ADC_SSCTL2_END1         0x00000020  ///< 2nd Sample is End of Sequence
00656 #define ADC_SSCTL2_D1           0x00000010  ///< 2nd Sample Diff Input Select
00657 #define ADC_SSCTL2_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00658 #define ADC_SSCTL2_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00659 #define ADC_SSCTL2_END0         0x00000002  ///< 1st Sample is End of Sequence
00660 #define ADC_SSCTL2_D0           0x00000001  ///< 1st Sample Diff Input Select
00661 /*\}*/
00662 
00666 /*\{*/
00667 #define ADC_SSFIFO2_DATA_M      0x000003FF  ///< Conversion Result Data
00668 #define ADC_SSFIFO2_DATA_S      0
00669 /*\}*/
00670 
00674 /*\{*/
00675 #define ADC_SSFSTAT2_FULL       0x00001000  ///< FIFO Full
00676 #define ADC_SSFSTAT2_EMPTY      0x00000100  ///< FIFO Empty
00677 #define ADC_SSFSTAT2_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00678 #define ADC_SSFSTAT2_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00679 #define ADC_SSFSTAT2_HPTR_S     4
00680 #define ADC_SSFSTAT2_TPTR_S     0
00681 /*\}*/
00682 
00686 /*\{*/
00687 #define ADC_SSCTL3_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00688 #define ADC_SSCTL3_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00689 #define ADC_SSCTL3_END0         0x00000002  ///< 1st Sample is End of Sequence
00690 #define ADC_SSCTL3_D0           0x00000001  ///< 1st Sample Diff Input Select
00691 /*\}*/
00692 
00696 /*\{*/
00697 #define ADC_SSFIFO3_DATA_M      0x000003FF  ///< Conversion Result Data
00698 #define ADC_SSFIFO3_DATA_S      0
00699 /*\}*/
00700 
00704 /*\{*/
00705 #define ADC_SSFSTAT3_FULL       0x00001000  ///< FIFO Full
00706 #define ADC_SSFSTAT3_EMPTY      0x00000100  ///< FIFO Empty
00707 #define ADC_SSFSTAT3_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00708 #define ADC_SSFSTAT3_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00709 #define ADC_SSFSTAT3_HPTR_S     4
00710 #define ADC_SSFSTAT3_TPTR_S     0
00711 /*\}*/
00712 
00716 /*\{*/
00717 #define ADC_TMLB_LB             0x00000001  ///< Loopback Mode Enable
00718 /*\}*/
00719 
00724 /*\{*/
00725 #define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  ///< Continuous Sample Counter
00726 #define ADC_SSFIFO_TMLB_CONT    0x00000020  ///< Continuation Sample Indicator
00727 #define ADC_SSFIFO_TMLB_DIFF    0x00000010  ///< Differential Sample Indicator
00728 #define ADC_SSFIFO_TMLB_TS      0x00000008  ///< Temp Sensor Sample Indicator
00729 #define ADC_SSFIFO_TMLB_MUX_M   0x00000007  ///< Analog Input Indicator
00730 #define ADC_SSFIFO_TMLB_CNT_S   6           ///< Sample counter shift
00731 #define ADC_SSFIFO_TMLB_MUX_S   0           ///< Input channel number shift
00732 /*\}*/
00733 
00734 
00735 /*
00736  * The following are defines for the bit fields in the ADC_O_SSMUX0 register.
00737  */
00738 #define ADC_SSMUX0_MUX7_S       28
00739 #define ADC_SSMUX0_MUX6_S       24
00740 #define ADC_SSMUX0_MUX5_S       20
00741 #define ADC_SSMUX0_MUX4_S       16
00742 #define ADC_SSMUX0_MUX3_S       12
00743 #define ADC_SSMUX0_MUX2_S       8
00744 #define ADC_SSMUX0_MUX1_S       4
00745 #define ADC_SSMUX0_MUX0_S       0
00746 
00747 
00748 /*
00749  * The following are defines for the bit fields in the ADC_O_SSCTL0 register.
00750  */
00751 #define ADC_SSCTL0_TS7          0x80000000  ///< 8th Sample Temp Sensor Select
00752 #define ADC_SSCTL0_IE7          0x40000000  ///< 8th Sample Interrupt Enable
00753 #define ADC_SSCTL0_END7         0x20000000  ///< 8th Sample is End of Sequence
00754 #define ADC_SSCTL0_D7           0x10000000  ///< 8th Sample Diff Input Select
00755 #define ADC_SSCTL0_TS6          0x08000000  ///< 7th Sample Temp Sensor Select
00756 #define ADC_SSCTL0_IE6          0x04000000  ///< 7th Sample Interrupt Enable
00757 #define ADC_SSCTL0_END6         0x02000000  ///< 7th Sample is End of Sequence
00758 #define ADC_SSCTL0_D6           0x01000000  ///< 7th Sample Diff Input Select
00759 #define ADC_SSCTL0_TS5          0x00800000  ///< 6th Sample Temp Sensor Select
00760 #define ADC_SSCTL0_IE5          0x00400000  ///< 6th Sample Interrupt Enable
00761 #define ADC_SSCTL0_END5         0x00200000  ///< 6th Sample is End of Sequence
00762 #define ADC_SSCTL0_D5           0x00100000  ///< 6th Sample Diff Input Select
00763 #define ADC_SSCTL0_TS4          0x00080000  ///< 5th Sample Temp Sensor Select
00764 #define ADC_SSCTL0_IE4          0x00040000  ///< 5th Sample Interrupt Enable
00765 #define ADC_SSCTL0_END4         0x00020000  ///< 5th Sample is End of Sequence
00766 #define ADC_SSCTL0_D4           0x00010000  ///< 5th Sample Diff Input Select
00767 #define ADC_SSCTL0_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00768 #define ADC_SSCTL0_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00769 #define ADC_SSCTL0_END3         0x00002000  ///< 4th Sample is End of Sequence
00770 #define ADC_SSCTL0_D3           0x00001000  ///< 4th Sample Diff Input Select
00771 #define ADC_SSCTL0_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00772 #define ADC_SSCTL0_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00773 #define ADC_SSCTL0_END2         0x00000200  ///< 3rd Sample is End of Sequence
00774 #define ADC_SSCTL0_D2           0x00000100  ///< 3rd Sample Diff Input Select
00775 #define ADC_SSCTL0_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00776 #define ADC_SSCTL0_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00777 #define ADC_SSCTL0_END1         0x00000020  ///< 2nd Sample is End of Sequence
00778 #define ADC_SSCTL0_D1           0x00000010  ///< 2nd Sample Diff Input Select
00779 #define ADC_SSCTL0_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00780 #define ADC_SSCTL0_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00781 #define ADC_SSCTL0_END0         0x00000002  ///< 1st Sample is End of Sequence
00782 #define ADC_SSCTL0_D0           0x00000001  ///< 1st Sample Diff Input Select
00783 
00784 
00785 /*
00786  * The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
00787  */
00788 #define ADC_SSFIFO0_DATA_M      0x000003FF  ///< Conversion Result Data
00789 #define ADC_SSFIFO0_DATA_S      0
00790 
00791 
00792 /*
00793  * The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
00794  */
00795 #define ADC_SSFSTAT0_FULL       0x00001000  ///< FIFO Full
00796 #define ADC_SSFSTAT0_EMPTY      0x00000100  ///< FIFO Empty
00797 #define ADC_SSFSTAT0_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00798 #define ADC_SSFSTAT0_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00799 #define ADC_SSFSTAT0_HPTR_S     4
00800 #define ADC_SSFSTAT0_TPTR_S     0
00801 
00802 
00803 /*
00804  * The following are defines for the bit fields in the ADC_O_SSOP0 register.
00805  */
00806 #define ADC_SSOP0_S7DCOP        0x10000000  ///< Sample 7 Digital Comparator
00807 
00808 #define ADC_SSOP0_S6DCOP        0x01000000  ///< Sample 6 Digital Comparator
00809 
00810 #define ADC_SSOP0_S5DCOP        0x00100000  ///< Sample 5 Digital Comparator
00811 
00812 #define ADC_SSOP0_S4DCOP        0x00010000  ///< Sample 4 Digital Comparator
00813 
00814 #define ADC_SSOP0_S3DCOP        0x00001000  ///< Sample 3 Digital Comparator
00815 
00816 #define ADC_SSOP0_S2DCOP        0x00000100  ///< Sample 2 Digital Comparator
00817 
00818 #define ADC_SSOP0_S1DCOP        0x00000010  ///< Sample 1 Digital Comparator
00819 
00820 #define ADC_SSOP0_S0DCOP        0x00000001  ///< Sample 0 Digital Comparator
00821 
00822 
00823 
00824 /*
00825  * The following are defines for the bit fields in the ADC_O_SSDC0 register.
00826  */
00827 #define ADC_SSDC0_S7DCSEL_M     0xF0000000  ///< Sample 7 Digital Comparator
00828 
00829 #define ADC_SSDC0_S6DCSEL_M     0x0F000000  ///< Sample 6 Digital Comparator
00830 
00831 #define ADC_SSDC0_S5DCSEL_M     0x00F00000  ///< Sample 5 Digital Comparator
00832 
00833 #define ADC_SSDC0_S4DCSEL_M     0x000F0000  ///< Sample 4 Digital Comparator
00834 
00835 #define ADC_SSDC0_S3DCSEL_M     0x0000F000  ///< Sample 3 Digital Comparator
00836 
00837 #define ADC_SSDC0_S2DCSEL_M     0x00000F00  ///< Sample 2 Digital Comparator
00838 
00839 #define ADC_SSDC0_S1DCSEL_M     0x000000F0  ///< Sample 1 Digital Comparator
00840 
00841 #define ADC_SSDC0_S0DCSEL_M     0x0000000F  ///< Sample 0 Digital Comparator
00842 
00843 #define ADC_SSDC0_S6DCSEL_S     24
00844 #define ADC_SSDC0_S5DCSEL_S     20
00845 #define ADC_SSDC0_S4DCSEL_S     16
00846 #define ADC_SSDC0_S3DCSEL_S     12
00847 #define ADC_SSDC0_S2DCSEL_S     8
00848 #define ADC_SSDC0_S1DCSEL_S     4
00849 #define ADC_SSDC0_S0DCSEL_S     0
00850 
00851 
00852 /*
00853  * The following are defines for the bit fields in the ADC_O_SSCTL1 register.
00854  */
00855 #define ADC_SSCTL1_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00856 #define ADC_SSCTL1_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00857 #define ADC_SSCTL1_END3         0x00002000  ///< 4th Sample is End of Sequence
00858 #define ADC_SSCTL1_D3           0x00001000  ///< 4th Sample Diff Input Select
00859 #define ADC_SSCTL1_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00860 #define ADC_SSCTL1_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00861 #define ADC_SSCTL1_END2         0x00000200  ///< 3rd Sample is End of Sequence
00862 #define ADC_SSCTL1_D2           0x00000100  ///< 3rd Sample Diff Input Select
00863 #define ADC_SSCTL1_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00864 #define ADC_SSCTL1_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00865 #define ADC_SSCTL1_END1         0x00000020  ///< 2nd Sample is End of Sequence
00866 #define ADC_SSCTL1_D1           0x00000010  ///< 2nd Sample Diff Input Select
00867 #define ADC_SSCTL1_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00868 #define ADC_SSCTL1_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00869 #define ADC_SSCTL1_END0         0x00000002  ///< 1st Sample is End of Sequence
00870 #define ADC_SSCTL1_D0           0x00000001  ///< 1st Sample Diff Input Select
00871 
00872 
00873 /*
00874  * The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
00875  */
00876 #define ADC_SSFIFO1_DATA_M      0x000003FF  ///< Conversion Result Data
00877 #define ADC_SSFIFO1_DATA_S      0
00878 
00879 
00880 /*
00881  * The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
00882  */
00883 #define ADC_SSFSTAT1_FULL       0x00001000  ///< FIFO Full
00884 #define ADC_SSFSTAT1_EMPTY      0x00000100  ///< FIFO Empty
00885 #define ADC_SSFSTAT1_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00886 #define ADC_SSFSTAT1_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00887 #define ADC_SSFSTAT1_HPTR_S     4
00888 #define ADC_SSFSTAT1_TPTR_S     0
00889 
00890 
00891 /*
00892  * The following are defines for the bit fields in the ADC_O_SSOP1 register.
00893  */
00894 #define ADC_SSOP1_S3DCOP        0x00001000  ///< Sample 3 Digital Comparator
00895 
00896 #define ADC_SSOP1_S2DCOP        0x00000100  ///< Sample 2 Digital Comparator
00897 
00898 #define ADC_SSOP1_S1DCOP        0x00000010  ///< Sample 1 Digital Comparator
00899 
00900 #define ADC_SSOP1_S0DCOP        0x00000001  ///< Sample 0 Digital Comparator
00901 
00902 
00903 
00904 /*
00905  * The following are defines for the bit fields in the ADC_O_SSDC1 register.
00906  */
00907 #define ADC_SSDC1_S3DCSEL_M     0x0000F000  ///< Sample 3 Digital Comparator
00908 
00909 #define ADC_SSDC1_S2DCSEL_M     0x00000F00  ///< Sample 2 Digital Comparator
00910 
00911 #define ADC_SSDC1_S1DCSEL_M     0x000000F0  ///< Sample 1 Digital Comparator
00912 
00913 #define ADC_SSDC1_S0DCSEL_M     0x0000000F  ///< Sample 0 Digital Comparator
00914 
00915 #define ADC_SSDC1_S2DCSEL_S     8
00916 #define ADC_SSDC1_S1DCSEL_S     4
00917 #define ADC_SSDC1_S0DCSEL_S     0
00918 
00919 
00920 /*
00921  * The following are defines for the bit fields in the ADC_O_SSMUX2 register.
00922  */
00923 #define ADC_SSMUX2_MUX3_M       0x0000F000  ///< 4th Sample Input Select
00924 #define ADC_SSMUX2_MUX2_M       0x00000F00  ///< 3rd Sample Input Select
00925 #define ADC_SSMUX2_MUX1_M       0x000000F0  ///< 2nd Sample Input Select
00926 #define ADC_SSMUX2_MUX0_M       0x0000000F  ///< 1st Sample Input Select
00927 #define ADC_SSMUX2_MUX3_S       12
00928 #define ADC_SSMUX2_MUX2_S       8
00929 #define ADC_SSMUX2_MUX1_S       4
00930 #define ADC_SSMUX2_MUX0_S       0
00931 
00932 
00933 /*
00934  * The following are defines for the bit fields in the ADC_O_SSCTL2 register.
00935  */
00936 #define ADC_SSCTL2_TS3          0x00008000  ///< 4th Sample Temp Sensor Select
00937 #define ADC_SSCTL2_IE3          0x00004000  ///< 4th Sample Interrupt Enable
00938 #define ADC_SSCTL2_END3         0x00002000  ///< 4th Sample is End of Sequence
00939 #define ADC_SSCTL2_D3           0x00001000  ///< 4th Sample Diff Input Select
00940 #define ADC_SSCTL2_TS2          0x00000800  ///< 3rd Sample Temp Sensor Select
00941 #define ADC_SSCTL2_IE2          0x00000400  ///< 3rd Sample Interrupt Enable
00942 #define ADC_SSCTL2_END2         0x00000200  ///< 3rd Sample is End of Sequence
00943 #define ADC_SSCTL2_D2           0x00000100  ///< 3rd Sample Diff Input Select
00944 #define ADC_SSCTL2_TS1          0x00000080  ///< 2nd Sample Temp Sensor Select
00945 #define ADC_SSCTL2_IE1          0x00000040  ///< 2nd Sample Interrupt Enable
00946 #define ADC_SSCTL2_END1         0x00000020  ///< 2nd Sample is End of Sequence
00947 #define ADC_SSCTL2_D1           0x00000010  ///< 2nd Sample Diff Input Select
00948 #define ADC_SSCTL2_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
00949 #define ADC_SSCTL2_IE0          0x00000004  ///< 1st Sample Interrupt Enable
00950 #define ADC_SSCTL2_END0         0x00000002  ///< 1st Sample is End of Sequence
00951 #define ADC_SSCTL2_D0           0x00000001  ///< 1st Sample Diff Input Select
00952 
00953 
00954 /*
00955  * The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
00956  */
00957 #define ADC_SSFIFO2_DATA_M      0x000003FF  ///< Conversion Result Data
00958 #define ADC_SSFIFO2_DATA_S      0
00959 
00960 
00961 /*
00962  * The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
00963  */
00964 #define ADC_SSFSTAT2_FULL       0x00001000  ///< FIFO Full
00965 #define ADC_SSFSTAT2_EMPTY      0x00000100  ///< FIFO Empty
00966 #define ADC_SSFSTAT2_HPTR_M     0x000000F0  ///< FIFO Head Pointer
00967 #define ADC_SSFSTAT2_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
00968 #define ADC_SSFSTAT2_HPTR_S     4
00969 #define ADC_SSFSTAT2_TPTR_S     0
00970 
00971 
00972 /*
00973  * The following are defines for the bit fields in the ADC_O_SSOP2 register.
00974  */
00975 #define ADC_SSOP2_S3DCOP        0x00001000  ///< Sample 3 Digital Comparator
00976 
00977 #define ADC_SSOP2_S2DCOP        0x00000100  ///< Sample 2 Digital Comparator
00978 
00979 #define ADC_SSOP2_S1DCOP        0x00000010  ///< Sample 1 Digital Comparator
00980 
00981 #define ADC_SSOP2_S0DCOP        0x00000001  ///< Sample 0 Digital Comparator
00982 
00983 
00984 
00985 /*
00986  * The following are defines for the bit fields in the ADC_O_SSDC2 register.
00987  */
00988 #define ADC_SSDC2_S3DCSEL_M     0x0000F000  ///< Sample 3 Digital Comparator
00989 
00990 #define ADC_SSDC2_S2DCSEL_M     0x00000F00  ///< Sample 2 Digital Comparator
00991 
00992 #define ADC_SSDC2_S1DCSEL_M     0x000000F0  ///< Sample 1 Digital Comparator
00993 
00994 #define ADC_SSDC2_S0DCSEL_M     0x0000000F  ///< Sample 0 Digital Comparator
00995 
00996 #define ADC_SSDC2_S2DCSEL_S     8
00997 #define ADC_SSDC2_S1DCSEL_S     4
00998 #define ADC_SSDC2_S0DCSEL_S     0
00999 
01000 
01001 /*
01002  * The following are defines for the bit fields in the ADC_O_SSMUX3 register.
01003  */
01004 #define ADC_SSMUX3_MUX0_M       0x0000000F  ///< 1st Sample Input Select
01005 #define ADC_SSMUX3_MUX0_S       0
01006 
01007 
01008 /*
01009  * The following are defines for the bit fields in the ADC_O_SSCTL3 register.
01010  */
01011 #define ADC_SSCTL3_TS0          0x00000008  ///< 1st Sample Temp Sensor Select
01012 #define ADC_SSCTL3_IE0          0x00000004  ///< 1st Sample Interrupt Enable
01013 #define ADC_SSCTL3_END0         0x00000002  ///< 1st Sample is End of Sequence
01014 #define ADC_SSCTL3_D0           0x00000001  ///< 1st Sample Diff Input Select
01015 
01016 
01017 /*
01018  * The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
01019  */
01020 #define ADC_SSFIFO3_DATA_M      0x000003FF  ///< Conversion Result Data
01021 #define ADC_SSFIFO3_DATA_S      0
01022 
01023 
01024 /*
01025  * The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
01026  */
01027 #define ADC_SSFSTAT3_FULL       0x00001000  ///< FIFO Full
01028 #define ADC_SSFSTAT3_EMPTY      0x00000100  ///< FIFO Empty
01029 #define ADC_SSFSTAT3_HPTR_M     0x000000F0  ///< FIFO Head Pointer
01030 #define ADC_SSFSTAT3_TPTR_M     0x0000000F  ///< FIFO Tail Pointer
01031 #define ADC_SSFSTAT3_HPTR_S     4
01032 #define ADC_SSFSTAT3_TPTR_S     0
01033 
01034 
01035 /*
01036  * The following are defines for the bit fields in the ADC_O_SSOP3 register.
01037  */
01038 #define ADC_SSOP3_S0DCOP        0x00000001  ///< Sample 0 Digital Comparator
01039 
01040 
01041 
01042 /*
01043  * The following are defines for the bit fields in the ADC_O_SSDC3 register.
01044  */
01045 #define ADC_SSDC3_S0DCSEL_M     0x0000000F  ///< Sample 0 Digital Comparator
01046 
01047 
01048 
01049 /*
01050  * The following are defines for the bit fields in the ADC_O_TMLB register.
01051  */
01052 #define ADC_TMLB_LB             0x00000001  ///< Loopback Mode Enable
01053 
01054 
01055 /*
01056  * The following are defines for the bit fields in the ADC_O_DCRIC register.
01057  */
01058 #define ADC_DCRIC_DCTRIG7       0x00800000  ///< Digital Comparator Trigger 7
01059 #define ADC_DCRIC_DCTRIG6       0x00400000  ///< Digital Comparator Trigger 6
01060 #define ADC_DCRIC_DCTRIG5       0x00200000  ///< Digital Comparator Trigger 5
01061 #define ADC_DCRIC_DCTRIG4       0x00100000  ///< Digital Comparator Trigger 4
01062 #define ADC_DCRIC_DCTRIG3       0x00080000  ///< Digital Comparator Trigger 3
01063 #define ADC_DCRIC_DCTRIG2       0x00040000  ///< Digital Comparator Trigger 2
01064 #define ADC_DCRIC_DCTRIG1       0x00020000  ///< Digital Comparator Trigger 1
01065 #define ADC_DCRIC_DCTRIG0       0x00010000  ///< Digital Comparator Trigger 0
01066 #define ADC_DCRIC_DCINT7        0x00000080  ///< Digital Comparator Interrupt 7
01067 #define ADC_DCRIC_DCINT6        0x00000040  ///< Digital Comparator Interrupt 6
01068 #define ADC_DCRIC_DCINT5        0x00000020  ///< Digital Comparator Interrupt 5
01069 #define ADC_DCRIC_DCINT4        0x00000010  ///< Digital Comparator Interrupt 4
01070 #define ADC_DCRIC_DCINT3        0x00000008  ///< Digital Comparator Interrupt 3
01071 #define ADC_DCRIC_DCINT2        0x00000004  ///< Digital Comparator Interrupt 2
01072 #define ADC_DCRIC_DCINT1        0x00000002  ///< Digital Comparator Interrupt 1
01073 #define ADC_DCRIC_DCINT0        0x00000001  ///< Digital Comparator Interrupt 0
01074 
01075 
01076 /*
01077  * The following are defines for the bit fields in the ADC_O_DCCTL0 register.
01078  */
01079 #define ADC_DCCTL0_CTE          0x00001000  ///< Comparison Trigger Enable
01080 #define ADC_DCCTL0_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01081 #define ADC_DCCTL0_CTC_LOW      0x00000000  ///< Low Band
01082 #define ADC_DCCTL0_CTC_MID      0x00000400  ///< Mid Band
01083 #define ADC_DCCTL0_CTC_HIGH     0x00000C00  ///< High Band
01084 #define ADC_DCCTL0_CTM_M        0x00000300  ///< Comparison Trigger Mode
01085 #define ADC_DCCTL0_CTM_ALWAYS   0x00000000  ///< Always
01086 #define ADC_DCCTL0_CTM_ONCE     0x00000100  ///< Once
01087 #define ADC_DCCTL0_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01088 #define ADC_DCCTL0_CTM_HONCE    0x00000300  ///< Hysteresis Once
01089 #define ADC_DCCTL0_CIE          0x00000010  ///< Comparison Interrupt Enable
01090 #define ADC_DCCTL0_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01091 #define ADC_DCCTL0_CIC_LOW      0x00000000  ///< Low Band
01092 #define ADC_DCCTL0_CIC_MID      0x00000004  ///< Mid Band
01093 #define ADC_DCCTL0_CIC_HIGH     0x0000000C  ///< High Band
01094 #define ADC_DCCTL0_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01095 #define ADC_DCCTL0_CIM_ALWAYS   0x00000000  ///< Always
01096 #define ADC_DCCTL0_CIM_ONCE     0x00000001  ///< Once
01097 #define ADC_DCCTL0_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01098 #define ADC_DCCTL0_CIM_HONCE    0x00000003  ///< Hysteresis Once
01099 
01100 
01101 /*
01102  * The following are defines for the bit fields in the ADC_O_DCCTL1 register.
01103  */
01104 #define ADC_DCCTL1_CTE          0x00001000  ///< Comparison Trigger Enable
01105 #define ADC_DCCTL1_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01106 #define ADC_DCCTL1_CTC_LOW      0x00000000  ///< Low Band
01107 #define ADC_DCCTL1_CTC_MID      0x00000400  ///< Mid Band
01108 #define ADC_DCCTL1_CTC_HIGH     0x00000C00  ///< High Band
01109 #define ADC_DCCTL1_CTM_M        0x00000300  ///< Comparison Trigger Mode
01110 #define ADC_DCCTL1_CTM_ALWAYS   0x00000000  ///< Always
01111 #define ADC_DCCTL1_CTM_ONCE     0x00000100  ///< Once
01112 #define ADC_DCCTL1_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01113 #define ADC_DCCTL1_CTM_HONCE    0x00000300  ///< Hysteresis Once
01114 #define ADC_DCCTL1_CIE          0x00000010  ///< Comparison Interrupt Enable
01115 #define ADC_DCCTL1_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01116 #define ADC_DCCTL1_CIC_LOW      0x00000000  ///< Low Band
01117 #define ADC_DCCTL1_CIC_MID      0x00000004  ///< Mid Band
01118 #define ADC_DCCTL1_CIC_HIGH     0x0000000C  ///< High Band
01119 #define ADC_DCCTL1_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01120 #define ADC_DCCTL1_CIM_ALWAYS   0x00000000  ///< Always
01121 #define ADC_DCCTL1_CIM_ONCE     0x00000001  ///< Once
01122 #define ADC_DCCTL1_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01123 #define ADC_DCCTL1_CIM_HONCE    0x00000003  ///< Hysteresis Once
01124 
01125 
01126 /*
01127  * The following are defines for the bit fields in the ADC_O_DCCTL2 register.
01128  */
01129 #define ADC_DCCTL2_CTE          0x00001000  ///< Comparison Trigger Enable
01130 #define ADC_DCCTL2_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01131 #define ADC_DCCTL2_CTC_LOW      0x00000000  ///< Low Band
01132 #define ADC_DCCTL2_CTC_MID      0x00000400  ///< Mid Band
01133 #define ADC_DCCTL2_CTC_HIGH     0x00000C00  ///< High Band
01134 #define ADC_DCCTL2_CTM_M        0x00000300  ///< Comparison Trigger Mode
01135 #define ADC_DCCTL2_CTM_ALWAYS   0x00000000  ///< Always
01136 #define ADC_DCCTL2_CTM_ONCE     0x00000100  ///< Once
01137 #define ADC_DCCTL2_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01138 #define ADC_DCCTL2_CTM_HONCE    0x00000300  ///< Hysteresis Once
01139 #define ADC_DCCTL2_CIE          0x00000010  ///< Comparison Interrupt Enable
01140 #define ADC_DCCTL2_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01141 #define ADC_DCCTL2_CIC_LOW      0x00000000  ///< Low Band
01142 #define ADC_DCCTL2_CIC_MID      0x00000004  ///< Mid Band
01143 #define ADC_DCCTL2_CIC_HIGH     0x0000000C  ///< High Band
01144 #define ADC_DCCTL2_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01145 #define ADC_DCCTL2_CIM_ALWAYS   0x00000000  ///< Always
01146 #define ADC_DCCTL2_CIM_ONCE     0x00000001  ///< Once
01147 #define ADC_DCCTL2_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01148 #define ADC_DCCTL2_CIM_HONCE    0x00000003  ///< Hysteresis Once
01149 
01150 
01151 /*
01152  * The following are defines for the bit fields in the ADC_O_DCCTL3 register.
01153  */
01154 #define ADC_DCCTL3_CTE          0x00001000  ///< Comparison Trigger Enable
01155 #define ADC_DCCTL3_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01156 #define ADC_DCCTL3_CTC_LOW      0x00000000  ///< Low Band
01157 #define ADC_DCCTL3_CTC_MID      0x00000400  ///< Mid Band
01158 #define ADC_DCCTL3_CTC_HIGH     0x00000C00  ///< High Band
01159 #define ADC_DCCTL3_CTM_M        0x00000300  ///< Comparison Trigger Mode
01160 #define ADC_DCCTL3_CTM_ALWAYS   0x00000000  ///< Always
01161 #define ADC_DCCTL3_CTM_ONCE     0x00000100  ///< Once
01162 #define ADC_DCCTL3_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01163 #define ADC_DCCTL3_CTM_HONCE    0x00000300  ///< Hysteresis Once
01164 #define ADC_DCCTL3_CIE          0x00000010  ///< Comparison Interrupt Enable
01165 #define ADC_DCCTL3_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01166 #define ADC_DCCTL3_CIC_LOW      0x00000000  ///< Low Band
01167 #define ADC_DCCTL3_CIC_MID      0x00000004  ///< Mid Band
01168 #define ADC_DCCTL3_CIC_HIGH     0x0000000C  ///< High Band
01169 #define ADC_DCCTL3_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01170 #define ADC_DCCTL3_CIM_ALWAYS   0x00000000  ///< Always
01171 #define ADC_DCCTL3_CIM_ONCE     0x00000001  ///< Once
01172 #define ADC_DCCTL3_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01173 #define ADC_DCCTL3_CIM_HONCE    0x00000003  ///< Hysteresis Once
01174 
01175 
01176 /*
01177  * The following are defines for the bit fields in the ADC_O_DCCTL4 register.
01178  */
01179 #define ADC_DCCTL4_CTE          0x00001000  ///< Comparison Trigger Enable
01180 #define ADC_DCCTL4_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01181 #define ADC_DCCTL4_CTC_LOW      0x00000000  ///< Low Band
01182 #define ADC_DCCTL4_CTC_MID      0x00000400  ///< Mid Band
01183 #define ADC_DCCTL4_CTC_HIGH     0x00000C00  ///< High Band
01184 #define ADC_DCCTL4_CTM_M        0x00000300  ///< Comparison Trigger Mode
01185 #define ADC_DCCTL4_CTM_ALWAYS   0x00000000  ///< Always
01186 #define ADC_DCCTL4_CTM_ONCE     0x00000100  ///< Once
01187 #define ADC_DCCTL4_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01188 #define ADC_DCCTL4_CTM_HONCE    0x00000300  ///< Hysteresis Once
01189 #define ADC_DCCTL4_CIE          0x00000010  ///< Comparison Interrupt Enable
01190 #define ADC_DCCTL4_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01191 #define ADC_DCCTL4_CIC_LOW      0x00000000  ///< Low Band
01192 #define ADC_DCCTL4_CIC_MID      0x00000004  ///< Mid Band
01193 #define ADC_DCCTL4_CIC_HIGH     0x0000000C  ///< High Band
01194 #define ADC_DCCTL4_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01195 #define ADC_DCCTL4_CIM_ALWAYS   0x00000000  ///< Always
01196 #define ADC_DCCTL4_CIM_ONCE     0x00000001  ///< Once
01197 #define ADC_DCCTL4_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01198 #define ADC_DCCTL4_CIM_HONCE    0x00000003  ///< Hysteresis Once
01199 
01200 
01201 /*
01202  * The following are defines for the bit fields in the ADC_O_DCCTL5 register.
01203  */
01204 #define ADC_DCCTL5_CTE          0x00001000  ///< Comparison Trigger Enable
01205 #define ADC_DCCTL5_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01206 #define ADC_DCCTL5_CTC_LOW      0x00000000  ///< Low Band
01207 #define ADC_DCCTL5_CTC_MID      0x00000400  ///< Mid Band
01208 #define ADC_DCCTL5_CTC_HIGH     0x00000C00  ///< High Band
01209 #define ADC_DCCTL5_CTM_M        0x00000300  ///< Comparison Trigger Mode
01210 #define ADC_DCCTL5_CTM_ALWAYS   0x00000000  ///< Always
01211 #define ADC_DCCTL5_CTM_ONCE     0x00000100  ///< Once
01212 #define ADC_DCCTL5_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01213 #define ADC_DCCTL5_CTM_HONCE    0x00000300  ///< Hysteresis Once
01214 #define ADC_DCCTL5_CIE          0x00000010  ///< Comparison Interrupt Enable
01215 #define ADC_DCCTL5_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01216 #define ADC_DCCTL5_CIC_LOW      0x00000000  ///< Low Band
01217 #define ADC_DCCTL5_CIC_MID      0x00000004  ///< Mid Band
01218 #define ADC_DCCTL5_CIC_HIGH     0x0000000C  ///< High Band
01219 #define ADC_DCCTL5_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01220 #define ADC_DCCTL5_CIM_ALWAYS   0x00000000  ///< Always
01221 #define ADC_DCCTL5_CIM_ONCE     0x00000001  ///< Once
01222 #define ADC_DCCTL5_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01223 #define ADC_DCCTL5_CIM_HONCE    0x00000003  ///< Hysteresis Once
01224 
01225 
01226 /*
01227  * The following are defines for the bit fields in the ADC_O_DCCTL6 register.
01228  */
01229 #define ADC_DCCTL6_CTE          0x00001000  ///< Comparison Trigger Enable
01230 #define ADC_DCCTL6_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01231 #define ADC_DCCTL6_CTC_LOW      0x00000000  ///< Low Band
01232 #define ADC_DCCTL6_CTC_MID      0x00000400  ///< Mid Band
01233 #define ADC_DCCTL6_CTC_HIGH     0x00000C00  ///< High Band
01234 #define ADC_DCCTL6_CTM_M        0x00000300  ///< Comparison Trigger Mode
01235 #define ADC_DCCTL6_CTM_ALWAYS   0x00000000  ///< Always
01236 #define ADC_DCCTL6_CTM_ONCE     0x00000100  ///< Once
01237 #define ADC_DCCTL6_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01238 #define ADC_DCCTL6_CTM_HONCE    0x00000300  ///< Hysteresis Once
01239 #define ADC_DCCTL6_CIE          0x00000010  ///< Comparison Interrupt Enable
01240 #define ADC_DCCTL6_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01241 #define ADC_DCCTL6_CIC_LOW      0x00000000  ///< Low Band
01242 #define ADC_DCCTL6_CIC_MID      0x00000004  ///< Mid Band
01243 #define ADC_DCCTL6_CIC_HIGH     0x0000000C  ///< High Band
01244 #define ADC_DCCTL6_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01245 #define ADC_DCCTL6_CIM_ALWAYS   0x00000000  ///< Always
01246 #define ADC_DCCTL6_CIM_ONCE     0x00000001  ///< Once
01247 #define ADC_DCCTL6_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01248 #define ADC_DCCTL6_CIM_HONCE    0x00000003  ///< Hysteresis Once
01249 
01250 
01251 /*
01252  * The following are defines for the bit fields in the ADC_O_DCCTL7 register.
01253  */
01254 #define ADC_DCCTL7_CTE          0x00001000  ///< Comparison Trigger Enable
01255 #define ADC_DCCTL7_CTC_M        0x00000C00  ///< Comparison Trigger Condition
01256 #define ADC_DCCTL7_CTC_LOW      0x00000000  ///< Low Band
01257 #define ADC_DCCTL7_CTC_MID      0x00000400  ///< Mid Band
01258 #define ADC_DCCTL7_CTC_HIGH     0x00000C00  ///< High Band
01259 #define ADC_DCCTL7_CTM_M        0x00000300  ///< Comparison Trigger Mode
01260 #define ADC_DCCTL7_CTM_ALWAYS   0x00000000  ///< Always
01261 #define ADC_DCCTL7_CTM_ONCE     0x00000100  ///< Once
01262 #define ADC_DCCTL7_CTM_HALWAYS  0x00000200  ///< Hysteresis Always
01263 #define ADC_DCCTL7_CTM_HONCE    0x00000300  ///< Hysteresis Once
01264 #define ADC_DCCTL7_CIE          0x00000010  ///< Comparison Interrupt Enable
01265 #define ADC_DCCTL7_CIC_M        0x0000000C  ///< Comparison Interrupt Condition
01266 #define ADC_DCCTL7_CIC_LOW      0x00000000  ///< Low Band
01267 #define ADC_DCCTL7_CIC_MID      0x00000004  ///< Mid Band
01268 #define ADC_DCCTL7_CIC_HIGH     0x0000000C  ///< High Band
01269 #define ADC_DCCTL7_CIM_M        0x00000003  ///< Comparison Interrupt Mode
01270 #define ADC_DCCTL7_CIM_ALWAYS   0x00000000  ///< Always
01271 #define ADC_DCCTL7_CIM_ONCE     0x00000001  ///< Once
01272 #define ADC_DCCTL7_CIM_HALWAYS  0x00000002  ///< Hysteresis Always
01273 #define ADC_DCCTL7_CIM_HONCE    0x00000003  ///< Hysteresis Once
01274 
01275 
01276 /*
01277  * The following are defines for the bit fields in the ADC_O_DCCMP0 register.
01278  */
01279 #define ADC_DCCMP0_COMP1_M      0x03FF0000  ///< Compare 1
01280 #define ADC_DCCMP0_COMP0_M      0x000003FF  ///< Compare 0
01281 #define ADC_DCCMP0_COMP1_S      16
01282 #define ADC_DCCMP0_COMP0_S      0
01283 
01284 
01285 /*
01286  * The following are defines for the bit fields in the ADC_O_DCCMP1 register.
01287  */
01288 #define ADC_DCCMP1_COMP1_M      0x03FF0000  ///< Compare 1
01289 #define ADC_DCCMP1_COMP0_M      0x000003FF  ///< Compare 0
01290 #define ADC_DCCMP1_COMP1_S      16
01291 #define ADC_DCCMP1_COMP0_S      0
01292 
01293 
01294 /*
01295  * The following are defines for the bit fields in the ADC_O_DCCMP2 register.
01296  */
01297 #define ADC_DCCMP2_COMP1_M      0x03FF0000  ///< Compare 1
01298 #define ADC_DCCMP2_COMP0_M      0x000003FF  ///< Compare 0
01299 #define ADC_DCCMP2_COMP1_S      16
01300 #define ADC_DCCMP2_COMP0_S      0
01301 
01302 
01303 /*
01304  * The following are defines for the bit fields in the ADC_O_DCCMP3 register.
01305  */
01306 #define ADC_DCCMP3_COMP1_M      0x03FF0000  ///< Compare 1
01307 #define ADC_DCCMP3_COMP0_M      0x000003FF  ///< Compare 0
01308 #define ADC_DCCMP3_COMP1_S      16
01309 #define ADC_DCCMP3_COMP0_S      0
01310 
01311 
01312 /*
01313  * The following are defines for the bit fields in the ADC_O_DCCMP4 register.
01314  */
01315 #define ADC_DCCMP4_COMP1_M      0x03FF0000  ///< Compare 1
01316 #define ADC_DCCMP4_COMP0_M      0x000003FF  ///< Compare 0
01317 #define ADC_DCCMP4_COMP1_S      16
01318 #define ADC_DCCMP4_COMP0_S      0
01319 
01320 
01321 /*
01322  * The following are defines for the bit fields in the ADC_O_DCCMP5 register.
01323  */
01324 #define ADC_DCCMP5_COMP1_M      0x03FF0000  ///< Compare 1
01325 #define ADC_DCCMP5_COMP0_M      0x000003FF  ///< Compare 0
01326 #define ADC_DCCMP5_COMP1_S      16
01327 #define ADC_DCCMP5_COMP0_S      0
01328 
01329 
01330 /*
01331  * The following are defines for the bit fields in the ADC_O_DCCMP6 register.
01332  */
01333 #define ADC_DCCMP6_COMP1_M      0x03FF0000  ///< Compare 1
01334 #define ADC_DCCMP6_COMP0_M      0x000003FF  ///< Compare 0
01335 #define ADC_DCCMP6_COMP1_S      16
01336 #define ADC_DCCMP6_COMP0_S      0
01337 
01338 
01339 /*
01340  * The following are defines for the bit fields in the ADC_O_DCCMP7 register.
01341  */
01342 #define ADC_DCCMP7_COMP1_M      0x03FF0000  ///< Compare 1
01343 #define ADC_DCCMP7_COMP0_M      0x000003FF  ///< Compare 0
01344 #define ADC_DCCMP7_COMP1_S      16
01345 #define ADC_DCCMP7_COMP0_S      0
01346 
01347 
01348 /*
01349  * The following are defines for the the interpretation of the data in the
01350  * SSFIFOx when the ADC TMLB is enabled.
01351  */
01352 
01353 #define ADC_SSFIFO_TMLB_CNT_M   0x000003C0  ///< Continuous Sample Counter
01354 #define ADC_SSFIFO_TMLB_CONT    0x00000020  ///< Continuation Sample Indicator
01355 #define ADC_SSFIFO_TMLB_DIFF    0x00000010  ///< Differential Sample Indicator
01356 #define ADC_SSFIFO_TMLB_TS      0x00000008  ///< Temp Sensor Sample Indicator
01357 #define ADC_SSFIFO_TMLB_MUX_M   0x00000007  ///< Analog Input Indicator
01358 #define ADC_SSFIFO_TMLB_CNT_S   6           ///< Sample counter shift
01359 #define ADC_SSFIFO_TMLB_MUX_S   0           ///< Input channel number shift
01360 
01361 #endif /* LM3S_ADC_H */