BeRTOS
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00001 00040 /* 00041 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. 00042 * 00043 * Redistribution and use in source and binary forms, with or without 00044 * modification, are permitted provided that the following conditions 00045 * are met: 00046 * 00047 * 1. Redistributions of source code must retain the above copyright 00048 * notice, this list of conditions and the following disclaimer. 00049 * 2. Redistributions in binary form must reproduce the above copyright 00050 * notice, this list of conditions and the following disclaimer in the 00051 * documentation and/or other materials provided with the distribution. 00052 * 3. Neither the name of the copyright holders nor the names of 00053 * contributors may be used to endorse or promote products derived 00054 * from this software without specific prior written permission. 00055 * 00056 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00057 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00058 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00059 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00060 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00061 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00062 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00063 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00064 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00065 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00066 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00067 * SUCH DAMAGE. 00068 * 00069 * For additional information see http://www.ethernut.de/ 00070 */ 00071 00072 #ifndef AT91_MC_H 00073 #define AT91_MC_H 00074 00075 #define MC_RCR_OFF 0x00000000 ///< MC remap control register offset. 00076 #define MC_RCR (*((reg32_t *)(MC_BASE + MC_RCR_OFF))) ///< MC remap control register address. 00077 #define MC_RCB 0 ///< Remap command. 00078 00079 #define MC_ASR_OFF 0x00000004 ///< MC abort status register offset. 00080 #define MC_ASR (*((reg32_t *)(MC_BASE + MC_ASR_OFF))) ///< MC abort status register address. 00081 #define MC_UNDADD 0 ///< Undefined Addess Abort status. 00082 #define MC_MISADD 1 ///< Misaligned Addess Abort status. 00083 #define MC_ABTSZ_MASK 0x00000300 ///< Abort size status mask. 00084 #define MC_ABTSZ_BYTE 0x00000000 ///< Byte size abort. 00085 #define MC_ABTSZ_HWORD 0x00000100 ///< Half-word size abort. 00086 #define MC_ABTSZ_WORD 0x00000200 ///< Word size abort. 00087 #define MC_ABTTYP_MASK 0x00000C00 ///< Abort type status mask. 00088 #define MC_ABTTYP_DATAR 0x00000000 ///< Data read abort. 00089 #define MC_ABTTYP_DATAW 0x00000400 ///< Data write abort. 00090 #define MC_ABTTYP_FETCH 0x00000800 ///< Code fetch abort. 00091 #define MC_MST_PDC 0x00020000 ///< PDC abort source. 00092 #define MC_MST_ARM 0x00040000 ///< ARM abort source. 00093 #define MC_SVMST_PDC 0x02000000 ///< Saved PDC abort source. 00094 #define MC_SVMST_ARM 0x04000000 ///< Saved ARM abort source. 00095 00096 #define MC_AASR_OFF 0x00000008 ///< MC abort address status register offset. 00097 #define MC_AASR (*((reg32_t *)(MC_BASE + MC_AASR_OFF))) ///< MC abort address status register address. 00098 00099 #define MC_FMR_OFF 0x00000060 ///< MC flash mode register offset. 00100 #define MC_FMR (*((reg32_t *)(MC_BASE + MC_FMR_OFF))) ///< MC flash mode register address. 00101 #define MC_FRDY 0 ///< Flash ready. 00102 #define MC_LOCKE 2 ///< Lock error. 00103 #define MC_PROGE 3 ///< Programming error. 00104 #define MC_NEBP 7 ///< No erase before programming. 00105 #define MC_FWS_MASK 0x00000300 ///< Flash wait state mask. 00106 #define MC_FWS_1R2W 0x00000000 ///< 1 cycle for read, 2 for write operations. 00107 #define MC_FWS_2R3W 0x00000100 ///< 2 cycles for read, 3 for write operations. 00108 #define MC_FWS_3R4W 0x00000200 ///< 3 cycles for read, 4 for write operations. 00109 #define MC_FWS_4R4W 0x00000300 ///< 4 cycles for read and write operations. 00110 #define MC_FMCN_MASK 0x00FF0000 ///< Flash microsecond cycle number mask. 00111 #define MC_FMCN_SHIFT 16 ///< Flash microsecond cycle number shift. 00112 00113 #define MC_FCR_OFF 0x00000064 ///< MC flash command register offset. 00114 #define MC_FCR (*((reg32_t *)(MC_BASE + MC_FCR_OFF))) ///< MC flash command register address. 00115 #define MC_FCMD_MASK 0x0000000F ///< Flash command mask. 00116 #define MC_FCMD_NOP 0x00000000 ///< No command. 00117 #define MC_FCMD_WP 0x00000001 ///< Write page. 00118 #define MC_FCMD_SLB 0x00000002 ///< Set lock bit. 00119 #define MC_FCMD_WPL 0x00000003 ///< Write page and lock. 00120 #define MC_FCMD_CLB 0x00000004 ///< Clear lock bit. 00121 #define MC_FCMD_EA 0x00000008 ///< Erase all. 00122 #define MC_FCMD_SGPB 0x0000000B ///< Set general purpose NVM bit. 00123 #define MC_FCMD_CGPB 0x0000000D ///< Clear general purpose NVM bit. 00124 #define MC_FCMD_SSB 0x0000000F ///< Set security bit. 00125 #define MC_PAGEN_MASK 0x0003FF00 ///< Page number mask. 00126 #define MC_KEY 0x5A000000 ///< Writing protect key. 00127 00128 #define MC_FSR_OFF 0x00000068 ///< MC flash status register offset. 00129 #define MC_FSR (*((reg32_t *)(MC_BASE + MC_FSR_OFF))) ///< MC flash status register address. 00130 #define MC_SECURITY 4 ///< Security bit status. 00131 00132 #define MC_GPNVM0 8 ///< General purpose NVM bit 0. 00133 #define MC_GPNVM1 9 ///< General purpose NVM bit 1. 00134 #define MC_GPNVM2 10 ///< General purpose NVM bit 2. 00135 00136 #define MC_LOCKS0 16 ///< Lock region 0 lock status. 00137 #define MC_LOCKS1 17 ///< Lock region 1 lock status. 00138 #define MC_LOCKS2 18 ///< Lock region 2 lock status. 00139 #define MC_LOCKS3 19 ///< Lock region 3 lock status. 00140 #define MC_LOCKS4 20 ///< Lock region 4 lock status. 00141 #define MC_LOCKS5 21 ///< Lock region 5 lock status. 00142 #define MC_LOCKS6 22 ///< Lock region 6 lock status. 00143 #define MC_LOCKS7 23 ///< Lock region 7 lock status. 00144 #define MC_LOCKS8 24 ///< Lock region 8 lock status. 00145 #define MC_LOCKS9 25 ///< Lock region 9 lock status. 00146 #define MC_LOCKS10 26 ///< Lock region 10 lock status. 00147 #define MC_LOCKS11 27 ///< Lock region 11 lock status. 00148 #define MC_LOCKS12 28 ///< Lock region 12 lock status. 00149 #define MC_LOCKS13 29 ///< Lock region 13 lock status. 00150 #define MC_LOCKS14 30 ///< Lock region 14 lock status. 00151 #define MC_LOCKS15 31 ///< Lock region 15 lock status. 00152 00153 #endif /* AT91_MC_H */