BeRTOS
|
AVR MEGA UART and SPI I/O driver (Implementation) More...
#include "hw/hw_ser.h"
#include <hw/hw_cpufreq.h>
#include "cfg/cfg_ser.h"
#include <cfg/macros.h>
#include <cfg/debug.h>
#include <cfg/cfg_arch.h>
#include <drv/ser.h>
#include <drv/ser_p.h>
#include <drv/timer.h>
#include <struct/fifobuf.h>
#include <avr/io.h>
#include <avr/signal.h>
Go to the source code of this file.
Data Structures | |
struct | AvrSerial |
Internal hardware state structure. More... | |
Defines | |
Hardware handshake (RTS/CTS). | |
#define | RTS_ON do {} while (0) |
Dummy value, must be overridden. | |
#define | RTS_OFF do {} while (0) |
Dummy value, must be overridden. | |
#define | IS_CTS_ON true |
Dummy value, must be overridden. | |
#define | EIMSKF_CTS 0 |
Dummy value, must be overridden. | |
Overridable serial bus hooks | |
These can be redefined in hw.h to implement special bus policies such as half-duplex, 485, etc. TXBEGIN TXCHAR TXEND TXOFF | __________|__________ | | | | | | | | | | | v v v v v v v v v ______ __ __ __ __ __ __ ________________ \/ \/ \/ \/ \/ \/ \/ ______/\__/\__/\__/\__/\__/\__/ | |
#define | SER_UART0_BUS_TXINIT |
Default TXINIT macro - invoked in uart0_init() | |
#define | SER_UART0_BUS_TXBEGIN |
Invoked before starting a transmission. | |
#define | SER_UART0_BUS_TXCHAR(c) |
Invoked to send one character. | |
#define | SER_UART0_BUS_TXEND |
Invoked as soon as the txfifo becomes empty. | |
#define | SER_UART0_BUS_TXOFF |
Invoked after the last character has been transmitted. | |
#define | SER_UART1_BUS_TXINIT |
#define | SER_UART1_BUS_TXBEGIN |
#define | SER_UART1_BUS_TXCHAR(c) |
#define | SER_UART1_BUS_TXEND |
#define | SER_UART1_BUS_TXOFF |
#define | SER_UART2_BUS_TXINIT |
#define | SER_UART2_BUS_TXBEGIN |
#define | SER_UART2_BUS_TXCHAR(c) |
#define | SER_UART2_BUS_TXEND |
#define | SER_UART2_BUS_TXOFF |
#define | SER_UART3_BUS_TXINIT |
#define | SER_UART3_BUS_TXBEGIN |
#define | SER_UART3_BUS_TXCHAR(c) |
#define | SER_UART3_BUS_TXEND |
#define | SER_UART3_BUS_TXOFF |
Overridable SPI hooks | |
These can be redefined in hw.h to implement special bus policies such as slave select pin handling, etc. | |
#define | SER_SPI_BUS_TXINIT |
Default TXINIT macro - invoked in spi_init() The default is no action. | |
#define | SER_SPI_BUS_TXCLOSE |
Invoked after the last character has been transmitted. | |
Functions | |
DECLARE_ISR (USART0_UDRE_vect) | |
Serial 0 TX interrupt handler. | |
DECLARE_ISR (USART0_TX_vect) | |
Serial port 0 TX complete interrupt handler. | |
DECLARE_ISR (USART0_RX_vect) | |
Serial 0 RX complete interrupt handler. | |
DECLARE_ISR (SPI_STC_vect) | |
SPI interrupt handler. |
AVR MEGA UART and SPI I/O driver (Implementation)
Definition in file ser_mega.c.
#define SER_SPI_BUS_TXCLOSE |
Invoked after the last character has been transmitted.
The default is no action.
Definition at line 329 of file ser_mega.c.
#define SER_UART0_BUS_TXBEGIN |
#define SER_UART0_BUS_TXEND |
Invoked as soon as the txfifo becomes empty.
Definition at line 183 of file ser_mega.c.
#define SER_UART0_BUS_TXINIT |
do { \ UCSR0A = 0; /* The Arduino Uno bootloader turns on U2X0 */ \ UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \ } while (0)
Default TXINIT macro - invoked in uart0_init()
Definition at line 148 of file ser_mega.c.
#define SER_UART0_BUS_TXOFF |
Invoked after the last character has been transmitted.
The default is no action.
Definition at line 197 of file ser_mega.c.
#define SER_UART1_BUS_TXBEGIN |
Definition at line 209 of file ser_mega.c.
#define SER_UART1_BUS_TXCHAR | ( | c | ) |
do { \ UDR1 = (c); \ } while (0)
Definition at line 215 of file ser_mega.c.
#define SER_UART1_BUS_TXEND |
Definition at line 221 of file ser_mega.c.
#define SER_UART1_BUS_TXINIT |
Definition at line 203 of file ser_mega.c.
#define SER_UART1_BUS_TXOFF |
Definition at line 232 of file ser_mega.c.
#define SER_UART2_BUS_TXBEGIN |
Definition at line 244 of file ser_mega.c.
#define SER_UART2_BUS_TXCHAR | ( | c | ) |
do { \ UDR2 = (c); \ } while (0)
Definition at line 250 of file ser_mega.c.
#define SER_UART2_BUS_TXEND |
Definition at line 256 of file ser_mega.c.
#define SER_UART2_BUS_TXINIT |
Definition at line 238 of file ser_mega.c.
#define SER_UART2_BUS_TXOFF |
Definition at line 267 of file ser_mega.c.
#define SER_UART3_BUS_TXBEGIN |
Definition at line 279 of file ser_mega.c.
#define SER_UART3_BUS_TXCHAR | ( | c | ) |
do { \ UDR3 = (c); \ } while (0)
Definition at line 285 of file ser_mega.c.
#define SER_UART3_BUS_TXEND |
Definition at line 291 of file ser_mega.c.
#define SER_UART3_BUS_TXINIT |
Definition at line 273 of file ser_mega.c.
#define SER_UART3_BUS_TXOFF |
Definition at line 302 of file ser_mega.c.
DECLARE_ISR | ( | USART0_RX_vect | ) |
Serial 0 RX complete interrupt handler.
This handler is interruptible. Interrupt are reenabled as soon as recv complete interrupt is disabled. Using INTERRUPT() is troublesome when the serial is heavily loaded, because an interrupt could be retriggered when executing the handler prologue before RXCIE is disabled.
Definition at line 1193 of file ser_mega.c.
DECLARE_ISR | ( | USART0_TX_vect | ) |
Serial port 0 TX complete interrupt handler.
This IRQ is usually disabled. The UDR-empty interrupt enables it when there's no more data to transmit. We need to wait until the last character has been transmitted before switching the 485 transceiver to receive mode.
The txfifo might have been refilled by putchar() while we were waiting for the transmission complete interrupt. In this case, we must restart the UDR empty interrupt, otherwise we'd stop the serial port with some data still pending in the buffer.
Definition at line 993 of file ser_mega.c.