BeRTOS
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#include <cfg/compiler.h>
Go to the source code of this file.
Defines | |
#define | AIC_SMR(i) (*((reg32_t *)(AIC_BASE + (i) * 4))) |
Source mode register array. | |
#define | AIC_PRIOR_MASK 0x00000007 |
Priority mask. | |
#define | AIC_SRCTYPE_MASK 0x00000060 |
Interrupt source type mask. | |
#define | AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 |
Internal level sensitive. | |
#define | AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 |
Internal edge triggered. | |
#define | AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 |
External low level. | |
#define | AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 |
External falling edge. | |
#define | AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 |
External high level. | |
#define | AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 |
External rising edge. | |
#define | AIC_SVR(i) (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4))) |
Interrupt Source Vector Registers. | |
#define | AIC_IVR_OFF 0x00000100 |
Interrupt Vector Register. | |
#define | AIC_IVR (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) |
IRQ vector register address. | |
#define | AIC_FVR_OFF 0x00000104 |
Fast Interrupt Vector Register. | |
#define | AIC_FVR (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) |
FIQ vector register address. | |
#define | AIC_ISR_OFF 0x00000108 |
Interrupt Status Register. | |
#define | AIC_ISR (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) |
Interrupt status register address. | |
#define | AIC_IRQID_MASK 0x0000001F |
Current interrupt identifier mask. | |
#define | AIC_IPR_OFF 0x0000010C |
Interrupt Pending Register. | |
#define | AIC_IPR (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) |
Interrupt pending register address. | |
#define | AIC_IMR_OFF 0x00000110 |
Interrupt Mask Register. | |
#define | AIC_IMR (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) |
Interrupt mask register address. | |
#define | AIC_CISR_OFF 0x00000114 |
Interrupt Core Status Register. | |
#define | AIC_CISR (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) |
Core interrupt status register address. | |
#define | AIC_NFIQ 1 |
Core FIQ Status. | |
#define | AIC_NIRQ 2 |
Core IRQ Status. | |
#define | AIC_IECR_OFF 0x00000120 |
Interrupt Enable Command Register. | |
#define | AIC_IECR (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF))) |
Interrupt enable command register address. | |
#define | AIC_IDCR_OFF 0x00000124 |
Interrupt Disable Command Register. | |
#define | AIC_IDCR (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF))) |
Interrupt disable command register address. | |
#define | AIC_ICCR_OFF 0x00000128 |
Interrupt Clear Command Register. | |
#define | AIC_ICCR (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF))) |
Interrupt clear command register address. | |
#define | AIC_ISCR_OFF 0x0000012C |
Interrupt Set Command Register. | |
#define | AIC_ISCR (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF))) |
Interrupt set command register address. | |
#define | AIC_EOICR_OFF 0x00000130 |
End Of Interrupt Command Register. | |
#define | AIC_EOICR (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF))) |
End of interrupt command register address. | |
#define | AIC_SPU_OFF 0x00000134 |
Spurious Interrupt Vector Register. | |
#define | AIC_SPU (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)== |
Spurious vector register address. | |
#define | AIC_DCR_OFF 0x0000138 |
Debug Control Register. | |
#define | AIC_DCR (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF))) |
Debug control register address. | |
#define | AIC_FFER_OFF 0x00000140 |
Fast Forcing Enable Register. | |
#define | AIC_FFER (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF))) |
Fast forcing enable register address. | |
#define | AIC_FFDR_OFF 0x00000144 |
Fast Forcing Disable Register. | |
#define | AIC_FFDR (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF))) |
Fast forcing disable register address. | |
#define | AIC_FFSR_OFF 0x00000148 |
Fast Forcing Status Register. | |
#define | AIC_FFSR (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF))) |
Fast forcing status register address. | |
Typedefs | |
typedef void(* | irq_handler_t )(void) |
Type for interrupt handlers. |
AT91 advanced interrupt controller. This file is based on NUT/OS implementation. See license below.
Definition in file at91_aic.h.
#define AIC_CISR_OFF 0x00000114 |
Interrupt Core Status Register.
Core interrupt status register offset.
Definition at line 156 of file at91_aic.h.
#define AIC_DCR_OFF 0x0000138 |
#define AIC_EOICR_OFF 0x00000130 |
End Of Interrupt Command Register.
End of interrupt command register offset.
Definition at line 188 of file at91_aic.h.
#define AIC_FFDR_OFF 0x00000144 |
Fast Forcing Disable Register.
Fast forcing disable register address.
Definition at line 212 of file at91_aic.h.
#define AIC_FFER_OFF 0x00000140 |
Fast Forcing Enable Register.
Fast forcing enable register offset.
Definition at line 206 of file at91_aic.h.
#define AIC_FFSR_OFF 0x00000148 |
Fast Forcing Status Register.
Fast forcing status register address.
Definition at line 218 of file at91_aic.h.
#define AIC_FVR_OFF 0x00000104 |
Fast Interrupt Vector Register.
FIQ vector register offset.
Definition at line 131 of file at91_aic.h.
#define AIC_ICCR_OFF 0x00000128 |
Interrupt Clear Command Register.
Interrupt clear command register offset.
Definition at line 176 of file at91_aic.h.
#define AIC_IDCR_OFF 0x00000124 |
Interrupt Disable Command Register.
Interrupt disable command register offset.
Definition at line 170 of file at91_aic.h.
#define AIC_IECR_OFF 0x00000120 |
Interrupt Enable Command Register.
Interrupt enable command register offset.
Definition at line 164 of file at91_aic.h.
#define AIC_IMR_OFF 0x00000110 |
#define AIC_IPR_OFF 0x0000010C |
Interrupt Pending Register.
Interrupt pending register offset.
Definition at line 144 of file at91_aic.h.
#define AIC_ISCR_OFF 0x0000012C |
Interrupt Set Command Register.
Interrupt set command register offset.
Definition at line 182 of file at91_aic.h.
#define AIC_ISR_OFF 0x00000108 |
Interrupt Status Register.
Interrupt status register offset.
Definition at line 137 of file at91_aic.h.
#define AIC_IVR_OFF 0x00000100 |
#define AIC_PRIOR_MASK 0x00000007 |
Priority mask.
Priority levels can be between 0 (lowest) and 7 (highest).
Definition at line 88 of file at91_aic.h.
#define AIC_SPU_OFF 0x00000134 |
Spurious Interrupt Vector Register.
Spurious vector register offset.
Definition at line 194 of file at91_aic.h.
#define AIC_SRCTYPE_MASK 0x00000060 |
Interrupt source type mask.
Internal interrupts can level sensitive or edge triggered.
External interrupts can triggered on positive or negative levels or on rising or falling edges.
Definition at line 98 of file at91_aic.h.
#define AIC_SVR | ( | i | ) | (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4))) |
Interrupt Source Vector Registers.
Source vector register array.
Stores the addresses of the corresponding interrupt handlers.
Definition at line 120 of file at91_aic.h.