BeRTOS
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00001 00036 #ifndef SAM3_SDRAMC_H 00037 #define SAM3_SDRAMC_H 00038 00039 #include <cfg/macros.h> 00040 00041 00042 #if CPU_CM3_SAM3X 00043 00045 #define SDRAMC_BASE 0x400E0200 00046 00047 00051 /*\{*/ 00052 #define SDRAMC_MR_OFF 0x00 ///< Mode Register 00053 #define SDRAMC_TR_OFF 0x04 ///< Refresh Timer Register 00054 #define SDRAMC_CR_OFF 0x08 ///< Configuration Register 00055 #define SDRAMC_LPR_OFF 0x10 ///< Low Power Register 00056 #define SDRAMC_IER_OFF 0x14 ///< Interrupt Enable Register 00057 #define SDRAMC_IDR_OFF 0x18 ///< Interrupt Disable Register 00058 #define SDRAMC_IMR_OFF 0x1C ///< Interrupt Mask Register 00059 #define SDRAMC_ISR_OFF 0x20 ///< Interrupt Status Register 00060 #define SDRAMC_MDR_OFF 0x24 ///< Memory Device Register 00061 #define SDRAMC_CR1_OFF 0x28 ///< Configuration Register 1 00062 #define SDRAMC_OCMS_OFF 0x2C ///< OCMS Register 1 00063 /*\}*/ 00064 00068 /*\{*/ 00069 #define SDRAMC_MR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_MR_OFF )) 00070 #define SDRAMC_TR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_TR_OFF )) 00071 #define SDRAMC_CR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_CR_OFF )) 00072 #define SDRAMC_LPR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_LPR_OFF )) 00073 #define SDRAMC_IER (*(reg32_t *)(SDRAMC_BASE + SDRAMC_IER_OFF )) 00074 #define SDRAMC_IDR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_IDR_OFF )) 00075 #define SDRAMC_IMR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_IMR_OFF )) 00076 #define SDRAMC_ISR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_ISR_OFF )) 00077 #define SDRAMC_MDR (*(reg32_t *)(SDRAMC_BASE + SDRAMC_MDR_OFF )) 00078 #define SDRAMC_CR1 (*(reg32_t *)(SDRAMC_BASE + SDRAMC_CR1_OFF )) 00079 #define SDRAMC_OCMS (*(reg32_t *)(SDRAMC_BASE + SDRAMC_OCMS_OFF)) 00080 /*\}*/ 00081 00082 00086 /*\{*/ 00087 #define SDRAMC_MR_MODE_MASK 0x7 00088 #define SDRAMC_MR_MODE_NORMAL 0x0 ///< Normal mode. Any access to the SDRAM is decoded normally. To activate this mode, command must be followed by a write to the SDRAM. 00089 #define SDRAMC_MR_MODE_NOP 0x1 ///< The SDRAM Controller issues a NOP command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 00090 #define SDRAMC_MR_MODE_ALLBANKS_PRECHARGE 0x2 ///< The SDRAM Controller issues an "All Banks Precharge" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 00091 #define SDRAMC_MR_MODE_LOAD_MODEREG 0x3 ///< The SDRAM Controller issues a "Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, command must be followed by a write to the SDRAM. 00092 #define SDRAMC_MR_MODE_AUTO_REFRESH 0x4 ///< The SDRAM Controller issues an "Auto-Refresh" Command when the SDRAM device is accessed regardless of the cycle. Previously, an "All Banks Precharge" command must be issued. To activate this mode, command must be followed by a write to the SDRAM. 00093 #define SDRAMC_MR_MODE_EXT_LOAD_MODEREG 0x5 ///< The SDRAM Controller issues an "Extended Load Mode Register" command when the SDRAM device is accessed regardless of the cycle. To activate this mode, the "Extended Load Mode Register" command must be followed by a write to the SDRAM. The write in the SDRAM must be done in the appropriate bank; most low-power SDRAM devices use the bank 1. 00094 #define SDRAMC_MR_MODE_DEEP_POWERDOWN 0x6 ///< Deep power-down mode. Enters deep power-down mode. 00095 /*\}*/ 00096 00100 /*\{*/ 00101 #define SDRAMC_TR_COUNT_MASK 0xfff 00102 #define SDRAMC_TR_COUNT(value) (SDRAMC_TR_COUNT_MASK & (value)) 00103 /*\}*/ 00104 00108 /*\{*/ 00109 #define SDRAMC_CR_NC_SHIFT 0 00110 #define SDRAMC_CR_NC_MASK 0x3 ///< Number of Column Bits 00111 #define SDRAMC_CR_NC_COL8 0x0 ///< 8 column bits 00112 #define SDRAMC_CR_NC_COL9 0x1 ///< 9 column bits 00113 #define SDRAMC_CR_NC_COL10 0x2 ///< 10 column bits 00114 #define SDRAMC_CR_NC_COL11 0x3 ///< 11 column bits 00115 #define SDRAMC_CR_NR_SHIFT 2 00116 #define SDRAMC_CR_NR_MASK (0x3 << 2) ///< Number of Row Bits 00117 #define SDRAMC_CR_NR_ROW11 (0x0 << 2) ///< 11 row bits 00118 #define SDRAMC_CR_NR_ROW12 (0x1 << 2) ///< 12 row bits 00119 #define SDRAMC_CR_NR_ROW13 (0x2 << 2) ///< 13 row bits 00120 #define SDRAMC_CR_NB (0x1 << 4) ///< Number of Banks 00121 #define SDRAMC_CR_NB_BANK2 (0x0 << 4) ///< 2 banks 00122 #define SDRAMC_CR_NB_BANK4 (0x1 << 4) ///< 4 banks 00123 #define SDRAMC_CR_CAS_SHIFT 5 00124 #define SDRAMC_CR_CAS_MASK (0x3 << SDRAMC_CR_CAS_SHIFT) ///< CAS Latency 00125 #define SDRAMC_CR_CAS_LATENCY1 (0x1 << 5) ///< 1 cycle CAS latency 00126 #define SDRAMC_CR_CAS_LATENCY2 (0x2 << 5) ///< 2 cycle CAS latency 00127 #define SDRAMC_CR_CAS_LATENCY3 (0x3 << 5) ///< 3 cycle CAS latency 00128 #define SDRAMC_CR_DBW (0x1 << 7) ///< Data Bus Width 00129 #define SDRAMC_CR_TWR_SHIFT 8 00130 #define SDRAMC_CR_TWR_MASK (0xf << SDRAMC_CR_TWR_SHIFT) ///< Write Recovery Delay 00131 #define SDRAMC_CR_TWR(value) (SDRAMC_CR_TWR_MASK & ((value) << SDRAMC_CR_TWR_SHIFT)) 00132 #define SDRAMC_CR_TRC_TRFC_SHIFT 12 00133 #define SDRAMC_CR_TRC_TRFC_MASK (0xf << SDRAMC_CR_TRC_TRFC_SHIFT) ///< Row Cycle Delay and Row Refresh Cycle 00134 #define SDRAMC_CR_TRC_TRFC(value) (SDRAMC_CR_TRC_TRFC_MASK & ((value) << SDRAMC_CR_TRC_TRFC_SHIFT)) 00135 #define SDRAMC_CR_TRP_SHIFT 16 00136 #define SDRAMC_CR_TRP_MASK (0xf << SDRAMC_CR_TRP_SHIFT) ///< Row Precharge Delay 00137 #define SDRAMC_CR_TRP(value) (SDRAMC_CR_TRP_MASK & ((value) << SDRAMC_CR_TRP_SHIFT)) 00138 #define SDRAMC_CR_TRCD_SHIFT 20 00139 #define SDRAMC_CR_TRCD_MASK (0xf << SDRAMC_CR_TRCD_SHIFT) ///< Row to Column Delay 00140 #define SDRAMC_CR_TRCD(value) (SDRAMC_CR_TRCD_MASK & ((value) << SDRAMC_CR_TRCD_SHIFT)) 00141 #define SDRAMC_CR_TRAS_SHIFT 24 00142 #define SDRAMC_CR_TRAS_MASK (0xf << SDRAMC_CR_TRAS_SHIFT) ///< Active to Precharge Delay 00143 #define SDRAMC_CR_TRAS(value) (SDRAMC_CR_TRAS_MASK & ((value) << SDRAMC_CR_TRAS_SHIFT)) 00144 #define SDRAMC_CR_TXSR_SHIFT 28 00145 #define SDRAMC_CR_TXSR_MASK (0xf << SDRAMC_CR_TXSR_SHIFT) ///< Exit Self Refresh to Active Delay 00146 #define SDRAMC_CR_TXSR(value) (SDRAMC_CR_TXSR_MASK & ((value) << SDRAMC_CR_TXSR_SHIFT)) 00147 /*\}*/ 00148 00152 /*\{*/ 00153 #define SDRAMC_MDR_MD_MASK 0x3 00154 #define SDRAMC_MDR_MD_SDRAM 0x0 00155 #define SDRAMC_MDR_MD_LPSDRAM 0x1 00156 /*\}*/ 00157 00158 #endif /* CPU_CM_SAM3X */ 00159 00160 #endif /* SAM3_SDRAMC_H */