Defines |
#define | TC_TC0_OFF 0x00000000 |
| Timer Counter Control Register.
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#define | TC_TC1_OFF 0x00000040 |
| Channel 1 control register offset.
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#define | TC_TC2_OFF 0x00000080 |
| Channel 2 control register offset.
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#define | TC0_CCR (*((reg32_t *)(TC_BASE + TC_TC0_OFF))) |
| Channel 0 control register address.
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#define | TC1_CCR (*((reg32_t *)(TC_BASE + TC_TC1_OFF))) |
| Channel 1 control register address.
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#define | TC2_CCR (*((reg32_t *)(TC_BASE + TC_TC2_OFF))) |
| Channel 2 control register address.
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#define | TC_CLKEN 0 |
| Clock enable command.
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#define | TC_CLKDIS 1 |
| Clock disable command.
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#define | TC_SWTRG 2 |
| Software trigger command.
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#define | TC_CMR_OFF 0x00000004 |
| Timer Counter Channel Mode Register.
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#define | TC0_CMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CMR_OFF))) |
| Channel 0 mode register address.
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#define | TC1_CMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CMR_OFF))) |
| Channel 1 mode register address.
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#define | TC2_CMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CMR_OFF))) |
| Channel 2 mode register address.
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#define | TC_CLKS_MASK 0x00000007 |
| Clock selection mask.
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#define | TC_CLKS_MCK2 0x00000000 |
| Selects MCK / 2.
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#define | TC_CLKS_MCK8 0x00000001 |
| Selects MCK / 8.
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#define | TC_CLKS_MCK32 0x00000002 |
| Selects MCK / 32.
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#define | TC_CLKS_MCK128 0x00000003 |
| Selects MCK / 128.
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#define | TC_CLKS_MCK1024 0x00000004 |
| Selects MCK / 1024.
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#define | TC_CLKS_XC0 0x00000005 |
| Selects external clock 0.
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#define | TC_CLKS_XC1 0x00000006 |
| Selects external clock 1.
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#define | TC_CLKS_XC2 0x00000007 |
| Selects external clock 2.
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#define | TC_CLKI 3 |
| Increments on falling edge.
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#define | TC_BURST_MASK 0x00000030 |
| Burst signal selection mask.
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#define | TC_BURST_NONE 0x00000000 |
| Clock is not gated by an external signal.
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#define | TC_BUSRT_XC0 0x00000010 |
| ANDed with external clock 0.
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#define | TC_BURST_XC1 0x00000020 |
| ANDed with external clock 1.
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#define | TC_BURST_XC2 0x00000030 |
| ANDed with external clock 2.
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#define | TC_WAVE 15 |
| Selects waveform mode.
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#define | TC_CPCTRG 14 |
| Capture Mode.
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#define | TC_LDBSTOP 6 |
| Counter clock stopped on RB loading.
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#define | TC_LDBDIS 7 |
| Counter clock disabled on RB loading.
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#define | TC_ETRGEDG_MASK 0x00000300 |
| External trigger edge selection mask.
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#define | TC_ETRGEDG_RISING_EDGE 0x00000100 |
| Trigger on external rising edge.
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#define | TC_ETRGEDG_FALLING_EDGE 0x00000200 |
| Trigger on external falling edge.
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#define | TC_ETRGEDG_BOTH_EDGE 0x00000300 |
| Trigger on both external edges.
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#define | TC_ABETRG_MASK 0x00000400 |
| TIOA or TIOB external trigger selection mask.
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#define | TC_ABETRG_TIOA 10 |
| TIOA used as an external trigger.
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#define | TC_LDRA_MASK 0x00030000 |
| RA loading selection mask.
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#define | TC_LDRA_RISING_EDGE 0x00010000 |
| Load RA on rising edge of TIOA.
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#define | TC_LDRA_FALLING_EDGE 0x00020000 |
| Load RA on falling edge of TIOA.
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#define | TC_LDRA_BOTH_EDGE 0x00030000 |
| Load RA on any edge of TIOA.
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#define | TC_LDRB_MASK 0x000C0000 |
| RB loading selection mask.
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#define | TC_LDRB_RISING_EDGE 0x00040000 |
| Load RB on rising edge of TIOA.
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#define | TC_LDRB_FALLING_EDGE 0x00080000 |
| Load RB on falling edge of TIOA.
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#define | TC_LDRB_BOTH_EDGE 0x000C0000 |
| Load RB on any edge of TIOA.
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#define | TC_CPCSTOP 6 |
| Waveform Mode.
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#define | TC_CPCDIS 7 |
| Counter clock disabled on RC compare.
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#define | TC_EEVTEDG_MASK 0x00000300 |
| External event edge selection mask.
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#define | TC_EEVTEDG_RISING_EDGE 0x00000100 |
| External event on rising edge..
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#define | TC_EEVTEDG_FALLING_EDGE 0x00000200 |
| External event on falling edge..
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#define | TC_EEVTEDG_BOTH_EDGE 0x00000300 |
| External event on any edge..
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#define | TC_EEVT_MASK 0x00000C00 |
| External event selection mask.
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#define | TC_EEVT_TIOB 0x00000000 |
| TIOB selected as external event.
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#define | TC_EEVT_XC0 0x00000400 |
| XC0 selected as external event.
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#define | TC_EEVT_XC1 0x00000800 |
| XC1 selected as external event.
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#define | TC_EEVT_XC2 0x00000C00 |
| XC2 selected as external event.
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#define | TC_ENETRG 12 |
| External event trigger enable.
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#define | TC_WAVSEL_MASK 0x00006000 |
| Waveform selection mask.
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#define | TC_WAVSEL_UP 0x00000000 |
| UP mode whitout automatic trigger on RC compare.
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#define | TC_WAVSEL_UP_RC_TRG 0x00004000 |
| UP mode whit automatic trigger on RC compare.
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#define | TC_WAVSEL_UPDOWN 0x00002000 |
| UPDOWN mode whitout automatic trigger on RC compare.
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#define | TC_WAVSEL_UPDOWN_RC_TRG 0x00003000 |
| UPDOWN mode whit automatic trigger on RC compare.
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#define | TC_ACPA_MASK 0x00030000 |
| Masks RA compare effect on TIOA.
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#define | TC_ACPA_SET_OUTPUT 0x00010000 |
| RA compare sets TIOA.
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#define | TC_ACPA_CLEAR_OUTPUT 0x00020000 |
| RA compare clears TIOA.
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#define | TC_ACPA_TOGGLE_OUTPUT 0x00030000 |
| RA compare toggles TIOA.
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#define | TC_ACPC_MASK 0x000C0000 |
| Masks RC compare effect on TIOA.
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#define | TC_ACPC_SET_OUTPUT 0x00040000 |
| RC compare sets TIOA.
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#define | TC_ACPC_CLEAR_OUTPUT 0x00080000 |
| RC compare clears TIOA.
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#define | TC_ACPC_TOGGLE_OUTPUT 0x000C0000 |
| RC compare toggles TIOA.
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#define | TC_AEEVT_MASK 0x00300000 |
| Masks external event effect on TIOA.
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#define | TC_AEEVT_SET_OUTPUT 0x00100000 |
| External event sets TIOA.
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#define | TC_AEEVT_CLEAR_OUTPUT 0x00200000 |
| External event clears TIOA.
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#define | TC_AEEVT_TOGGLE_OUTPUT 0x00300000 |
| External event toggles TIOA.
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#define | TC_ASWTRG_MASK 0x00C00000 |
| Masks software trigger effect on TIOA.
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#define | TC_ASWTRG_SET_OUTPUT 0x00400000 |
| Software trigger sets TIOA.
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#define | TC_ASWTRG_CLEAR_OUTPUT 0x00800000 |
| Software trigger clears TIOA.
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#define | TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000 |
| Software trigger toggles TIOA.
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#define | TC_BCPB_MASK 0x03000000 |
| Masks RB compare effect on TIOB.
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#define | TC_BCPB_SET_OUTPUT 0x01000000 |
| RB compare sets TIOB.
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#define | TC_BCPB_CLEAR_OUTPUT 0x02000000 |
| RB compare clears TIOB.
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#define | TC_BCPB_TOGGLE_OUTPUT 0x03000000 |
| RB compare toggles TIOB.
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#define | TC_BCPC_MASK 0x0C000000 |
| Masks RC compare effect on TIOB.
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#define | TC_BCPC_SET_OUTPUT 0x04000000 |
| RC compare sets TIOB.
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#define | TC_BCPC_CLEAR_OUTPUT 0x08000000 |
| RC compare clears TIOB.
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#define | TC_BCPC_TOGGLE_OUTPUT 0x0C000000 |
| RC compare toggles TIOB.
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#define | TC_BEEVT_MASK 0x30000000 |
| Masks external event effect on TIOB.
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#define | TC_BEEVT_SET_OUTPUT 0x10000000 |
| External event sets TIOB.
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#define | TC_BEEVT_CLEAR_OUTPUT 0x20000000 |
| External event clears TIOB.
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#define | TC_BEEVT_TOGGLE_OUTPUT 0x30000000 |
| External event toggles TIOB.
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#define | TC_BSWTRG_MASK 0xC0000000 |
| Masks software trigger effect on TIOB.
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#define | TC_BSWTRG_SET_OUTPUT 0x40000000 |
| Software trigger sets TIOB.
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#define | TC_BSWTRG_CLEAR_OUTPUT 0x80000000 |
| Software trigger clears TIOB.
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#define | TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000 |
| Software trigger toggles TIOB.
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#define | TC_CV_OFF 0x00000010 |
| Counter Value Register.
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#define | TC0_CV (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CV_OFF))) |
| Counter 0 value.
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#define | TC1_CV (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CV_OFF))) |
| Counter 1 value.
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#define | TC2_CV (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CV_OFF))) |
| Counter 2 value.
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#define | TC_RA_OFF 0x00000014 |
| Timer Counter Register A.
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#define | TC0_RA (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RA_OFF))) |
| Channel 0 register A.
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#define | TC1_RA (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RA_OFF))) |
| Channel 1 register A.
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#define | TC2_RA (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RA_OFF))) |
| Channel 2 register A.
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#define | TC_RB_OFF 0x00000018 |
| Timer Counter Register B.
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#define | TC0_RB (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RB_OFF))) |
| Channel 0 register B.
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#define | TC1_RB (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RB_OFF))) |
| Channel 1 register B.
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#define | TC2_RB (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RB_OFF))) |
| Channel 2 register B.
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#define | TC_RC_OFF 0x0000001C |
| Timer Counter Register C.
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#define | TC0_RC (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RC_OFF))) |
| Channel 0 register C.
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#define | TC1_RC (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RC_OFF))) |
| Channel 1 register C.
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#define | TC2_RC (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RC_OFF))) |
| Channel 2 register C.
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#define | TC_SR_OFF 0x00000020 |
| Timer Counter Status and Interrupt Registers.
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#define | TC0_SR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) |
| Status register address.
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#define | TC1_SR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) |
| Status register address.
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#define | TC2_SR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) |
| Status register address.
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#define | TC_IER_OFF 0x00000024 |
| Interrupt Enable Register offset.
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#define | TC0_IER (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IER_OFF))) |
| Channel 0 interrupt enable register address.
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#define | TC1_IER (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IER_OFF))) |
| Channel 1 interrupt enable register address.
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#define | TC2_IER (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IER_OFF))) |
| Channel 2 interrupt enable register address.
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#define | TC_IDR_OFF 0x00000028 |
| Interrupt Disable Register offset.
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#define | TC0_IDR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IDR_OFF))) |
| Channel 0 interrupt disable register address.
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#define | TC1_IDR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IDR_OFF))) |
| Channel 1 interrupt disable register address.
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#define | TC2_IDR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) |
| Channel 2 interrupt disable register address.
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#define | TC_IMR_OFF 0x0000002C |
| Interrupt Mask Register offset.
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#define | TC0_IMR (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) |
| Channel 0 interrupt mask register address.
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#define | TC1_IMR (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) |
| Channel 1 interrupt mask register address.
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#define | TC2_IMR (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) |
| Channel 2 interrupt mask register address.
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#define | TC_COVFS 0 |
| Counter overflow flag.
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#define | TC_LOVRS 1 |
| Load overrun flag.
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#define | TC_CPAS 2 |
| RA compare flag.
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#define | TC_CPBS 3 |
| RB compare flag.
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#define | TC_CPCS 4 |
| RC compare flag.
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#define | TC_LDRAS 5 |
| RA loading flag.
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#define | TC_LDRBS 6 |
| RB loading flag.
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#define | TC_ETRGS 7 |
| External trigger flag.
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#define | TC_CLKSTA 16 |
| Clock enable flag.
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#define | TC_MTIOA 17 |
| TIOA flag.
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#define | TC_MTIOB 18 |
| TIOB flag.
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#define | TC_BCR_OFF 0x000000C0 |
| Timer Counter Block Control Register.
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#define | TC_BCR (*((reg32_t *)(TC_BASE + TC_BCR_OFF))) |
| Block control register address.
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#define | TC_SYNC 0 |
| Synchronisation trigger.
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#define | TC_BMR_OFF 0x000000C4 |
| Timer Counter Block Mode Register.
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#define | TC_BMR (*((reg32_t *)(TC_BASE + TC_BMR_OFF))) |
| Block mode register address.
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#define | TC_TC0XC0S 0x00000003 |
| External clock signal 0 selection mask.
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#define | TC_TCLK0XC0 0x00000000 |
| Selects TCLK0.
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#define | TC_NONEXC0 0x00000001 |
| None selected.
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#define | TC_TIOA1XC0 0x00000002 |
| Selects TIOA1.
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#define | TC_TIOA2XC0 0x00000003 |
| Selects TIOA2.
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#define | TC_TC1XC1S 0x0000000C |
| External clock signal 1 selection mask.
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#define | TC_TCLK1XC1 0x00000000 |
| Selects TCLK1.
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#define | TC_NONEXC1 0x00000004 |
| None selected.
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#define | TC_TIOA0XC1 0x00000008 |
| Selects TIOA0.
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#define | TC_TIOA2XC1 0x0000000C |
| Selects TIOA2.
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#define | TC_TC2XC2S 0x00000030 |
| External clock signal 2 selection mask.
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#define | TC_TCLK2XC2 0x00000000 |
| Selects TCLK2.
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#define | TC_NONEXC2 0x00000010 |
| None selected.
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#define | TC_TIOA0XC2 0x00000020 |
| Selects TIOA0.
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#define | TC_TIOA1XC2 0x00000030 |
| Selects TIOA1.
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