BeRTOS
Defines
at91_adc.h File Reference

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Defines

#define ADC_CR_OFF   0x00000000
 ADC control register.
#define ADC_CR   (*((reg32_t *)(ADC_BASE + ADC_CR_OFF)))
 Control register address.
#define ADC_SWRST   0
 Software reset.
#define ADC_START   1
 Start conversion.
#define ADC_MR_OFF   0x00000004
 ADC mode register.
#define ADC_MR   (*((reg32_t *)(ADC_BASE + ADC_MR_OFF)))
 Mode register address.
#define ADC_TRGEN   0
 Trigger enable.
#define ADC_TRGSEL_TIOA0   0x00000000
 TIOA output of the timer counter channel 0.
#define ADC_TRGSEL_TIOA1   0x00000002
 TIOA output of the timer counter channel 1.
#define ADC_TRGSEL_TIOA2   0x00000004
 TIOA output of the timer counter channel 2.
#define ADC_TRGSEL_EXT   0x0000000C
 External trigger.
#define ADC_LOWRES   4
 Resolution 0: 10-bit, 1: 8-bit.
#define ADC_SLEEP   5
 Sleep mode.
#define ADC_PRESCALER_MASK   0x00003F00
 Prescaler rate selection.
#define ADC_PRESCALER_SHIFT   8
 Prescale rate selection shift.
#define ADC_STARTUP_MASK   0x001F0000
 Start up timer.
#define ADC_STARTUP_SHIFT   16
 Start up timer shift.
#define ADC_SHTIME_MASK   0x0F000000
 Sample & hold time.
#define ADC_SHTIME_SHIFT   24
 Sample & hold time shift.
#define ADC_CHER_OFF   0x00000010
 ADC channel enable register.
#define ADC_CHER   (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF)))
 Channel enable register address.
#define ADC_CHDR_OFF   0x00000014
 ADC channel disable register.
#define ADC_CHDR   (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF)))
 Channel disable register address.
#define ADC_CHSR_OFF   0x00000018
 ADC channel status register.
#define ADC_CHSR   (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF)))
 Channel status register address.
#define ADC_CH_MASK   0x000000FF
 Channel mask.
#define ADC_CH0   0
 Channel 0.
#define ADC_CH1   1
 Channel 1.
#define ADC_CH2   2
 Channel 2.
#define ADC_CH3   3
 Channel 3.
#define ADC_CH4   4
 Channel 4.
#define ADC_CH5   5
 Channel 5.
#define ADC_CH6   6
 Channel 6.
#define ADC_CH7   7
 Channel 7.
#define ADC_SR_OFF   0x0000001C
 ADC status register.
#define ADC_SR   (*((reg32_t *)(ADC_BASE + ADC_SR_OFF)))
 Status register address.
#define ADC_IER_OFF   0x00000024
 ADC Interrupt enable register.
#define ADC_IER   (*((reg32_t *)(ADC_BASE + ADC_IER_OFF)))
 Interrupt enable register.
#define ADC_IDR_OFF   0x00000028
 ADC Interrupt disable register.
#define ADC_IDR   (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF)))
 Interrupt disable register.
#define ADC_IMR_OFF   0x0000002C
 ADC Interrupt mask register.
#define ADC_IMR   (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF)))
 Interrupt mask register.
#define ADC_EOC_MASK   0x000000FF
 End of converison mask.
#define ADC_EOC0   0
 End of conversion channel 0.
#define ADC_EOC1   1
 End of conversion channel 1.
#define ADC_EOC2   2
 End of conversion channel 2.
#define ADC_EOC3   3
 End of conversion channel 3.
#define ADC_EOC4   4
 End of conversion channel 4.
#define ADC_EOC5   5
 End of conversion channel 5.
#define ADC_EOC6   6
 End of conversion channel 6.
#define ADC_EOC7   7
 End of conversion channel 7.
#define ADC_OVRE0   8
 Overrun error channel 0.
#define ADC_OVRE1   9
 Overrun error channel 1.
#define ADC_OVRE2   10
 Overrun error channel 2.
#define ADC_OVRE3   11
 Overrun error channel 3.
#define ADC_OVRE4   12
 Overrun error channel 4.
#define ADC_OVRE5   13
 Overrun error channel 5.
#define ADC_OVRE6   14
 Overrun error channel 6.
#define ADC_OVRE7   15
 Overrun error channel 7.
#define ADC_DRDY   16
 Data ready.
#define ADC_GOVRE   17
 General overrun error.
#define ADC_ENDRX   18
 End of RX buffer.
#define ADC_RXBUFF   19
 Rx buffer full.
#define ADC_LCDR_OFF   0x00000020
 ADC last convert data register.
#define ADC_LCDR   (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF)))
 Last converted data register.
#define ADC_CDR0_OFF   0x00000030
 ADC channel data register.
#define ADC_CDR1_OFF   0x00000034
 Channel data register 1 offeset.
#define ADC_CDR2_OFF   0x00000038
 Channel data register 2 offeset.
#define ADC_CDR3_OFF   0x0000003C
 Channel data register 3 offeset.
#define ADC_CDR4_OFF   0x00000040
 Channel data register 4 offeset.
#define ADC_CDR5_OFF   0x00000044
 Channel data register 5 offeset.
#define ADC_CDR6_OFF   0x00000048
 Channel data register 6 offeset.
#define ADC_CDR7_OFF   0x0000004C
 Channel data register 7 offeset.
#define ADC_CDR0   (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF)))
 Channel data register 0.
#define ADC_CDR1   (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF)))
 Channel data register 1.
#define ADC_CDR2   (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF)))
 Channel data register 2.
#define ADC_CDR3   (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF)))
 Channel data register 3.
#define ADC_CDR4   (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF)))
 Channel data register 4.
#define ADC_CDR5   (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF)))
 Channel data register 5.
#define ADC_CDR6   (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF)))
 Channel data register 6.
#define ADC_CDR7   (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF)))
 Channel data register 7.

Detailed Description

Author:
Daniele Basile <asterix@develer.com>

AT91SAM7 Analog to Digital Converter.

Definition in file at91_adc.h.


Define Documentation

#define ADC_CDR0_OFF   0x00000030

ADC channel data register.

Channel data register 0 offeset.

Definition at line 178 of file at91_adc.h.

#define ADC_CHDR_OFF   0x00000014

ADC channel disable register.

Channel disable register offeset.

Definition at line 100 of file at91_adc.h.

#define ADC_CHER_OFF   0x00000010

ADC channel enable register.

Channel enable register offeset.

Definition at line 94 of file at91_adc.h.

#define ADC_CHSR_OFF   0x00000018

ADC channel status register.

Channel status register offeset.

Definition at line 106 of file at91_adc.h.

#define ADC_CR_OFF   0x00000000

ADC control register.

Control register offeset.

Definition at line 47 of file at91_adc.h.

#define ADC_IDR_OFF   0x00000028

ADC Interrupt disable register.

Interrupt disable register offeset.

Definition at line 134 of file at91_adc.h.

#define ADC_IER_OFF   0x00000024

ADC Interrupt enable register.

Interrupt enable register offeset.

Definition at line 128 of file at91_adc.h.

#define ADC_IMR_OFF   0x0000002C

ADC Interrupt mask register.

Interrupt mask register offeset.

Definition at line 140 of file at91_adc.h.

#define ADC_LCDR_OFF   0x00000020

ADC last convert data register.

Last converted data register offeset.

Definition at line 170 of file at91_adc.h.

#define ADC_MR_OFF   0x00000004

ADC mode register.

Mode register offeset.

Definition at line 56 of file at91_adc.h.

#define ADC_PRESCALER_MASK   0x00003F00

Prescaler rate selection.

ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2) Prescaler rate selection mask.

Definition at line 72 of file at91_adc.h.

#define ADC_SHTIME_MASK   0x0F000000

Sample & hold time.

Sample & hold time = (ADC_SHTIM_VALUE + 1) * 8 /ADCClock Sample & hold time mask.

Definition at line 87 of file at91_adc.h.

#define ADC_SR_OFF   0x0000001C

ADC status register.

Status register offeset.

Definition at line 122 of file at91_adc.h.

#define ADC_STARTUP_MASK   0x001F0000

Start up timer.

Startup time = (ADC_STARTUP_VALUE + 1) * 8 /ADCClock Start up timer mask.

Definition at line 79 of file at91_adc.h.