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Defines | Functions
sam3_pmc.h File Reference

SAM3 PMC hardware. More...

#include <cfg/macros.h>
#include <cfg/debug.h>

Go to the source code of this file.

Defines

#define PMC_BASE   0x400E0400
 PMC registers base.
#define PMC_SCER_OFF   0x00
 PMC register offsets.
#define PMC_SCDR_OFF   0x04
 System Clock Disable Register.
#define PMC_SCSR_OFF   0x08
 System Clock Status Register.
#define PMC_MOR_OFF   0x20
 Main Oscillator Register.
#define PMC_MCFR_OFF   0x24
 Main Clock Frequency Register.
#define PMC_MCKR_OFF   0x30
 Master Clock Register.
#define PMC_IER_OFF   0x60
 Interrupt Enable Register.
#define PMC_IDR_OFF   0x64
 Interrupt Disable Register.
#define PMC_SR_OFF   0x68
 Status Register.
#define PMC_IMR_OFF   0x6C
 Interrupt Mask Register.
#define PMC_FSMR_OFF   0x70
 Fast Startup Mode Register.
#define PMC_FSPR_OFF   0x74
 Fast Startup Polarity Register.
#define PMC_FOCR_OFF   0x78
 Fault Output Clear Register.
#define PMC_WPMR_OFF   0xE4
 Write Protect Mode Register.
#define PMC_WPSR_OFF   0xE8
 Write Protect Status Register.
#define PMC_SCER   (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))
 PMC registers.
#define PMC_SCDR   (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF)))
 System Clock Disable Register.
#define PMC_SCSR   (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF)))
 System Clock Status Register.
#define CKGR_MOR   (*((reg32_t *)(PMC_BASE + PMC_MOR_OFF )))
 Main Oscillator Register.
#define CKGR_MCFR   (*((reg32_t *)(PMC_BASE + PMC_MCFR_OFF)))
 Main Clock Frequency Register.
#define PMC_MCKR   (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF)))
 Master Clock Register.
#define PMC_IER   (*((reg32_t *)(PMC_BASE + PMC_IER_OFF )))
 Interrupt Enable Register.
#define PMC_IDR   (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF )))
 Interrupt Disable Register.
#define PMC_SR   (*((reg32_t *)(PMC_BASE + PMC_SR_OFF )))
 Status Register.
#define PMC_IMR   (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF )))
 Interrupt Mask Register.
#define PMC_FSMR   (*((reg32_t *)(PMC_BASE + PMC_FSMR_OFF)))
 Fast Startup Mode Register.
#define PMC_FSPR   (*((reg32_t *)(PMC_BASE + PMC_FSPR_OFF)))
 Fast Startup Polarity Register.
#define PMC_FOCR   (*((reg32_t *)(PMC_BASE + PMC_FOCR_OFF)))
 Fault Output Clear Register.
#define PMC_WPMR   (*((reg32_t *)(PMC_BASE + PMC_WPMR_OFF)))
 Write Protect Mode Register.
#define PMC_WPSR   (*((reg32_t *)(PMC_BASE + PMC_WPSR_OFF)))
 Write Protect Status Register.
#define PMC_SCER_PCK0   8
 Defines for bit fields in PMC_SCER register.
#define PMC_SCER_PCK1   9
 Programmable Clock 1 Output Enable.
#define PMC_SCER_PCK2   10
 Programmable Clock 2 Output Enable.
#define PMC_SCDR_PCK0   8
 Defines for bit fields in PMC_SCDR register.
#define PMC_SCDR_PCK1   9
 Programmable Clock 1 Output Disable.
#define PMC_SCDR_PCK2   10
 Programmable Clock 2 Output Disable.
#define PMC_SCSR_PCK0   8
 Defines for bit fields in PMC_SCSR register.
#define PMC_SCSR_PCK1   9
 Programmable Clock 1 Output Status.
#define PMC_SCSR_PCK2   10
 Programmable Clock 2 Output Status.
#define CKGR_MOR_MOSCXTEN   0
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCXTBY   1
 Main Crystal Oscillator Bypass.
#define CKGR_MOR_WAITMODE   2
 Wait Mode Command.
#define CKGR_MOR_MOSCRCEN   3
 Main On-Chip RC Oscillator Enable.
#define CKGR_MOR_MOSCRCF_SHIFT   4
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCRCF_MASK   (0x7 << CKGR_MOR_MOSCRCF_SHIFT)
 Main On-Chip RC Oscillator Frequency Selection.
#define CKGR_MOR_MOSCRCF(value)   ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCRCF_4MHZ   (0x0 << CKGR_MOR_MOSCRCF_SHIFT)
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCRCF_8MHZ   (0x1 << CKGR_MOR_MOSCRCF_SHIFT)
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCRCF_12MHZ   (0x2 << CKGR_MOR_MOSCRCF_SHIFT)
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCXTST_SHIFT   8
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCXTST_MASK   (0xff << CKGR_MOR_MOSCXTST_SHIFT)
 Main Crystal Oscillator Start-up Time.
#define CKGR_MOR_MOSCXTST(value)   ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_KEY_SHIFT   16
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_KEY_MASK   (0xffu << CKGR_MOR_KEY_SHIFT)
 Password.
#define CKGR_MOR_KEY(value)   ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))
 Defines for bit fields in CKGR_MOR register.
#define CKGR_MOR_MOSCSEL   24
 Main Oscillator Selection.
#define CKGR_MOR_CFDEN   25
 Clock Failure Detector Enable.
#define CKGR_MCFR_MAINF_MASK   0xffff
 Defines for bit fields in CKGR_MCFR register.
#define CKGR_MCFR_MAINFRDY   16
 Main Clock Ready.
#define CKGR_PLLR_DIV_MASK   0xff
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_DIV(value)   (CKGR_PLLR_DIV_MASK & (value))
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_PLLCOUNT_SHIFT   8
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_PLLCOUNT_MASK   (0x3f << CKGR_PLLR_PLLCOUNT_SHIFT)
 PLL Counter mask.
#define CKGR_PLLR_PLLCOUNT(value)   (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_MUL_SHIFT   16
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_MUL_MASK   (0x7ff << CKGR_PLLR_MUL_SHIFT)
 PLL Multiplier mask.
#define CKGR_PLLR_MUL(value)   (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))
 Defines for bit fields in CKGR_PLLR register.
#define CKGR_PLLR_STUCKTO1   29
 Defines for bit fields in CKGR_PLLR register.
#define PMC_MCKR_CSS_MASK   0x3
 Defines for bit fields in PMC_MCKR register.
#define PMC_MCKR_CSS_SLOW_CLK   0x0
 Slow Clock is selected.
#define PMC_MCKR_CSS_MAIN_CLK   0x1
 Main Clock is selected.
#define PMC_MCKR_CSS_PLL_CLK   0x2
 PLL Clock is selected.
#define PMC_MCKR_PRES_SHIFT   4
 Defines for bit fields in PMC_MCKR register.
#define PMC_MCKR_PRES_MASK   (0x7 << PMC_MCKR_PRES_SHIFT)
 Processor Clock Prescaler mask.
#define PMC_MCKR_PRES_CLK   (0x0 << PMC_MCKR_PRES_SHIFT)
 Selected clock.
#define PMC_MCKR_PRES_CLK_2   (0x1 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 2.
#define PMC_MCKR_PRES_CLK_4   (0x2 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 4.
#define PMC_MCKR_PRES_CLK_8   (0x3 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 8.
#define PMC_MCKR_PRES_CLK_16   (0x4 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 16.
#define PMC_MCKR_PRES_CLK_32   (0x5 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 32.
#define PMC_MCKR_PRES_CLK_64   (0x6 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 64.
#define PMC_MCKR_PRES_CLK_3   (0x7 << PMC_MCKR_PRES_SHIFT)
 Selected clock divided by 3.
#define PMC_MCKR_PLLDIV2   12
 PLL Divisor by 2.
#define PMC_PCK_CSS_MASK   0x7
 Defines for bit fields in PMC_PCK[3] register.
#define PMC_PCK_CSS_SLOW   0x0
 Slow Clock is selected.
#define PMC_PCK_CSS_MAIN   0x1
 Main Clock is selected.
#define PMC_PCK_CSS_PLL   0x2
 PLL Clock is selected.
#define PMC_PCK_CSS_MCK   0x4
 Master Clock is selected.
#define PMC_PCK_PRES_SHIFT   4
 Defines for bit fields in PMC_PCK[3] register.
#define PMC_PCK_PRES_MASK   (0x7 << PMC_PCK_PRES_SHIFT)
 Programmable Clock Prescaler.
#define PMC_PCK_PRES_CLK   (0x0 << PMC_PCK_PRES_SHIFT)
 Selected clock.
#define PMC_PCK_PRES_CLK_2   (0x1 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 2.
#define PMC_PCK_PRES_CLK_4   (0x2 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 4.
#define PMC_PCK_PRES_CLK_8   (0x3 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 8.
#define PMC_PCK_PRES_CLK_16   (0x4 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 16.
#define PMC_PCK_PRES_CLK_32   (0x5 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 32.
#define PMC_PCK_PRES_CLK_64   (0x6 << PMC_PCK_PRES_SHIFT)
 Selected clock divided by 64.
#define PMC_IER_MOSCXTS   0
 Defines for bit fields in PMC_IER register.
#define PMC_IER_LOCK   1
 PLL Lock Interrupt Enable.
#define PMC_IER_MCKRDY   3
 Master Clock Ready Interrupt Enable.
#define PMC_IER_PCKRDY0   8
 Programmable Clock Ready 0 Interrupt Enable.
#define PMC_IER_PCKRDY1   9
 Programmable Clock Ready 1 Interrupt Enable.
#define PMC_IER_PCKRDY2   10
 Programmable Clock Ready 2 Interrupt Enable.
#define PMC_IER_MOSCSELS   16
 Main Oscillator Selection Status Interrupt Enable.
#define PMC_IER_MOSCRCS   17
 Main On-Chip RC Status Interrupt Enable.
#define PMC_IER_CFDEV   18
 Clock Failure Detector Event Interrupt Enable.
#define PMC_IDR_MOSCXTS   0
 Defines for bit fields in PMC_IDR register.
#define PMC_IDR_LOCK   1
 PLL Lock Interrupt Disable.
#define PMC_IDR_MCKRDY   3
 Master Clock Ready Interrupt Disable.
#define PMC_IDR_PCKRDY0   8
 Programmable Clock Ready 0 Interrupt Disable.
#define PMC_IDR_PCKRDY1   9
 Programmable Clock Ready 1 Interrupt Disable.
#define PMC_IDR_PCKRDY2   10
 Programmable Clock Ready 2 Interrupt Disable.
#define PMC_IDR_MOSCSELS   16
 Main Oscillator Selection Status Interrupt Disable.
#define PMC_IDR_MOSCRCS   17
 Main On-Chip RC Status Interrupt Disable.
#define PMC_IDR_CFDEV   18
 Clock Failure Detector Event Interrupt Disable.
#define PMC_SR_MOSCXTS   0
 Defines for bit fields in PMC_SR register.
#define PMC_SR_LOCK   1
 PLL Lock Status.
#define PMC_SR_MCKRDY   3
 Master Clock Status.
#define PMC_SR_OSCSELS   7
 Slow Clock Oscillator Selection.
#define PMC_SR_PCKRDY0   8
 Programmable Clock Ready Status.
#define PMC_SR_PCKRDY1   9
 Programmable Clock Ready Status.
#define PMC_SR_PCKRDY2   10
 Programmable Clock Ready Status.
#define PMC_SR_MOSCSELS   16
 Main Oscillator Selection Status.
#define PMC_SR_MOSCRCS   17
 Main On-Chip RC Oscillator Status.
#define PMC_SR_CFDEV   18
 Clock Failure Detector Event.
#define PMC_SR_CFDS   19
 Clock Failure Detector Status.
#define PMC_SR_FOS   20
 Clock Failure Detector Fault Output Status.
#define PMC_IMR_MOSCXTS   0
 Defines for bit fields in PMC_IMR register.
#define PMC_IMR_LOCK   1
 PLL Lock Interrupt Mask.
#define PMC_IMR_MCKRDY   3
 Master Clock Ready Interrupt Mask.
#define PMC_IMR_PCKRDY0   8
 Programmable Clock Ready 0 Interrupt Mask.
#define PMC_IMR_PCKRDY1   9
 Programmable Clock Ready 1 Interrupt Mask.
#define PMC_IMR_PCKRDY2   10
 Programmable Clock Ready 2 Interrupt Mask.
#define PMC_IMR_MOSCSELS   16
 Main Oscillator Selection Status Interrupt Mask.
#define PMC_IMR_MOSCRCS   17
 Main On-Chip RC Status Interrupt Mask.
#define PMC_IMR_CFDEV   18
 Clock Failure Detector Event Interrupt Mask.
#define PMC_FSMR_FSTT0   0
 Defines for bit fields in PMC_FSMR register.
#define PMC_FSMR_FSTT1   1
 Fast Startup Input Enable 1.
#define PMC_FSMR_FSTT2   2
 Fast Startup Input Enable 2.
#define PMC_FSMR_FSTT3   3
 Fast Startup Input Enable 3.
#define PMC_FSMR_FSTT4   4
 Fast Startup Input Enable 4.
#define PMC_FSMR_FSTT5   5
 Fast Startup Input Enable 5.
#define PMC_FSMR_FSTT6   6
 Fast Startup Input Enable 6.
#define PMC_FSMR_FSTT7   7
 Fast Startup Input Enable 7.
#define PMC_FSMR_FSTT8   8
 Fast Startup Input Enable 8.
#define PMC_FSMR_FSTT9   9
 Fast Startup Input Enable 9.
#define PMC_FSMR_FSTT10   10
 Fast Startup Input Enable 10.
#define PMC_FSMR_FSTT11   11
 Fast Startup Input Enable 11.
#define PMC_FSMR_FSTT12   12
 Fast Startup Input Enable 12.
#define PMC_FSMR_FSTT13   13
 Fast Startup Input Enable 13.
#define PMC_FSMR_FSTT14   14
 Fast Startup Input Enable 14.
#define PMC_FSMR_FSTT15   15
 Fast Startup Input Enable 15.
#define PMC_FSMR_RTTAL   16
 RTT Alarm Enable.
#define PMC_FSMR_RTCAL   17
 RTC Alarm Enable.
#define PMC_FSMR_LPM   20
 Low Power Mode.
#define PMC_FSPR_FSTP0   0
 Defines for bit fields in PMC_FSPR register.
#define PMC_FSPR_FSTP1   1
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP2   2
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP3   3
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP4   4
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP5   5
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP6   6
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP7   7
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP8   8
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP9   9
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP10   10
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP11   11
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP12   12
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP13   13
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP14   14
 Fast Startup Input Polarityx.
#define PMC_FSPR_FSTP15   15
 Fast Startup Input Polarityx.
#define PMC_FOCR_FOCLR   0
 Defines for bit fields in PMC_FOCR register.
#define PMC_WPMR_WPEN   0
 Defines for bit fields in PMC_WPMR register.
#define PMC_WPMR_WPKEY_SHIFT   8
 Defines for bit fields in PMC_WPMR register.
#define PMC_WPMR_WPKEY_MASK   (0xffffff << PMC_WPMR_WPKEY_SHIFT)
 Write Protect key mask.
#define PMC_WPMR_WPKEY(value)   ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))
 Defines for bit fields in PMC_WPMR register.
#define PMC_WPSR_WPVS   0
 Defines for bit fields in PMC_WPSR register.
#define PMC_WPSR_WPVSRC_SHIFT   8
 Defines for bit fields in PMC_WPSR register.
#define PMC_WPSR_WPVSRC_MASK   (0xffff << PMC_WPSR_WPVSRC_SHIFT)
 Write Protect Violation Source mask.
#define PMC_OCR_CAL4_MASK   0x7f
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_CAL4(value)   (PMC_OCR_CAL4_MASK & (value))
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_SEL4   7
 Selection of RC Oscillator Calibration bits for 4 MHz.
#define PMC_OCR_CAL8_SHIFT   8
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_CAL8_MASK   (0x7f << PMC_OCR_CAL8_SHIFT)
 RC Oscillator Calibration bits for 8 MHz mask.
#define PMC_OCR_CAL8(value)   ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_SEL8   15
 Selection of RC Oscillator Calibration bits for 8 MHz.
#define PMC_OCR_CAL12_SHIFT   16
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_CAL12_MASK   (0x7f << PMC_OCR_CAL12_SHIFT)
 RC Oscillator Calibration bits for 12 MHz mask.
#define PMC_OCR_CAL12(value)   ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))
 Defines for bit fields in PMC_OCR register.
#define PMC_OCR_SEL12   23
 Selection of RC Oscillator Calibration bits for 12 MHz.

Functions

void pmc_periphEnable (unsigned id)
 Enable a peripheral clock.
void pmc_periphDisable (unsigned id)
 Disable a peripheral clock.

Detailed Description

SAM3 PMC hardware.

Definition in file sam3_pmc.h.


Define Documentation

#define CKGR_MCFR_MAINF_MASK   0xffff

Defines for bit fields in CKGR_MCFR register.

Main Clock Frequency mask

Definition at line 251 of file sam3_pmc.h.

#define CKGR_MOR_KEY (   value)    ((CKGR_MOR_KEY_MASK & ((value) << CKGR_MOR_KEY_SHIFT)))

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 242 of file sam3_pmc.h.

#define CKGR_MOR_KEY_SHIFT   16

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 240 of file sam3_pmc.h.

#define CKGR_MOR_MOSCRCF (   value)    ((CKGR_MOR_MOSCRCF_MASK & ((value) << CKGR_MOR_MOSCRCF_SHIFT)))

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 233 of file sam3_pmc.h.

#define CKGR_MOR_MOSCRCF_12MHZ   (0x2 << CKGR_MOR_MOSCRCF_SHIFT)

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 236 of file sam3_pmc.h.

#define CKGR_MOR_MOSCRCF_4MHZ   (0x0 << CKGR_MOR_MOSCRCF_SHIFT)

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 234 of file sam3_pmc.h.

#define CKGR_MOR_MOSCRCF_8MHZ   (0x1 << CKGR_MOR_MOSCRCF_SHIFT)

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 235 of file sam3_pmc.h.

#define CKGR_MOR_MOSCRCF_SHIFT   4

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 231 of file sam3_pmc.h.

#define CKGR_MOR_MOSCXTEN   0

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 227 of file sam3_pmc.h.

#define CKGR_MOR_MOSCXTST (   value)    ((CKGR_MOR_MOSCXTST_MASK & ((value) << CKGR_MOR_MOSCXTST_SHIFT)))

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 239 of file sam3_pmc.h.

#define CKGR_MOR_MOSCXTST_SHIFT   8

Defines for bit fields in CKGR_MOR register.

Main Crystal Oscillator Enable

Definition at line 237 of file sam3_pmc.h.

#define CKGR_PLLR_DIV (   value)    (CKGR_PLLR_DIV_MASK & (value))

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 260 of file sam3_pmc.h.

#define CKGR_PLLR_DIV_MASK   0xff

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 259 of file sam3_pmc.h.

#define CKGR_PLLR_MUL (   value)    (CKGR_PLLR_MUL_MASK & ((value) << CKGR_PLLR_MUL_SHIFT))

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 266 of file sam3_pmc.h.

#define CKGR_PLLR_MUL_SHIFT   16

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 264 of file sam3_pmc.h.

#define CKGR_PLLR_PLLCOUNT (   value)    (CKGR_PLLR_PLLCOUNT_MASK & ((value) << CKGR_PLLR_PLLCOUNT_SHIFT))

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 263 of file sam3_pmc.h.

#define CKGR_PLLR_PLLCOUNT_SHIFT   8

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 261 of file sam3_pmc.h.

#define CKGR_PLLR_STUCKTO1   29

Defines for bit fields in CKGR_PLLR register.

Divider mask

Definition at line 267 of file sam3_pmc.h.

#define PMC_BASE   0x400E0400

PMC registers base.

Definition at line 47 of file sam3_pmc.h.

#define PMC_FOCR_FOCLR   0

Defines for bit fields in PMC_FOCR register.

Fault Output Clear

Definition at line 425 of file sam3_pmc.h.

#define PMC_FSMR_FSTT0   0

Defines for bit fields in PMC_FSMR register.

Fast Startup Input Enable 0

Definition at line 378 of file sam3_pmc.h.

#define PMC_FSPR_FSTP0   0

Defines for bit fields in PMC_FSPR register.

Fast Startup Input Polarityx

Definition at line 403 of file sam3_pmc.h.

#define PMC_IDR_MOSCXTS   0

Defines for bit fields in PMC_IDR register.

Main Crystal Oscillator Status Interrupt Disable

Definition at line 330 of file sam3_pmc.h.

#define PMC_IER_MOSCXTS   0

Defines for bit fields in PMC_IER register.

Main Crystal Oscillator Status Interrupt Enable

Definition at line 315 of file sam3_pmc.h.

#define PMC_IMR_MOSCXTS   0

Defines for bit fields in PMC_IMR register.

Main Crystal Oscillator Status Interrupt Mask

Definition at line 363 of file sam3_pmc.h.

#define PMC_MCKR_CSS_MASK   0x3

Defines for bit fields in PMC_MCKR register.

Master Clock Source Selection mask

Definition at line 274 of file sam3_pmc.h.

#define PMC_MCKR_PRES_SHIFT   4

Defines for bit fields in PMC_MCKR register.

Master Clock Source Selection mask

Definition at line 278 of file sam3_pmc.h.

#define PMC_OCR_CAL12 (   value)    ((PMC_OCR_CAL12_MASK & ((value) << PMC_OCR_CAL12_SHIFT)))

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 460 of file sam3_pmc.h.

#define PMC_OCR_CAL12_SHIFT   16

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 458 of file sam3_pmc.h.

#define PMC_OCR_CAL4 (   value)    (PMC_OCR_CAL4_MASK & (value))

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 452 of file sam3_pmc.h.

#define PMC_OCR_CAL4_MASK   0x7f

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 451 of file sam3_pmc.h.

#define PMC_OCR_CAL8 (   value)    ((PMC_OCR_CAL8_MASK & ((value) << PMC_OCR_CAL8_SHIFT)))

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 456 of file sam3_pmc.h.

#define PMC_OCR_CAL8_SHIFT   8

Defines for bit fields in PMC_OCR register.

RC Oscillator Calibration bits for 4 MHz mask

Definition at line 454 of file sam3_pmc.h.

#define PMC_PCK_CSS_MASK   0x7

Defines for bit fields in PMC_PCK[3] register.

Master Clock Source Selection mask

Definition at line 295 of file sam3_pmc.h.

#define PMC_PCK_PRES_SHIFT   4

Defines for bit fields in PMC_PCK[3] register.

Master Clock Source Selection mask

Definition at line 300 of file sam3_pmc.h.

#define PMC_SCDR_PCK0   8

Defines for bit fields in PMC_SCDR register.

Programmable Clock 0 Output Disable

Definition at line 209 of file sam3_pmc.h.

#define PMC_SCER   (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))

PMC registers.

System Clock Enable Register

Definition at line 102 of file sam3_pmc.h.

#define PMC_SCER_OFF   0x00

PMC register offsets.

System Clock Enable Register

Definition at line 54 of file sam3_pmc.h.

#define PMC_SCER_PCK0   8

Defines for bit fields in PMC_SCER register.

Programmable Clock 0 Output Enable

Definition at line 200 of file sam3_pmc.h.

#define PMC_SCSR_PCK0   8

Defines for bit fields in PMC_SCSR register.

Programmable Clock 0 Output Status

Definition at line 218 of file sam3_pmc.h.

#define PMC_SR_MOSCXTS   0

Defines for bit fields in PMC_SR register.

Main XTAL Oscillator Status

Definition at line 345 of file sam3_pmc.h.

#define PMC_WPMR_WPEN   0

Defines for bit fields in PMC_WPMR register.

Write Protect Enable

Definition at line 432 of file sam3_pmc.h.

#define PMC_WPMR_WPKEY (   value)    ((PMC_WPMR_WPKEY_MASK & ((value) << PMC_WPMR_WPKEY_SHIFT)))

Defines for bit fields in PMC_WPMR register.

Write Protect Enable

Definition at line 435 of file sam3_pmc.h.

#define PMC_WPMR_WPKEY_SHIFT   8

Defines for bit fields in PMC_WPMR register.

Write Protect Enable

Definition at line 433 of file sam3_pmc.h.

#define PMC_WPSR_WPVS   0

Defines for bit fields in PMC_WPSR register.

Write Protect Violation Status

Definition at line 442 of file sam3_pmc.h.

#define PMC_WPSR_WPVSRC_SHIFT   8

Defines for bit fields in PMC_WPSR register.

Write Protect Violation Status

Definition at line 443 of file sam3_pmc.h.


Function Documentation

void pmc_periphDisable ( unsigned  id) [inline]

Disable a peripheral clock.

Parameters:
idperipheral id of the peripheral whose clock is enabled

Definition at line 188 of file sam3_pmc.h.

void pmc_periphEnable ( unsigned  id) [inline]

Enable a peripheral clock.

Parameters:
idperipheral id of the peripheral whose clock is enabled

Definition at line 162 of file sam3_pmc.h.