BeRTOS
at91_emac.h
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00001 
00039 /*
00040  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00041  *
00042  * Redistribution and use in source and binary forms, with or without
00043  * modification, are permitted provided that the following conditions
00044  * are met:
00045  *
00046  * 1. Redistributions of source code must retain the above copyright
00047  *    notice, this list of conditions and the following disclaimer.
00048  * 2. Redistributions in binary form must reproduce the above copyright
00049  *    notice, this list of conditions and the following disclaimer in the
00050  *    documentation and/or other materials provided with the distribution.
00051  * 3. Neither the name of the copyright holders nor the names of
00052  *    contributors may be used to endorse or promote products derived
00053  *    from this software without specific prior written permission.
00054  *
00055  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00056  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00057  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00058  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00059  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00060  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00061  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00062  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00063  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00064  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00065  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00066  * SUCH DAMAGE.
00067  *
00068  * For additional information see http://www.ethernut.de/
00069  */
00070 
00071 #ifndef AT91_EMAC_H
00072 #define AT91_EMAC_H
00073 
00074 
00080 /* \{ */
00081 #define EMAC_NCR_OFF                0x00000000  ///< Network control register offset.
00082 #define EMAC_NCR    (*((reg32_t *)(EMAC_BASE +  EMAC_NCR_OFF)))  ///< Network Control register address.
00083 #define EMAC_LB                              0  ///< PHY loopback.
00084 #define EMAC_LLB                             1   ///< EMAC loopback.
00085 #define EMAC_RE                              2  ///< Receive enable.
00086 #define EMAC_TE                              3  ///< Transmit enable.
00087 #define EMAC_MPE                             4  ///< Management port enable.
00088 #define EMAC_CLRSTAT                         5  ///< Clear statistics registers.
00089 #define EMAC_INCSTAT                         6  ///< Increment statistics registers.
00090 #define EMAC_WESTAT                          7  ///< Write enable for statistics registers.
00091 #define EMAC_BP                              8  ///< Back pressure.
00092 #define EMAC_TSTART                          9  ///< Start Transmission.
00093 #define EMAC_THALT                          10  ///< Transmission halt.
00094 // Not in sam7x
00095 //#define EMAC_TPFR                           11  ///< Transmit pause frame.
00096 //#define EMAC_TZQ                            12  ///< Transmit zero quantum pause frame.
00097 /* \} */
00098 
00103 /* \{ */
00104 #define EMAC_NCFGR_OFF              0x00000004  ///< Network configuration register offset.
00105 #define EMAC_NCFGR   (*((reg32_t *)(EMAC_BASE +  EMAC_NCFGR_OFF))) ///< Network configuration register address.
00106 #define EMAC_SPD                             0  ///< Speed, set for 100Mb.
00107 #define EMAC_FD                              1  ///< Full duplex.
00108 #define EMAC_JFRAME                          3  ///< Jumbo Frames.
00109 #define EMAC_CAF                             4  ///< Copy all frames.
00110 #define EMAC_NBC                             5  ///< No broadcast.
00111 #define EMAC_MTI                             6  ///< Multicast hash event enable.
00112 #define EMAC_UNI                             7  ///< Unicast hash enable.
00113 #define EMAC_BIG                             8  ///< Receive 1522 bytes.
00114 // Not in sam7x
00115 //#define EMAC_EAE                           9  ///< External address match enable.
00116 #define EMAC_CLK                    0x00000C00  ///< Clock divider mask.
00117 #define EMAC_CLK_HCLK_8             0x00000000  ///< HCLK divided by 8.
00118 #define EMAC_CLK_HCLK_16            0x00000400  ///< HCLK divided by 16.
00119 #define EMAC_CLK_HCLK_32            0x00000800  ///< HCLK divided by 32.
00120 #define EMAC_CLK_HCLK_64            0x00000C00  ///< HCLK divided by 64.
00121 #define EMAC_RTY                            12  ///< Retry test.
00122 #define EMAC_PAE                            13  ///< Pause enable.
00123 #define EMAC_RBOF                   0x0000C000  ///< Receive buffer offset.
00124 #define EMAC_RBOF_OFFSET_0          0x00000000  ///< No offset from start of receive buffer.
00125 #define EMAC_RBOF_OFFSET_1          0x00004000  ///< One byte offset from start of receive buffer.
00126 #define EMAC_RBOF_OFFSET_2          0x00008000  ///< Two bytes offset from start of receive buffer.
00127 #define EMAC_RBOF_OFFSET_3          0x0000C000  ///< Three bytes offset from start of receive buffer.
00128 #define EMAC_RLCE                           16  ///< Receive length field checking enable.
00129 #define EMAC_DRFCS                          17  ///< Discard receive FCS.
00130 #define EMAC_EFRHD                          18  ///< Allow receive during transmit in half duplex.
00131 #define EMAC_IRXFCS                         19  ///< Ignore received FCS.
00132 /* \} */
00133 
00138 /* \{ */
00139 #define EMAC_NSR_OFF                0x00000008  ///< Network Status register offset.
00140 #define EMAC_NSR    (*((reg32_t *)(EMAC_BASE +  EMAC_NSR_OFF)))  ///< Network Status register address.
00141 // Not in sam7x
00142 //#define EMAC_LINKR                         0  ///< .
00143 #define EMAC_MDIO                            1  ///< Status of MDIO input pin.
00144 #define EMAC_IDLE                            2  ///< Set when PHY is running.
00145 /* \} */
00146 
00150 /* \{ */
00151 #define EMAC_TSR_OFF                0x00000014  ///< Transmit Status register offset.
00152 #define EMAC_TSR    (*((reg32_t *)(EMAC_BASE +  EMAC_TSR_OFF)))  ///< Transmit Status register address.
00153 
00154 #define EMAC_UBR                             0  ///< Used bit read.
00155 #define EMAC_COL                             1  ///< Collision occurred.
00156 #define EMAC_RLES                            2  ///< Retry limit exceeded.
00157 #define EMAC_TGO                             3  ///< Transmit active.
00158 #define EMAC_BEX                             4  ///< Buffers exhausted mid frame.
00159 #define EMAC_COMP                            5  ///< Transmit complete.
00160 #define EMAC_UND                             6  ///< Transmit underrun.
00161 /* \} */
00162 
00167 /* \{ */
00168 #define EMAC_RBQP_OFF               0x00000018  ///< Receive buffer queue pointer.
00169 #define EMAC_RBQP   (*((reg32_t *)(EMAC_BASE +  EMAC_RBQP_OFF))) ///< Receive buffer queue pointer.
00170 #define EMAC_TBQP_OFF               0x0000001C  ///< Transmit buffer queue pointer.
00171 #define EMAC_TBQP   (*((reg32_t *)(EMAC_BASE +  EMAC_TBQP_OFF))) ///< Transmit buffer queue pointer.
00172 /* \} */
00173 
00177 /* \{ */
00178 #define EMAC_RSR_OFF                0x00000020  ///< Receive status register offset.
00179 #define EMAC_RSR    (*((reg32_t *)(EMAC_BASE +  EMAC_RSR_OFF)))  ///< Receive status register address.
00180 #define EMAC_BNA                             0  ///< Buffer not available.
00181 #define EMAC_REC                             1  ///< Frame received.
00182 #define EMAC_OVR                             2  ///< Receive overrun.
00183 /* \} */
00184 
00186 /* \{ */
00187 #define EMAC_ISR_OFF                0x00000024  ///< Status register offset.
00188 #define EMAC_ISR    (*((reg32_t *)(EMAC_BASE +  EMAC_ISR_OFF)))  ///< Status register address.
00189 #define EMAC_IER_OFF                0x00000028  ///< Enable register offset.
00190 #define EMAC_IER    (*((reg32_t *)(EMAC_BASE +  EMAC_IER_OFF)))  ///< Enable register address.
00191 #define EMAC_IDR_OFF                0x0000002C  ///< Disable register offset.
00192 #define EMAC_IDR    (*((reg32_t *)(EMAC_BASE +  EMAC_IDR_OFF)))  ///< Disable register address.
00193 #define EMAC_IMR_OFF                0x00000030  ///< Mask register offset.
00194 #define EMAC_IMR    (*((reg32_t *)(EMAC_BASE +  EMAC_IMR_OFF)))  ///< Mask register address.
00195 
00196 #define EMAC_MFD                             0  ///< Management frame done.
00197 #define EMAC_RCOMP                           1  ///< Receive complete.
00198 #define EMAC_RXUBR                           2  ///< Receive used bit read.
00199 #define EMAC_TXUBR                           3  ///< Transmit used bit read.
00200 #define EMAC_TUND                            4  ///< Ethernet transmit buffer underrun.
00201 #define EMAC_RLEX                            5  ///< Retry limit exceeded.
00202 #define EMAC_TXERR                           6  ///< Transmit error.
00203 #define EMAC_TCOMP                           7  ///< Transmit complete.
00204 //Not in sam7x
00205 //#define EMAC_LINK                          8  ///< .
00206 #define EMAC_ROVR                           10  ///< Receive overrun.
00207 #define EMAC_HRESP                          11  ///< DMA bus error.
00208 #define EMAC_PFR                            12  ///< Pause frame received.
00209 #define EMAC_PTZ                            13  ///< Pause time zero.
00210 /* \} */
00211 
00216 /* \{ */
00217 #define EMAC_MAN_OFF                0x00000034  ///< PHY maintenance register offset.
00218 #define EMAC_MAN    (*((reg32_t *)(EMAC_BASE +  EMAC_MAN_OFF)))  ///< PHY maintenance register address.
00219 #define EMAC_DATA                   0x0000FFFF  ///< PHY data mask.
00220 #define EMAC_CODE                   0x00020000  ///< Fixed value.
00221 #define EMAC_REGA                   0x007C0000  ///< PHY register address mask.
00222 #define EMAC_REGA_SHIFT                     18  ///< PHY register address mask.
00223 #define EMAC_PHYA                   0x0F800000  ///< PHY address mask.
00224 #define EMAC_PHYA_SHIFT                     23  ///< PHY address mask.
00225 #define EMAC_RW                     0x30000000  ///< PHY read/write command mask.
00226 #define EMAC_RW_READ                0x20000000  ///< PHY read command.
00227 #define EMAC_RW_WRITE               0x10000000  ///< PHY write command.
00228 #define EMAC_SOF                    0x40000000  ///< Fixed value.
00229 /* \} */
00230 
00235 /* \{ */
00236 #define EMAC_PTR_OFF                0x00000038  ///< Pause time register offset.
00237 #define EMAC_PTR    (*((reg32_t *)(EMAC_BASE +  EMAC_PTR_OFF)))  ///< Pause time register address.
00238 #define EMAC_PTIME                  0x0000FFFF  ///< Pause time mask.
00239 /* \} */
00240 
00244 /* \{ */
00245 #define EMAC_PFRR_OFF               0x0000003C  ///< Pause frames received register offset.
00246 #define EMAC_PFRR  (*((reg32_t *)(EMAC_BASE +  EMAC_PFRR_OFF)))  ///< Pause frames received register address.
00247 #define EMAC_FTO_OFF                0x00000040  ///< Frames transmitted OK register offset.
00248 #define EMAC_FTO    (*((reg32_t *)(EMAC_BASE +  EMAC_FTO_OFF)))  ///< Frames transmitted OK register address.
00249 #define EMAC_SCF_OFF                0x00000044  ///< Single collision frame register offset.
00250 #define EMAC_SCF    (*((reg32_t *)(EMAC_BASE +  EMAC_SCF_OFF)))  ///< Single collision frame register address.
00251 #define EMAC_MCF_OFF                0x00000048  ///< Multiple collision frame register offset.
00252 #define EMAC_MCF    (*((reg32_t *)(EMAC_BASE +  EMAC_MCF_OFF)))  ///< Multiple collision frame register address.
00253 #define EMAC_FRO_OFF                0x0000004C  ///< Frames received OK register offset.
00254 #define EMAC_FRO    (*((reg32_t *)(EMAC_BASE +  EMAC_FRO_OFF)))  ///< Frames received OK register address.
00255 #define EMAC_FCSE_OFF               0x00000050  ///< Frame check sequence error register offset.
00256 #define EMAC_FCSE   (*((reg32_t *)(EMAC_BASE +  EMAC_FCSE_OFF))) ///< Frame check sequence error register address.
00257 #define EMAC_ALE_OFF                0x00000054  ///< Alignment error register offset.
00258 #define EMAC_ALE    (*((reg32_t *)(EMAC_BASE +  EMAC_ALE_OFF)))  ///< Alignment error register address.
00259 #define EMAC_DTF_OFF                0x00000058  ///< Deferred transmission frame register offset.
00260 #define EMAC_DTF    (*((reg32_t *)(EMAC_BASE +  EMAC_DTF_OFF)))  ///< Deferred transmission frame register address.
00261 #define EMAC_LCOL_OFF               0x0000005C  ///< Late collision register offset.
00262 #define EMAC_LCOL   (*((reg32_t *)(EMAC_BASE +  EMAC_LCOL_OFF))) ///< Late collision register address.
00263 #define EMAC_ECOL_OFF               0x00000060  ///< Excessive collision register offset.
00264 #define EMAC_ECOL   (*((reg32_t *)(EMAC_BASE +  EMAC_ECOL_OFF))) ///< Excessive collision register address.
00265 #define EMAC_TUNDR_OFF              0x00000064  ///< Transmit underrun error register offset.
00266 #define EMAC_TUNDR (*((reg32_t *)(EMAC_BASE +  EMAC_TUNDR_OFF))) ///< Transmit underrun error register address.
00267 #define EMAC_CSE_OFF                0x00000068  ///< Carrier sense error register offset.
00268 #define EMAC_CSE    (*((reg32_t *)(EMAC_BASE +  EMAC_CSE_OFF)))  ///< Carrier sense error register address.
00269 #define EMAC_RRE_OFF                0x0000006C  ///< Receive resource error register offset.
00270 #define EMAC_RRE    (*((reg32_t *)(EMAC_BASE +  EMAC_RRE_OFF)))  ///< Receive resource error register address.
00271 #define EMAC_ROV_OFF                0x00000070  ///< Receive overrun errors register offset.
00272 #define EMAC_ROV    (*((reg32_t *)(EMAC_BASE +  EMAC_ROV_OFF)))  ///< Receive overrun errors register address.
00273 #define EMAC_RSE_OFF                0x00000074  ///< Receive symbol errors register offset.
00274 #define EMAC_RSE    (*((reg32_t *)(EMAC_BASE +  EMAC_RSE_OFF)))  ///< Receive symbol errors register address.
00275 #define EMAC_ELE_OFF                0x00000078  ///< Excessive length errors register offset.
00276 #define EMAC_ELE    (*((reg32_t *)(EMAC_BASE +  EMAC_ELE_OFF)))  ///< Excessive length errors register address.
00277 #define EMAC_RJA_OFF                0x0000007C  ///< Receive jabbers register offset.
00278 #define EMAC_RJA    (*((reg32_t *)(EMAC_BASE +  EMAC_RJA_OFF)))  ///< Receive jabbers register address.
00279 #define EMAC_USF_OFF                0x00000080  ///< Undersize frames register offset.
00280 #define EMAC_USF    (*((reg32_t *)(EMAC_BASE +  EMAC_USF_OFF)))  ///< Undersize frames register address.
00281 #define EMAC_STE_OFF                0x00000084  ///< SQE test error register offset.
00282 #define EMAC_STE    (*((reg32_t *)(EMAC_BASE +  EMAC_STE_OFF)))  ///< SQE test error register address.
00283 #define EMAC_RLE_OFF                0x00000088  ///< Receive length field mismatch register offset.
00284 #define EMAC_RLE    (*((reg32_t *)(EMAC_BASE +  EMAC_RLE_OFF)))  ///< Receive length field mismatch register address.
00285 // Not in sam7x
00286 //#define EMAC_TPF_OFF                0x0000008C  ///< Transmitted pause frames register offset.
00287 //#define EMAC_TPF    (*((reg32_t *)(EMAC_BASE +  EMAC_TPF_OFF)  ///< Transmitted pause frames register address.
00288 /* \} */
00289 
00294 /* \{ */
00295 #define EMAC_HRB_OFF                0x00000090  ///< Hash address bottom[31:0].
00296 #define EMAC_HRB    (*((reg32_t *)(EMAC_BASE +  EMAC_HRB_OFF)))  ///< Hash address bottom[31:0].
00297 #define EMAC_HRT_OFF                0x00000094  ///< Hash address top[63:32].
00298 #define EMAC_HRT    (*((reg32_t *)(EMAC_BASE +  EMAC_HRT_OFF)))  ///< Hash address top[63:32].
00299 #define EMAC_SA1L_OFF               0x00000098  ///< Specific address 1 bottom, first 4 bytes.
00300 #define EMAC_SA1L   (*((reg32_t *)(EMAC_BASE +  EMAC_SA1L_OFF))) ///< Specific address 1 bottom, first 4 bytes.
00301 #define EMAC_SA1H_OFF               0x0000009C  ///< Specific address 1 top, last 2 bytes.
00302 #define EMAC_SA1H   (*((reg32_t *)(EMAC_BASE +  EMAC_SA1H_OFF))) ///< Specific address 1 top, last 2 bytes.
00303 #define EMAC_SA2L_OFF               0x000000A0  ///< Specific address 2 bottom, first 4 bytes.
00304 #define EMAC_SA2L   (*((reg32_t *)(EMAC_BASE +  EMAC_SA2L_OFF))) ///< Specific address 2 bottom, first 4 bytes.
00305 #define EMAC_SA2H_OFF               0x000000A4  ///< Specific address 2 top, last 2 bytes.
00306 #define EMAC_SA2H   (*((reg32_t *)(EMAC_BASE +  EMAC_SA2H_OFF))) ///< Specific address 2 top, last 2 bytes.
00307 #define EMAC_SA3L_OFF               0x000000A8  ///< Specific address 3 bottom, first 4 bytes.
00308 #define EMAC_SA3L   (*((reg32_t *)(EMAC_BASE +  EMAC_SA3L_OFF))) ///< Specific address 3 bottom, first 4 bytes.
00309 #define EMAC_SA3H_OFF               0x000000AC  ///< Specific address 3 top, last 2 bytes.
00310 #define EMAC_SA3H   (*((reg32_t *)(EMAC_BASE +  EMAC_SA3H_OFF))) ///< Specific address 3 top, last 2 bytes.
00311 #define EMAC_SA4L_OFF               0x000000B0  ///< Specific address 4 bottom, first 4 bytes.
00312 #define EMAC_SA4L   (*((reg32_t *)(EMAC_BASE +  EMAC_SA4L_OFF))) ///< Specific address 4 bottom, first 4 bytes.
00313 #define EMAC_SA4H_OFF               0x000000B4  ///< Specific address 4 top, last 2 bytes.
00314 #define EMAC_SA4H   (*((reg32_t *)(EMAC_BASE +  EMAC_SA4H_OFF))) ///< Specific address 4 top, last 2 bytes.
00315 /* \} */
00316 
00321 /* \{ */
00322 #define EMAC_TID_OFF                0x000000B8  ///< Type ID checking register offset.
00323 #define EMAC_TID    (*((reg32_t *)(EMAC_BASE +  EMAC_TID_OFF))) ///< Type ID checking register address.
00324 // Not in sam7x
00325 //#define EMAC_TPQ_OFF                0x000000BC  ///< Transmit pause quantum register offset.
00326 //#define EMAC_TPQ    (*((reg32_t *)(EMAC_BASE +  EMAC_TPQ_OFF)))  ///< Transmit pause quantum register address.
00327 /* \} */
00328 
00333 /* \{ */
00334 #define EMAC_USRIO_OFF              0x000000C0  ///< User input/output register offset.
00335 #define EMAC_USRIO (*((reg32_t *)(EMAC_BASE +  EMAC_USRIO_OFF))) ///< User input/output register address.
00336 
00337 #define EMAC_RMII                            0  ///< Enable reduced MII.
00338 #define EMAC_CLKEN                           1  ///< Enable tranceiver input clock.
00339 /* \} */
00340 
00341 // Not in sam7x
00342 /*
00343  * Wake On LAN Register
00344  *
00345  *
00346 * \{ *
00347 #define EMAC_WOL_OFF                0x000000C4  ///< Wake On LAN register offset.
00348 #define EMAC_WOL    (*((reg32_t *)(EMAC_BASE +  EMAC_WOL_OFF)  ///< Wake On LAN register address.
00349 #define EMAC_IP                     0x0000FFFF  ///< ARP request IP address mask.
00350 #define EMAC_MAG                    0x00010000  ///< Magic packet event enable.
00351 #define EMAC_ARP                    0x00020000  ///< ARP request event enable.
00352 #define EMAC_SA1                    0x00040000  ///< Specific address register 1 event enable.
00353 * \} *
00354 
00355 ** Revision Register *
00356 * \{ *
00357 #define EMAC_REV_OFF                0x000000FC  ///< Revision register offset.
00358 #define EMAC_REV    (*((reg32_t *)(EMAC_BASE +  EMAC_REV_OFF)  ///< Revision register address.
00359 #define EMAC_REVREF                 0x0000FFFF  ///< Revision.
00360 #define EMAC_PARTREF                0xFFFF0000  ///< Part.
00361 * \} *
00362 */
00363 
00364 #endif /* AT91_EMAC_H */