BeRTOS
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Go to the source code of this file.
Defines | |
#define | WDT_CR_OFF 0x00000000 |
Watch Dog Control Register. | |
#define | WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) |
Watchdog control register address. | |
#define | WDT_WDRSTT 0 |
Watchdog restart. | |
#define | WDT_KEY 0xA5000000 |
Watchdog password. | |
#define | WDT_MR_OFF 0x00000004 |
Watch Dog Mode Register. | |
#define | WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) |
Mode register address. | |
#define | WDT_WDV_MASK 0x00000FFF |
Counter value mask. | |
#define | WDT_WDV_SHIFT 0 |
Counter value LSB. | |
#define | WDT_WDFIEN 12 |
Fault interrupt enable. | |
#define | WDT_WDRSTEN 13 |
Reset enable. | |
#define | WDT_WDRPROC 14 |
Eset processor enable. | |
#define | WDT_WDDIS 15 |
Watchdog disable. | |
#define | WDT_WDD_MASK 0x0FFF0000 |
Delta value mask. | |
#define | WDT_WDD_SHIFT 16 |
Delta value LSB. | |
#define | WDT_WDDBGHLT 28 |
Watchdog debug halt. | |
#define | WDT_WDIDLEHLT 29 |
Watchdog idle halt. | |
#define | WDT_SR_OFF 0x00000008 |
Watch Dog Status Register. | |
#define | WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) |
Status register address. | |
#define | WDT_WDUNF 0 |
Watchdog underflow. | |
#define | WDT_WDERR 1 |
Watchdog error. |
AT91 Watchdog. This file is based on NUT/OS implementation. See license below.
Definition in file at91_wdt.h.
#define WDT_CR_OFF 0x00000000 |
Watch Dog Control Register.
Watchdog control register offset.
Definition at line 79 of file at91_wdt.h.
#define WDT_MR_OFF 0x00000004 |
#define WDT_SR_OFF 0x00000008 |