BeRTOS
ser_lm3s.h
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00001 
00038 #ifndef SER_LM3S_H
00039 #define SER_LM3S_H
00040 
00041 #include <cfg/cfg_debug.h>
00042 #include <cpu/power.h> /* cpu_relax() */
00043 #include <drv/clock_lm3s.h> /* lm3s_busyWait() */
00044 #include <io/lm3s.h>
00045 
00046 /* Serial hardware numbers */
00047 enum
00048 {
00049     SER_UART0,
00050     SER_UART1,
00051     SER_UART2,
00052 
00053     SER_CNT //< Number of serial ports
00054 };
00055 
00056 /* Software errors */
00057 #define SERRF_RXFIFOOVERRUN  BV(0) //< Rx FIFO buffer overrun
00058 #define SERRF_RXTIMEOUT      BV(1) //< Receive timeout
00059 #define SERRF_TXTIMEOUT      BV(2) //< Transmit timeout
00060 
00061 /*
00062  * Hardware errors.
00063  */
00064 #define SERRF_RXSROVERRUN    0 //< Input overrun
00065 #define SERRF_FRAMEERROR     0 //< Stop bit missing
00066 #define SERRF_PARITYERROR    0 //< Parity error
00067 #define SERRF_NOISEERROR     0 //< Noise error
00068 
00069 /* Serial error/status flags */
00070 typedef uint32_t serstatus_t;
00071 
00072 INLINE void lm3s_uartDisable(uint32_t base)
00073 {
00074     /* Disable the hardware FIFO */
00075     HWREG(base + UART_O_LCRH) &= ~UART_LCRH_FEN;
00076 
00077     /* Disable the UART */
00078     HWREG(base + UART_O_CTL) &=
00079         ~(UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE);
00080     lm3s_busyWait(512);
00081 }
00082 
00083 INLINE void lm3s_uartEnable(uint32_t base)
00084 {
00085     /* Enable the hardware FIFO */
00086     HWREG(base + UART_O_LCRH) |= UART_LCRH_FEN;
00087 
00088     /* Enable RX, TX, and the UART */
00089     HWREG(base + UART_O_CTL) |=
00090             UART_CTL_UARTEN | UART_CTL_TXE | UART_CTL_RXE;
00091     lm3s_busyWait(512);
00092 }
00093 
00094 /* Clear the flags register */
00095 INLINE void lm3s_uartClear(uint32_t base)
00096 {
00097     HWREG(base + UART_O_FR) = 0;
00098 }
00099 
00100 INLINE bool lm3s_uartTxDone(uint32_t base)
00101 {
00102     return HWREG(base + UART_O_FR) & UART_FR_TXFE ? true : false;
00103 }
00104 
00105 INLINE bool lm3s_uartTxReady(uint32_t base)
00106 {
00107     return HWREG(base + UART_O_FR) & UART_FR_TXFF ? false : true;
00108 }
00109 
00110 INLINE bool lm3s_uartRxReady(uint32_t base)
00111 {
00112     return HWREG(base + UART_O_FR) & UART_FR_RXFE ? false : true;
00113 }
00114 
00115 INLINE bool lm3s_uartReady(uint32_t base)
00116 {
00117     return HWREG(base + UART_O_FR) & UART_FR_BUSY ? false : true;
00118 }
00119 
00120 INLINE int lm3s_uartPutCharNonBlocking(uint32_t base, unsigned char c)
00121 {
00122     if (!lm3s_uartTxReady(base))
00123         return EOF;
00124     HWREG(base + UART_O_DR) = c;
00125     return c;
00126 }
00127 
00128 INLINE int lm3s_uartPutChar(uint32_t base, unsigned char c)
00129 {
00130     while (!lm3s_uartTxReady(base))
00131         cpu_relax();
00132     HWREG(base + UART_O_DR) = c;
00133     return c;
00134 }
00135 
00136 INLINE int lm3s_uartGetCharNonBlocking(uint32_t base)
00137 {
00138     if (!lm3s_uartRxReady(base))
00139         return EOF;
00140     return HWREG(base + UART_O_DR);
00141 }
00142 
00143 INLINE int lm3s_uartGetChar(uint32_t base)
00144 {
00145     while (!lm3s_uartRxReady(base))
00146         cpu_relax();
00147     return HWREG(base + UART_O_DR);
00148 }
00149 
00150 void lm3s_uartSetBaudRate(uint32_t base, unsigned long baud);
00151 void lm3s_uartSetParity(uint32_t base, int parity);
00152 void lm3s_uartInit(int port);
00153 
00154 #endif /* SER_LM3S_H */