BeRTOS
stm32_uart.h
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00001 
00036 #ifndef STM32_UART_H
00037 #define STM32_UART_H
00038 
00039 /*
00040  * USART Word Length
00041  */
00042 #define USART_WORD_LEN_8B                  ((uint16_t)0x0000)
00043 #define USART_WORD_LEN_9B                  ((uint16_t)0x1000)
00044 
00045 /*
00046  * USART Stop Bits
00047  */
00048 #define USART_STOP_BIT_1                     ((uint16_t)0x0000)
00049 #define USART_STOP_BIT_0_5                   ((uint16_t)0x1000)
00050 #define USART_STOP_BIT_2                     ((uint16_t)0x2000)
00051 #define USART_STOP_BIT_1_5                   ((uint16_t)0x3000)
00052 
00053 /*
00054  * USART Parity
00055  */
00056 #define USART_PARITY_NO                      ((uint16_t)0x0000)
00057 #define USART_PARITY_EVEN                    ((uint16_t)0x0400)
00058 #define USART_PARITY_ODD                     ((uint16_t)0x0600)
00059 
00060 
00061 /*
00062  * USART Hardware Flow Control
00063  */
00064 #define USART_HW_FLOW_NONE       ((uint16_t)0x0000)
00065 #define USART_HW_FLOW_RTS        ((uint16_t)0x0100)
00066 #define USART_HW_FLOW_CTS        ((uint16_t)0x0200)
00067 #define USART_HW_FLOW_RTS_CTS    ((uint16_t)0x0300)
00068 
00069 
00070 /*
00071  * USART Clock
00072  */
00073 #define USART_CLK_DIS                  ((uint16_t)0x0000)
00074 #define USART_CLK_EN                   ((uint16_t)0x0800)
00075 
00076 /*
00077  * USART Clock Polarity
00078  */
00079 #define USART_CPOL_LOW                       ((uint16_t)0x0000)
00080 #define USART_CPOL_HIGHT                      ((uint16_t)0x0400)
00081 
00082 /*
00083  * USART Clock Phase
00084  */
00085 #define USART_CPHA_1EDGE                     ((uint16_t)0x0000)
00086 #define USART_CPHA_2EDGE                     ((uint16_t)0x0200)
00087 
00088 
00089 
00090 /*
00091  * USART Interrupt definition
00092  */
00093 #define USART_IT_PE                          ((uint16_t)0x0028)
00094 #define USART_IT_TXE                         ((uint16_t)0x0727)
00095 #define USART_IT_TC                          ((uint16_t)0x0626)
00096 #define USART_IT_RXNE                        ((uint16_t)0x0525)
00097 #define USART_IT_IDLE                        ((uint16_t)0x0424)
00098 #define USART_IT_LBD                         ((uint16_t)0x0846)
00099 #define USART_IT_CTS                         ((uint16_t)0x096A)
00100 #define USART_IT_ERR                         ((uint16_t)0x0060)
00101 #define USART_IT_ORE                         ((uint16_t)0x0360)
00102 #define USART_IT_NE                          ((uint16_t)0x0260)
00103 #define USART_IT_FE                          ((uint16_t)0x0160)
00104 
00105 
00106 #define INT_UART0_CR1                                      0x0C
00107 #define INT_UART0_CR2                                      0x10
00108 #define INT_UART0_CR3                                      0x14
00109 
00110 /*
00111  * USART DMA Requests
00112  */
00113 #define USART_DMA_REQ_TX                      ((uint16_t)0x0080)
00114 #define USART_DMA_REQ_RX                      ((uint16_t)0x0040)
00115 
00116 /*
00117  * USART WakeUp methods
00118  */
00119 #define USART_WAKEUP_IDLELINE                ((uint16_t)0x0000)
00120 #define USART_WAKEUP_ADRESSMARK             ((uint16_t)0x0800)
00121 
00122 
00123 /*
00124  * USART LIN Break Detection Length
00125  */
00126 #define USART_LIN_BREAK_DET_LEN_10B      ((uint16_t)0x0000)
00127 #define USART_LIN_BREAK_DET_LEN_11B      ((uint16_t)0x0020)
00128 
00129 /*
00130  * USART IrDA Low Power
00131  */
00132 #define USART_IRDA_MODE_LOWPOWER              ((uint16_t)0x0004)
00133 #define USART_IRDA_MODE_NORMAL                ((uint16_t)0x0000)
00134 
00135 
00136 #define CR1_RUN_SET               ((uint16_t)0x2000)  /* USART Enable MASK */
00137 #define CR1_RUN_RESET             ((uint16_t)0xDFFF)  /* USART Disable MASK */
00138 #define CR1_RWU_SET               ((uint16_t)0x0002)  /* USART mute mode Enable MASK */
00139 #define CR1_RWU_RESET             ((uint16_t)0xFFFD)  /* USART mute mode Enable MASK */
00140 #define CR1_SBK_SET               ((uint16_t)0x0001)  /* USART Break Character send MASK */
00141 #define CR1_USART_CLEAR_MASK      ((uint16_t)0xE9F3)  /* USART CR1 MASK */
00142 #define CR1_UE                                   13
00143 #define CR1_M                                    12
00144 #define CR1_WAKE                                 11
00145 #define CR1_PCE                                  10
00146 #define CR1_PS                                    9
00147 #define CR1_PEIE                                  8
00148 #define CR1_TXEIE                                 7
00149 #define CR1_TCIE                                  6
00150 #define CR1_RXNEIE                                5
00151 #define CR1_IDLEIE                                4
00152 #define CR1_TE                                    3
00153 #define CR1_RE                                    2
00154 #define CR1_RWU                                   1
00155 #define CR1_SBK                                   0
00156 
00157 #define CR2_MASK                  ((uint16_t)0xFFF0)  /* USART address MASK */
00158 #define CR2_LINE_SET              ((uint16_t)0x4000)  /* USART LIN Enable MASK */
00159 #define CR2_LINE_RESET            ((uint16_t)0xBFFF)  /* USART LIN Disable MASK */
00160 #define CR2_USART_CLEAR_MASK      ((uint16_t)0xC0FF)  /* USART CR2 MASK */
00161 
00162 #define CR3_SCEN_SET              ((uint16_t)0x0020)  /* USART SC Enable MASK */
00163 #define CR3_SCEN_RESET            ((uint16_t)0xFFDF)  /* USART SC Disable MASK */
00164 #define CR3_NACK_SET              ((uint16_t)0x0010)  /* USART SC NACK Enable MASK */
00165 #define CR3_NACK_RESET            ((uint16_t)0xFFEF)  /* USART SC NACK Disable MASK */
00166 #define CR3_HDSEL_SET             ((uint16_t)0x0008)  /* USART Half-Duplex Enable MASK */
00167 #define CR3_HDSEL_RESET           ((uint16_t)0xFFF7)  /* USART Half-Duplex Disable MASK */
00168 #define CR3_IRLP_MASK             ((uint16_t)0xFFFB)  /* USART IrDA LowPower mode MASK */
00169 #define CR3_LBDL_MASK             ((uint16_t)0xFFDF)  /* USART LIN Break detection MASK */
00170 #define CR3_WAKE_MASK             ((uint16_t)0xF7FF)  /* USART WakeUp Method MASK */
00171 #define CR3_IREN_SET              ((uint16_t)0x0002)  /* USART IrDA Enable MASK */
00172 #define CR3_IREN_RESET            ((uint16_t)0xFFFD)  /* USART IrDA Disable MASK */
00173 #define CR3_CLEAR_MASK            ((uint16_t)0xFCFF)  /* USART CR3 MASK */
00174 
00175 
00176 /* Status */
00177 #define SR_CTS                                    9
00178 #define SR_LBD                                    8
00179 #define SR_TXE                                    7
00180 #define SR_TC                                     6
00181 #define SR_RXNE                                   5
00182 #define SR_IDLE                                   4
00183 #define SR_ORE                                    3
00184 #define SR_NE                                     2
00185 #define SR_FE                                     1
00186 #define SR_PE                                     0
00187 
00188 #define GTPR_LSB_MASK             ((uint16_t)0x00FF)  /* Guard Time Register LSB MASK */
00189 #define GTPR_MSB_MASK             ((uint16_t)0xFF00)  /* Guard Time Register MSB MASK */
00190 
00191 #define USART_IT_MASK             ((uint16_t)0x001F)  /* USART Interrupt MASK */
00192 
00193 /* USART flags */
00194 #define USART_FLAG_CTS            ((uint16_t)0x0200)
00195 #define USART_FLAG_LBD            ((uint16_t)0x0100)
00196 #define USART_FLAG_TXE            ((uint16_t)0x0080)
00197 #define USART_FLAG_TC             ((uint16_t)0x0040)
00198 #define USART_FLAG_RXNE           ((uint16_t)0x0020)
00199 #define USART_FLAG_IDLE           ((uint16_t)0x0010)
00200 #define USART_FLAG_ORE            ((uint16_t)0x0008)
00201 #define USART_FLAG_NE             ((uint16_t)0x0004)
00202 #define USART_FLAG_FE             ((uint16_t)0x0002)
00203 #define USART_FLAG_PE             ((uint16_t)0x0001)
00204 #define USART_FLAG_MASK           ((uint16_t)0x03FF)
00205 
00206 
00207 /* USART registers */
00208 struct stm32_usart
00209 {
00210     reg16_t SR;
00211     uint16_t _RESERVED0;
00212     reg16_t DR;
00213     uint16_t _RESERVED1;
00214     reg16_t BRR;
00215     uint16_t _RESERVED2;
00216     reg16_t CR1;
00217     uint16_t _RESERVED3;
00218     reg16_t CR2;
00219     uint16_t _RESERVED4;
00220     reg16_t CR3;
00221     uint16_t _RESERVED5;
00222     reg16_t GTPR;
00223     uint16_t _RESERVED6;
00224 };
00225 
00226 /* USART mode */
00227 #define USART_MODE_RX             ((uint16_t)0x0004)
00228 #define USART_MODE_TX             ((uint16_t)0x0008)
00229 
00230 /* USART last bit */
00231 #define USART_LASTBIT_DISABLE     ((uint16_t)0x0000)
00232 #define USART_LASTBIT_ENABLE      ((uint16_t)0x0100)
00233 
00234 
00235 INLINE uint16_t evaluate_brr(struct stm32_usart *base, unsigned long cpu_freq, unsigned long baud)
00236 {
00237     uint32_t freq, reg, div, frac;
00238 
00239     /* NOTE: PCLK1 has been configured as CPU_FREQ / 2 */
00240     freq = (base == (struct stm32_usart *)USART1_BASE) ? cpu_freq : cpu_freq / 2;
00241     div = (0x19 * freq) / (0x04 * baud);
00242     reg = (div / 0x64) << 0x04;
00243     frac = div - (0x64 * (reg >> 0x04));
00244     reg |= ((frac * 0x10 + 0x32) / 0x64) & 0x0f;
00245 
00246     return (uint16_t)reg;
00247 }
00248 
00249 #endif /* STM32_UART_H */
00250