BeRTOS
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00001 00040 /* 00041 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. 00042 * 00043 * Redistribution and use in source and binary forms, with or without 00044 * modification, are permitted provided that the following conditions 00045 * are met: 00046 * 00047 * 1. Redistributions of source code must retain the above copyright 00048 * notice, this list of conditions and the following disclaimer. 00049 * 2. Redistributions in binary form must reproduce the above copyright 00050 * notice, this list of conditions and the following disclaimer in the 00051 * documentation and/or other materials provided with the distribution. 00052 * 3. Neither the name of the copyright holders nor the names of 00053 * contributors may be used to endorse or promote products derived 00054 * from this software without specific prior written permission. 00055 * 00056 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00057 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00058 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00059 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00060 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00061 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00062 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00063 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00064 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00065 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00066 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00067 * SUCH DAMAGE. 00068 * 00069 * For additional information see http://www.ethernut.de/ 00070 */ 00071 00072 #ifndef SAM3_WDT_H 00073 #define SAM3_WDT_H 00074 00076 #if CPU_CM3_SAM3N 00077 #define WDT_BASE 0x400E1450 00078 #elif CPU_CM3_SAM3X 00079 #define WDT_BASE 0x400E1A50 00080 #endif 00081 00083 /*\{*/ 00084 #define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset. 00085 #define WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address. 00086 #define WDT_WDRSTT 0 ///< Watchdog restart. 00087 #define WDT_KEY 0xA5000000 ///< Watchdog password. 00088 /*\}*/ 00089 00091 /*\{*/ 00092 #define WDT_MR_OFF 0x00000004 ///< Mode register offset. 00093 #define WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address. 00094 #define WDT_WDV_MASK 0x00000FFF ///< Counter value mask. 00095 #define WDT_WDV_SHIFT 0 ///< Counter value LSB. 00096 #define WDT_WDFIEN 12 ///< Fault interrupt enable. 00097 #define WDT_WDRSTEN 13 ///< Reset enable. 00098 #define WDT_WDRPROC 14 ///< Eset processor enable. 00099 #define WDT_WDDIS 15 ///< Watchdog disable. 00100 #define WDT_WDD_MASK 0x0FFF0000 ///< Delta value mask. 00101 #define WDT_WDD_SHIFT 16 ///< Delta value LSB. 00102 #define WDT_WDDBGHLT 28 ///< Watchdog debug halt. 00103 #define WDT_WDIDLEHLT 29 ///< Watchdog idle halt. 00104 /*\}*/ 00105 00107 /*\{*/ 00108 #define WDT_SR_OFF 0x00000008 ///< Status register offset. 00109 #define WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address. 00110 #define WDT_WDUNF 0 ///< Watchdog underflow. 00111 #define WDT_WDERR 1 ///< Watchdog error. 00112 /*\}*/ 00113 00114 #endif /* SAM3_WDT_H */