BeRTOS
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00001 00040 #ifndef ETH_SAM3_H 00041 #define ETH_SAM3_H 00042 00043 // Settings and definition for DAVICOM 9161A 00044 // \{ 00045 #define NIC_PHY_ADDR 0 00046 00047 // Register bits definition 00048 #define NIC_PHY_BMCR 0x00 // Basic mode control register. 00049 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test. 00050 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode. 00051 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation. 00052 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII. 00053 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down. 00054 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation. 00055 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps. 00056 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode. 00057 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset. 00058 00059 #define NIC_PHY_BMSR 0x01 // Basic mode status register. 00060 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete. 00061 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation 00062 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status. 00063 00064 #define NIC_PHY_ANLPAR_10_HDX BV(5) // 10BASE-T half duplex 00065 #define NIC_PHY_ANLPAR_10_FDX BV(6) // 10BASE-T full duplex 00066 #define NIC_PHY_ANLPAR_TX_HDX BV(7) // 100BASE-TX half duplex 00067 #define NIC_PHY_ANLPAR_TX_FDX BV(8) // 100BASE-TX full duplex 00068 00069 #define NIC_PHY_ID1 0x02 // PHY identifier register 1. 00070 #define NIC_PHY_ID2 0x03 // PHY identifier register 2. 00071 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register. 00072 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register. 00073 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register. 00074 00075 #if CPU_ARM_AT91 00076 00077 /* 00078 * Pin definition for DAVICOM 9161A. 00079 * See schematics for AT91SAM7X-EK evalution board. 00080 */ 00081 // All pins in port B 00082 #define PHY_REFCLK_XT2_BIT 0 00083 #define PHY_TXEN_BIT 1 00084 #define PHY_TXD0_BIT 2 00085 #define PHY_TXD1_BIT 3 00086 #define PHY_CRS_AD4_BIT 4 00087 #define PHY_RXD0_AD0_BIT 5 00088 #define PHY_RXD1_AD1_BIT 6 00089 #define PHY_RXER_RXD4_RPTR_BIT 7 00090 #define PHY_MDC_BIT 8 00091 #define PHY_MDIO_BIT 9 00092 #define PHY_TXD2_BIT 10 00093 #define PHY_TXD3_BIT 11 00094 #define PHY_TXER_TXD4_BIT 12 00095 #define PHY_RXD2_AD2_BIT 13 00096 #define PHY_RXD3_AD3_BIT 14 00097 #define PHY_RXDV_TESTMODE_BIT 15 00098 #define PHY_COL_RMII_BIT 16 00099 #define PHY_RXCLK_10BTSER_BIT 17 00100 #define PHY_PWRDN_BIT 18 00101 #define PHY_MDINTR_BIT 26 00102 00103 #define PHY_MII_PINS \ 00104 BV(PHY_REFCLK_XT2_BIT) \ 00105 | BV(PHY_TXEN_BIT) \ 00106 | BV(PHY_TXD0_BIT) \ 00107 | BV(PHY_TXD1_BIT) \ 00108 | BV(PHY_CRS_AD4_BIT) \ 00109 | BV(PHY_RXD0_AD0_BIT) \ 00110 | BV(PHY_RXD1_AD1_BIT) \ 00111 | BV(PHY_RXER_RXD4_RPTR_BIT) \ 00112 | BV(PHY_MDC_BIT) \ 00113 | BV(PHY_MDIO_BIT) \ 00114 | BV(PHY_TXD2_BIT) \ 00115 | BV(PHY_TXD3_BIT) \ 00116 | BV(PHY_TXER_TXD4_BIT) \ 00117 | BV(PHY_RXD2_AD2_BIT) \ 00118 | BV(PHY_RXD3_AD3_BIT) \ 00119 | BV(PHY_RXDV_TESTMODE_BIT) \ 00120 | BV(PHY_COL_RMII_BIT) \ 00121 | BV(PHY_RXCLK_10BTSER_BIT) 00122 00123 #else 00124 00125 /* 00126 * Pin definition for DAVICOM 9161A. 00127 * See schematics for SAM3X-EK evalution board. 00128 */ 00129 // Port B 00130 #define PHY_REFCLK_XT2_BIT 0 00131 #define PHY_TXEN_BIT 1 00132 #define PHY_TXD0_BIT 2 00133 #define PHY_TXD1_BIT 3 00134 #define PHY_RXD0_AD0_BIT 5 00135 #define PHY_RXD1_AD1_BIT 6 00136 #define PHY_RXER_RXD4_RPTR_BIT 7 00137 #define PHY_MDC_BIT 8 00138 #define PHY_MDIO_BIT 9 00139 // Port C 00140 #define PHY_RXDV_TESTMODE_BIT 10 00141 // Port A 00142 #define PHY_MDINTR_BIT 5 00143 // Port D -- FIXME: Only on which revision? 00144 #define PHY_PWRDN_BIT 18 00145 00146 #define PHY_MII_PINS_PORTB \ 00147 BV(PHY_REFCLK_XT2_BIT) \ 00148 | BV(PHY_TXEN_BIT) \ 00149 | BV(PHY_TXD0_BIT) \ 00150 | BV(PHY_TXD1_BIT) \ 00151 | BV(PHY_RXD0_AD0_BIT) \ 00152 | BV(PHY_RXD1_AD1_BIT) \ 00153 | BV(PHY_RXER_RXD4_RPTR_BIT) \ 00154 | BV(PHY_MDC_BIT) \ 00155 | BV(PHY_MDIO_BIT) 00156 00157 #define PHY_MII_PINS_PORTC \ 00158 BV(PHY_RXDV_TESTMODE_BIT) 00159 00160 #endif /* CPU_ARM_AT91 */ 00161 // \} 00162 00163 00164 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this 00165 #define EMAC_TX_BUFFERS 1 //!!! Don't change this 00166 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS 00167 00168 #define EMAC_RX_BUFFERS 32 //!!! Don't change this 00169 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this 00170 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS 00171 00172 // Flag to manage local tx buffer 00173 #define TXS_USED 0x80000000 //Used buffer. 00174 #define TXS_WRAP 0x40000000 //Last descriptor. 00175 #define TXS_ERROR 0x20000000 //Retry limit exceeded. 00176 #define TXS_UNDERRUN 0x10000000 //Transmit underrun. 00177 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted. 00178 #define TXS_NO_CRC 0x00010000 //CRC not appended. 00179 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame. 00180 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS. 00181 00182 // Flag to manage local rx buffer 00183 #define RXBUF_OWNERSHIP 0x00000001 00184 #define RXBUF_WRAP 0x00000002 00185 00186 #define BUF_ADDRMASK 0xFFFFFFFC 00187 00188 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected. 00189 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match. 00190 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match. 00191 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match. 00192 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match. 00193 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match. 00194 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match. 00195 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match. 00196 #define RXS_TYPE_ID 0x00400000 // Type ID match. 00197 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected. 00198 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected. 00199 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority. 00200 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator. 00201 #define RXS_EOF 0x00008000 // End of frame. 00202 #define RXS_SOF 0x00004000 // Start of frame. 00203 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask. 00204 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS. 00205 00206 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR)) 00207 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \ 00208 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND)) 00209 00210 typedef struct BufDescriptor 00211 { 00212 volatile uint32_t addr; 00213 volatile uint32_t stat; 00214 } BufDescriptor; 00215 00216 #endif /* ETH_SAM3_H */