BeRTOS
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00001 00038 #ifndef DRV_VIC_LPC2_H 00039 #define DRV_VIC_LPC2_H 00040 00041 #include <cfg/compiler.h> 00042 #include <cpu/irq.h> 00043 00044 #if CPU_ARM_LPC2378 00045 #include <io/lpc23xx.h> 00046 #define vic_vector(i) (*(&VICVectAddr0 + i)) 00047 #define vic_priority(i) (*(&VICVectCntl0 + i)) 00048 #define VIC_SRC_CNT 32 00049 #define vic_enable(i) do { ASSERT(i < VIC_SRC_CNT); VICIntEnable = BV(i); } while (0) 00050 #define vic_disable(i) do { ASSERT(i < VIC_SRC_CNT); VICIntEnClr = BV(i); } while (0) 00051 00052 typedef void vic_handler_t(void); 00053 void vic_defaultHandler(void); 00054 00055 INLINE void vic_init(void) 00056 { 00057 IRQ_DISABLE; 00058 /* Assign all sources to IRQ (not to FIQ) */ 00059 VICIntSelect = 0; 00060 /* Disable all sw interrupts */ 00061 VICSoftIntClr = 0xFFFFFFFF; 00062 /* Disable all interrupts */ 00063 VICIntEnClr = 0xFFFFFFFF; 00064 00065 for (int i = 0; i < VIC_SRC_CNT; i++) 00066 vic_vector(i) = (reg32_t)vic_defaultHandler; 00067 } 00068 00069 INLINE void vic_setVector(int id, vic_handler_t *handler) 00070 { 00071 ASSERT(id < VIC_SRC_CNT); 00072 vic_vector(id) = (reg32_t)handler; 00073 } 00074 #else 00075 #error Unknown CPU 00076 #endif 00077 00078 #endif /* DRV_VIC_LPC2_H */