BeRTOS
kdebug_msp430.c
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00001 
00039 #include "kdebug_msp430.h"  /* for UART clock source definitions */
00040 
00041 #include "hw/hw_ser.h"      /* bus macros overrides */
00042 #include "cfg/cfg_debug.h"
00043 
00044 #include <cfg/macros.h>     /* for DIV_ROUND */
00045 
00046 #include <cpu/types.h>
00047 #include <cpu/attr.h>
00048 
00049 #include <io.h>
00050 
00051 #if CONFIG_KDEBUG_PORT == 0
00052 
00053     #ifndef KDBG_UART0_BUS_INIT
00054     #define KDBG_UART0_BUS_INIT  do {} while (0)
00055     #endif
00056     #ifndef KDBG_UART0_BUS_RX
00057     #define KDBG_UART0_BUS_RX    do {} while (0)
00058     #endif
00059     #ifndef KDBG_UART0_BUS_TX
00060     #define KDBG_UART0_BUS_TX    do {} while (0)
00061     #endif
00062 
00063     /* USCI Register definitions */
00064     #define UCSTAT  UCA0STAT
00065     #define UCTXBUF UCA0TXBUF
00066     #define UCRXBUF UCA0RXBUF
00067     #define UCTXIFG UCA0TXIFG
00068     #define UCRXIFG UCA0RXIFG
00069     #define UCTXIE  UCA0TXIE
00070     #define UCRXIE  UCA0RXIE
00071     #define UCCTL0  UCA0CTL0
00072     #define UCCTL1  UCA0CTL1
00073     #define UCBR0   UCA0BR0
00074     #define UCBR1   UCA0BR1
00075     #define UCMCTL  UCA0MCTL
00076     #define IE      IE2
00077     #define IFG     IFG2
00078 
00079     #if CPU_MSP430F2274
00080         #define KDBG_MSP430_UART_PINS_INIT()    do{ P3SEL = 0x30; }while(0)
00081     #endif
00082 
00083 #else
00084 
00085     #if CPU_MSP430F2274
00086         #error only 1 UART availbale, CONFIG_KDEBUG_PORT should be 0
00087     #endif
00088 
00089 #endif
00090 
00091 #define KDBG_WAIT_READY()     do { while((UCSTAT & UCBUSY)); } while(0)
00092 #define KDBG_WAIT_TXDONE()    do { while(!(IFG & UCTXIFG)); } while(0)
00093 
00094 #define KDBG_WRITE_CHAR(c)    do { UCTXBUF = (c); } while(0)
00095 
00096 #define KDBG_MASK_IRQ(old)    do { \
00097     (old) = IE; \
00098     IE &= ~(UCTXIE|UCRXIE);\
00099 } while(0)
00100 
00101 #define KDBG_RESTORE_IRQ(old) do { \
00102     KDBG_WAIT_TXDONE(); \
00103     IE = (old); \
00104 } while(0)
00105 
00106 #if CONFIG_KDEBUG_CLOCK_FREQ
00107     #define KDBG_MSP430_FREQ CONFIG_KDEBUG_CLOCK_FREQ
00108 #else
00109     #define KDBG_MSP430_FREQ CPU_FREQ
00110 #endif
00111 
00112 typedef uint8_t kdbg_irqsave_t;
00113 
00114 INLINE void kdbg_hw_init(void)
00115 {
00116     /* Compute the clock prescaler for the desired baudrate */
00117     uint16_t quot = DIV_ROUND(KDBG_MSP430_FREQ, CONFIG_KDEBUG_BAUDRATE);
00118     KDBG_MSP430_UART_PINS_INIT();       // Configure USCI TX/RX pins
00119 
00120 #if (CONFIG_KDEBUG_CLOCK_SOURCE == KDBG_UART_SMCLK)
00121     UCCTL1 |= UCSSEL_SMCLK;
00122 #else
00123     UCCTL1 |= UCSSEL_ACLK;
00124 #endif
00125 
00126     UCBR0   = quot & 0xFF;              // Setup clock prescaler for the UART
00127     UCBR1   = quot >> 8;
00128 
00129     UCMCTL  = UCBRS0;                   // No Modulation
00130     UCCTL0  = 0;                        // Default UART settings (8N1)
00131     UCCTL1 &= ~UCSWRST;                 // Initialize USCI state machine
00132     KDBG_MASK_IRQ(IE2);                 // Disable USCI interrupts
00133 }
00134