BeRTOS
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00001 00039 #include "stepper_at91.h" 00040 00041 #include "cfg/cfg_stepper.h" 00042 #include <cfg/macros.h> 00043 #include <cfg/debug.h> 00044 00045 #include <cpu/types.h> 00046 #include <cpu/irq.h> 00047 00048 #include <io/arm.h> 00049 00050 00051 #warning FIXME:This test is incomplete.. you MUST review.. 00052 00053 #if 0 00054 static void stepper_test_irq_schedule(struct Stepper *motor, stepper_time_t delay) 00055 { 00056 stepper_tc_doPulse(motor->timer); 00057 stepper_tc_setDelay(motor->timer, delay); 00058 } 00059 00060 static void stepper_test_irq(struct Stepper *motor) 00061 { 00062 00063 stepper_test_irq_schedule(motor, 300); 00064 } 00065 /* 00066 * Test a timer couter driver 00067 */ 00068 void stepper_timer_test_prestepper(struct Stepper *local_motor, struct StepperConfig *local_cfg, int index) 00069 { 00070 local_cfg->pulse = 300; 00071 00072 local_motor->cfg = local_cfg; 00073 stepper_tc_init(index, &stepper_test_irq, local_motor); 00074 stepper_tc_irq_enable(local_motor->timer); 00075 } 00076 00077 00078 bool su = true; 00079 bool sub = true; 00080 uint16_t periodo_st0 = 100; 00081 uint16_t periodo_st1 = 233; 00082 00083 static void tc_irq(void) __attribute__ ((interrupt)); 00084 static void tc_irq(void) 00085 { 00086 uint32_t status_reg = TC2_SR & TC2_IMR; 00087 00088 if (status_reg & BV(TC_CPAS)) 00089 { 00090 TC2_CMR &= ~TC_ACPA_MASK; 00091 if (su) 00092 { 00093 TC2_CMR |= TC_ACPA_CLEAR_OUTPUT; 00094 TC2_RA += periodo_st0; 00095 } 00096 else 00097 { 00098 TC2_CMR |= TC_ACPA_SET_OUTPUT; 00099 TC2_RA += periodo_st1; 00100 } 00101 su = !su; 00102 } 00103 if (status_reg & BV(TC_CPBS)) 00104 { 00105 TC2_CMR &= ~TC_BCPB_MASK ; 00106 if (sub) 00107 { 00108 TC2_CMR |= TC_BCPB_CLEAR_OUTPUT; 00109 TC2_RB += periodo_st0; 00110 } 00111 else 00112 { 00113 TC2_CMR |= TC_BCPB_SET_OUTPUT; 00114 TC2_RB += periodo_st1; 00115 } 00116 sub = !sub; 00117 } 00118 /* Inform hw that we have served the IRQ */ 00119 AIC_EOICR = 0; 00120 } 00121 00122 /* 00123 * Test a timer couter hardware 00124 */ 00125 void stepper_timer_test_brute(void) 00126 { 00127 PIOA_PDR |= BV(26) | BV(27); 00128 PIOA_BSR |= BV(26) | BV(27); 00129 00130 // Power on TCLK0 00131 PMC_PCER |= BV(TC2_ID);// | BV(TC1_ID) | BV(TC2_ID); 00132 00133 TC_BCR = 1; 00134 TC_BMR |= TC_NONEXC2; 00135 00136 // Select waveform mode 00137 TC2_CMR = BV(TC_WAVE); 00138 00139 TC2_CMR |= TC_EEVT_XC2; 00140 TC2_CMR |= TC_WAVSEL_UP; 00141 TC2_CMR |= TC_CLKS_MCK8; 00142 00143 //Set waveform on TIOA and TIOB 00144 TC2_CMR |= TC_ACPA_SET_OUTPUT; 00145 TC2_CMR |= TC_BCPB_SET_OUTPUT; 00146 00147 00148 //Reset all comp_reg register 00149 TC2_RA = 0; 00150 TC2_RB = 0; 00151 00152 cpuflags_t flags; 00153 IRQ_SAVE_DISABLE(flags); 00154 00155 /* Set the vector. */ 00156 AIC_SVR(TC2_ID) = tc_irq; 00157 /* Initialize to edge triggered with defined priority. */ 00158 AIC_SMR(TC2_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED; 00159 /* Enable the USART IRQ */ 00160 AIC_IECR = BV(TC2_ID); 00161 00162 IRQ_RESTORE(flags); 00163 00164 // Disable all interrupt 00165 TC2_IDR = 0xFFFFFFFF; 00166 00167 //Enable interrupt on RA, RB 00168 TC2_IER = BV(TC_CPAS) | BV(TC_CPBS); 00169 00170 //Enable timer and trig it 00171 TC2_CCR = BV(TC_CLKEN) | BV(TC_SWTRG); 00172 } 00173 #endif 00174