BeRTOS
at91_pmc.h
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00001 
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 
00072 #ifndef AT91_PMC_H
00073 #define AT91_PMC_H
00074 
00076 /*\{*/
00077 #define PMC_SCER_OFF                0x00000000  ///< System clock enable register offset.
00078 #define PMC_SCER    (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))   ///< System clock enable register address.
00079 #define PMC_SCDR_OFF                0x00000004  ///< System clock disable register offset.
00080 #define PMC_SCDR    (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF)))   ///< System clock disable register address.
00081 #define PMC_SCSR_OFF                0x00000008  ///< System clock status register offset.
00082 #define PMC_SCSR    (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF)))   ///< System clock status register address.
00083 
00084 #define PMC_PCK                              0  ///< Processor clock.
00085 #define PMC_UDP                              7  ///< USB device port clock.
00086 #define PMC_PCK0                             8  ///< Programmable clock 0 output.
00087 #define PMC_PCK1                             9  ///< Programmable clock 1 output.
00088 #define PMC_PCK2                            10  ///< Programmable clock 2 output.
00089 /*\}*/
00090 
00092 /*\{*/
00093 #define PMC_PCER_OFF                0x00000010  ///< Peripheral clock enable register offset.
00094 #define PMC_PCER    (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF)))   ///< Peripheral clock enable register address.
00095 #define PMC_PCDR_OFF                0x00000014  ///< Peripheral clock disable register offset.
00096 #define PMC_PCDR    (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF)))   ///< Peripheral clock disable register address.
00097 #define PMC_PCSR_OFF                0x00000018  ///< Peripheral clock status register offset.
00098 #define PMC_PCSR    (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF)))   ///< Peripheral clock status register address.
00099 /*\}*/
00100 
00102 /*\{*/
00103 #define CKGR_MOR_OFF                0x00000020  ///< Main oscillator register offset.
00104 #define CKGR_MOR    (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF)))   ///< Main oscillator register address.
00105 
00106 #define CKGR_MOSCEN                          0  ///< Main oscillator enable.
00107 #define CKGR_OSCBYPASS                       1  ///< Main oscillator bypass.
00108 #define CKGR_OSCOUNT_MASK           0x0000FF00  ///< Main oscillator start-up time mask.
00109 #define CKGR_OSCOUNT_SHIFT                   8  ///< Main oscillator start-up time LSB.
00110 /*\}*/
00111 
00113 /*\{*/
00114 #define CKGR_MCFR_OFF               0x00000024  ///< Main clock frequency register offset.
00115 #define CKGR_MCFR   (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF)))  ///< Main clock frequency register address.
00116 
00117 #define CKGR_MAINF_MASK             0x0000FFFF  ///< Main clock frequency mask mask.
00118 #define CKGR_MAINRDY                        16  ///< Main clock ready.
00119 /*\}*/
00120 
00122 /*\{*/
00123 #define CKGR_PLLR_OFF               0x0000002C  ///< Clock generator PLL register offset.
00124 #define CKGR_PLLR   (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF)))  ///< Clock generator PLL register address.
00125 
00126 #define CKGR_DIV_MASK               0x000000FF  ///< Divider.
00127 #define CKGR_DIV_SHIFT                       0  ///< Least significant bit of the divider.
00128 #define CKGR_DIV_0                  0x00000000  ///< Divider output is 0.
00129 #define CKGR_DIV_BYPASS             0x00000001  ///< Divider is bypassed.
00130 #define CKGR_PLLCOUNT_MASK          0x00003F00  ///< PLL counter mask.
00131 #define CKGR_PLLCOUNT_SHIFT                  8  ///< PLL counter LSB.
00132 
00133 #define CKGR_OUT_MASK               0x0000C000  ///< PLL output frequency range.
00134 #define CKGR_OUT_0                  0x00000000  ///< Please refer to the PLL datasheet.
00135 #define CKGR_OUT_1                  0x00004000  ///< Please refer to the PLL datasheet.
00136 #define CKGR_OUT_2                  0x00008000  ///< Please refer to the PLL datasheet.
00137 #define CKGR_OUT_3                  0x0000C000  ///< Please refer to the PLL datasheet.
00138 #define CKGR_MUL_MASK               0x07FF0000  ///< PLL multiplier.
00139 #define CKGR_MUL_SHIFT                      16  ///< Least significant bit of the PLL multiplier.
00140 
00141 #define CKGR_USBDIV_MASK            0x30000000  ///< Divider for USB clocks.
00142 #define CKGR_USBDIV_1               0x00000000  ///< Divider output is PLL clock output.
00143 #define CKGR_USBDIV_2               0x10000000  ///< Divider output is PLL clock output divided by 2.
00144 #define CKGR_USBDIV_4               0x20000000  ///< Divider output is PLL clock output divided by 4.
00145 /*\}*/
00146 
00148 /*\{*/
00149 #define PMC_MCKR_OFF                0x00000030  ///< Master clock register offset.
00150 #define PMC_MCKR    (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF)))   ///< Master clock register address.
00151 
00152 #define PMC_PCKR0_OFF               0x00000040  ///< Programmable clock 0 register offset.
00153 #define PMC_PCKR0   (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF)))  ///< Programmable clock 0 register address.
00154 #define PMC_PCKR1_OFF               0x00000044  ///< Programmable clock 1 register offset.
00155 #define PMC_PCKR1   (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF)))  ///< Programmable clock 1 register address.
00156 #define PMC_PCKR2_OFF               0x00000048  ///< Programmable clock 2 register offset.
00157 #define PMC_PCKR2   (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF)))  ///< Programmable clock 2 register address.
00158 
00159 #define PMC_CSS_MASK                0x00000003  ///< Clock selection mask.
00160 #define PMC_CSS_SLOW_CLK            0x00000000  ///< Slow clock selected.
00161 #define PMC_CSS_MAIN_CLK            0x00000001  ///< Main clock selected.
00162 #define PMC_CSS_PLL_CLK             0x00000003  ///< PLL clock selected.
00163 
00164 #define PMC_PRES_MASK               0x0000001C  ///< Clock prescaler mask.
00165 #define PMC_PRES_SHIFT                       2   ///< Clock prescaler LSB.
00166 #define PMC_PRES_CLK                0x00000000  ///< Selected clock, not divided.
00167 #define PMC_PRES_CLK_2              0x00000004  ///< Selected clock divided by 2.
00168 #define PMC_PRES_CLK_4              0x00000008  ///< Selected clock divided by 4.
00169 #define PMC_PRES_CLK_8              0x0000000C  ///< Selected clock divided by 8.
00170 #define PMC_PRES_CLK_16             0x00000010  ///< Selected clock divided by 16.
00171 #define PMC_PRES_CLK_32             0x00000014  ///< Selected clock divided by 32.
00172 #define PMC_PRES_CLK_64             0x00000018  ///< Selected clock divided by 64.
00173 /*\}*/
00174 
00176 /*\{*/
00177 #define PMC_IER_OFF                 0x00000060  ///< Interrupt enable register offset.
00178 #define PMC_IER     (*((reg32_t *)(PMC_BASE + PMC_IER_OFF)))    ///< Interrupt enable register address.
00179 #define PMC_IDR_OFF                 0x00000064  ///< Interrupt disable register offset.
00180 #define PMC_IDR     (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF)))    ///< Interrupt disable register address.
00181 #define PMC_SR_OFF                  0x00000068  ///< Status register offset.
00182 #define PMC_SR      (*((reg32_t *)(PMC_BASE + PMC_SR_OFF)))     ///< Status register address.
00183 #define PMC_IMR_OFF                 0x0000006C  ///< Interrupt mask register offset.
00184 #define PMC_IMR     (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF)))    ///< Interrupt mask register address.
00185 
00186 #define PMC_MOSCS                            0  ///< Main oscillator.
00187 #define PMC_LOCK                             2  ///< PLL lock.
00188 #define PMC_MCKRDY                           3  ///< Master clock ready.
00189 #define PMC_PCKRDY0                          8  ///< Programmable clock 0 ready.
00190 #define PMC_PCKRDY1                          9  ///< Programmable clock 1 ready.
00191 #define PMC_PCKRDY2                         10  ///< Programmable clock 2 ready.
00192 /*\}*/
00193 
00194 #endif /* AT91_PMC_H */