BeRTOS
|
00001 00044 /* ---------------------------------------------------------------------------- */ 00045 /* Atmel Microcontroller Software Support */ 00046 /* ---------------------------------------------------------------------------- */ 00047 /* Copyright (c) 2010, Atmel Corporation */ 00048 /* */ 00049 /* All rights reserved. */ 00050 /* */ 00051 /* Redistribution and use in source and binary forms, with or without */ 00052 /* modification, are permitted provided that the following condition is met: */ 00053 /* */ 00054 /* - Redistributions of source code must retain the above copyright notice, */ 00055 /* this list of conditions and the disclaimer below. */ 00056 /* */ 00057 /* Atmel's name may not be used to endorse or promote products derived from */ 00058 /* this software without specific prior written permission. */ 00059 /* */ 00060 /* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */ 00061 /* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */ 00062 /* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */ 00063 /* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */ 00064 /* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */ 00065 /* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */ 00066 /* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */ 00067 /* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */ 00068 /* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ 00069 /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ 00070 /* ---------------------------------------------------------------------------- */ 00071 /* */ 00072 /* File Name : SAM3N.h */ 00073 /* Object : SAM3N definitions */ 00074 /* Generated by : AT91 SW Application Group */ 00075 /* Generated on : 2010-09-06 */ 00076 00077 #ifndef SAM3N_H 00078 #define SAM3N_H 00079 00080 /* SAM3N_definitions SAM3N definitions 00081 This file defines all structures and symbols for SAM3N: 00082 - registers and bitfields 00083 - peripheral base address 00084 - peripheral ID 00085 - PIO definitions 00086 */ 00087 00088 #ifdef __cplusplus 00089 extern "C" { 00090 #endif 00091 00092 #ifndef __ASSEMBLY__ 00093 #include <stdint.h> 00094 #ifndef __cplusplus 00095 typedef volatile const uint32_t RoReg; /* Read only 32-bit register (volatile const unsigned int) */ 00096 #else 00097 typedef volatile uint32_t RoReg; /* Read only 32-bit register (volatile const unsigned int) */ 00098 #endif 00099 typedef volatile uint32_t WoReg; /* Write only 32-bit register (volatile unsigned int) */ 00100 typedef volatile uint32_t RwReg; /* Read-Write 32-bit register (volatile unsigned int) */ 00101 #define CAST(type, value) ((type *) value) 00102 #define REG_ACCESS(type, address) (*(type*)address) /* C code: Register value */ 00103 #else 00104 #define CAST(type, value) (value) 00105 #define REG_ACCESS(type, address) (address) /* Assembly code: Register address */ 00106 #endif 00107 00108 /* ************************************************************************** */ 00109 /* CMSIS DEFINITIONS FOR SAM3N */ 00110 /* ************************************************************************** */ 00111 00112 /* Interrupt Number Definition */ 00113 typedef enum IRQn 00114 { 00115 /****** Cortex-M3 Processor Exceptions Numbers ******************************/ 00116 NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */ 00117 MemoryManagement_IRQn = -12, /* 4 Cortex-M3 Memory Management Interrupt */ 00118 BusFault_IRQn = -11, /* 5 Cortex-M3 Bus Fault Interrupt */ 00119 UsageFault_IRQn = -10, /* 6 Cortex-M3 Usage Fault Interrupt */ 00120 SVCall_IRQn = -5, /* 11 Cortex-M3 SV Call Interrupt */ 00121 DebugMonitor_IRQn = -4, /* 12 Cortex-M3 Debug Monitor Interrupt */ 00122 PendSV_IRQn = -2, /* 14 Cortex-M3 Pend SV Interrupt */ 00123 SysTick_IRQn = -1, /* 15 Cortex-M3 System Tick Interrupt */ 00124 /****** SAM3N specific Interrupt Numbers *********************************/ 00125 00126 SUPC_IRQn = 0, /* 0 SAM3N Supply Controller (SUPC) */ 00127 RSTC_IRQn = 1, /* 1 SAM3N Reset Controller (RSTC) */ 00128 RTC_IRQn = 2, /* 2 SAM3N Real Time Clock (RTC) */ 00129 RTT_IRQn = 3, /* 3 SAM3N Real Time Timer (RTT) */ 00130 WDT_IRQn = 4, /* 4 SAM3N Watchdog Timer (WDT) */ 00131 PMC_IRQn = 5, /* 5 SAM3N Power Management Controller (PMC) */ 00132 EFC_IRQn = 6, /* 6 SAM3N Enhanced Flash Controller (EFC) */ 00133 UART0_IRQn = 8, /* 8 SAM3N UART 0 (UART0) */ 00134 UART1_IRQn = 9, /* 9 SAM3N UART 1 (UART1) */ 00135 PIOA_IRQn = 11, /* 11 SAM3N Parallel I/O Controller A (PIOA) */ 00136 PIOB_IRQn = 12, /* 12 SAM3N Parallel I/O Controller B (PIOB) */ 00137 PIOC_IRQn = 13, /* 13 SAM3N Parallel I/O Controller C (PIOC) */ 00138 USART0_IRQn = 14, /* 14 SAM3N USART 0 (USART0) */ 00139 USART1_IRQn = 15, /* 15 SAM3N USART 1 (USART1) */ 00140 TWI0_IRQn = 19, /* 19 SAM3N Two Wire Interface 0 (TWI0) */ 00141 TWI1_IRQn = 20, /* 20 SAM3N Two Wire Interface 1 (TWI1) */ 00142 SPI_IRQn = 21, /* 21 SAM3N Serial Peripheral Interface (SPI) */ 00143 TC0_IRQn = 23, /* 23 SAM3N Timer/Counter 0 (TC0) */ 00144 TC1_IRQn = 24, /* 24 SAM3N Timer/Counter 1 (TC1) */ 00145 TC2_IRQn = 25, /* 25 SAM3N Timer/Counter 2 (TC2) */ 00146 TC3_IRQn = 26, /* 26 SAM3N Timer/Counter 3 (TC3) */ 00147 TC4_IRQn = 27, /* 27 SAM3N Timer/Counter 4 (TC4) */ 00148 TC5_IRQn = 28, /* 28 SAM3N Timer/Counter 5 (TC5) */ 00149 ADC_IRQn = 29, /* 29 SAM3N Analog To Digital Converter (ADC) */ 00150 DACC_IRQn = 30, /* 30 SAM3N Digital To Analog Converter (DACC) */ 00151 PWM_IRQn = 31 /* 31 SAM3N Pulse Width Modulation (PWM) */ 00152 } IRQn_Type; 00153 00154 /* 00155 * Configuration of the Cortex-M3 Processor and Core Peripherals 00156 */ 00157 00158 #define __MPU_PRESENT 0 /* $product does not provide a MPU */ 00159 #define __NVIC_PRIO_BITS 4 /* $product uses 4 Bits for the Priority Levels */ 00160 #define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ 00161 00162 00163 /* ************************************************************************** */ 00164 /* SOFTWARE PERIPHERAL API DEFINITION FOR SAM3N */ 00165 /* ************************************************************************** */ 00166 /* ============================================================================= */ 00167 /* SOFTWARE API DEFINITION FOR Analog-to-digital Converter */ 00168 /* ============================================================================= */ 00169 00170 #ifndef __ASSEMBLY__ 00171 /* Adc hardware registers */ 00172 typedef struct { 00173 WoReg ADC_CR; /* (Adc Offset: 0x00) Control Register */ 00174 RwReg ADC_MR; /* (Adc Offset: 0x04) Mode Register */ 00175 RwReg ADC_SEQR1; /* (Adc Offset: 0x08) Channel Sequence Register 1 */ 00176 RwReg ADC_SEQR2; /* (Adc Offset: 0x0C) Channel Sequence Register 2 */ 00177 WoReg ADC_CHER; /* (Adc Offset: 0x10) Channel Enable Register */ 00178 WoReg ADC_CHDR; /* (Adc Offset: 0x14) Channel Disable Register */ 00179 RoReg ADC_CHSR; /* (Adc Offset: 0x18) Channel Status Register */ 00180 RwReg Reserved1[1]; 00181 RoReg ADC_LCDR; /* (Adc Offset: 0x20) Last Converted Data Register */ 00182 WoReg ADC_IER; /* (Adc Offset: 0x24) Interrupt Enable Register */ 00183 WoReg ADC_IDR; /* (Adc Offset: 0x28) Interrupt Disable Register */ 00184 RoReg ADC_IMR; /* (Adc Offset: 0x2C) Interrupt Mask Register */ 00185 RoReg ADC_ISR; /* (Adc Offset: 0x30) Interrupt Status Register */ 00186 RwReg Reserved2[2]; 00187 RoReg ADC_OVER; /* (Adc Offset: 0x3C) Overrun Status Register */ 00188 RwReg ADC_EMR; /* (Adc Offset: 0x40) Extended Mode Register */ 00189 RwReg ADC_CWR; /* (Adc Offset: 0x44) Compare Window Register */ 00190 RwReg Reserved3[2]; 00191 RoReg ADC_CDR[16]; /* (Adc Offset: 0x50) Channel Data Register */ 00192 RwReg Reserved4[21]; 00193 RwReg ADC_WPMR; /* (Adc Offset: 0xE4) Write Protect Mode Register */ 00194 RoReg ADC_WPSR; /* (Adc Offset: 0xE8) Write Protect Status Register */ 00195 RwReg Reserved5[5]; 00196 RwReg ADC_RPR; /* (Adc Offset: 0x100) Receive Pointer Register */ 00197 RwReg ADC_RCR; /* (Adc Offset: 0x104) Receive Counter Register */ 00198 RwReg ADC_TPR; /* (Adc Offset: 0x108) Transmit Pointer Register */ 00199 RwReg ADC_TCR; /* (Adc Offset: 0x10C) Transmit Counter Register */ 00200 RwReg ADC_RNPR; /* (Adc Offset: 0x110) Receive Next Pointer Register */ 00201 RwReg ADC_RNCR; /* (Adc Offset: 0x114) Receive Next Counter Register */ 00202 RwReg ADC_TNPR; /* (Adc Offset: 0x118) Transmit Next Pointer Register */ 00203 RwReg ADC_TNCR; /* (Adc Offset: 0x11C) Transmit Next Counter Register */ 00204 WoReg ADC_PTCR; /* (Adc Offset: 0x120) Transfer Control Register */ 00205 RoReg ADC_PTSR; /* (Adc Offset: 0x124) Transfer Status Register */ 00206 } Adc; 00207 #endif /* __ASSEMBLY__ */ 00208 /* -------- ADC_CR : (ADC Offset: 0x00) Control Register -------- */ 00209 #define ADC_CR_SWRST (0x1u << 0) /* (ADC_CR) Software Reset */ 00210 #define ADC_CR_START (0x1u << 1) /* (ADC_CR) Start Conversion */ 00211 /* -------- ADC_MR : (ADC Offset: 0x04) Mode Register -------- */ 00212 #define ADC_MR_TRGEN (0x1u << 0) /* (ADC_MR) Trigger Enable */ 00213 #define ADC_MR_TRGEN_DIS (0x0u << 0) /* (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software. */ 00214 #define ADC_MR_TRGEN_EN (0x1u << 0) /* (ADC_MR) Hardware trigger selected by TRGSEL field is enabled. */ 00215 #define ADC_MR_TRGSEL_Pos 1 00216 #define ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) /* (ADC_MR) Trigger Selection */ 00217 #define ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) /* (ADC_MR) External trigger */ 00218 #define ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) /* (ADC_MR) TIO Output of the Timer Counter Channel 0 */ 00219 #define ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) /* (ADC_MR) TIO Output of the Timer Counter Channel 1 */ 00220 #define ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) /* (ADC_MR) TIO Output of the Timer Counter Channel 2 */ 00221 #define ADC_MR_LOWRES (0x1u << 4) /* (ADC_MR) Resolution */ 00222 #define ADC_MR_LOWRES_BITS_10 (0x0u << 4) /* (ADC_MR) 10-bit resolution */ 00223 #define ADC_MR_LOWRES_BITS_8 (0x1u << 4) /* (ADC_MR) 8-bit resolution */ 00224 #define ADC_MR_SLEEP (0x1u << 5) /* (ADC_MR) Sleep Mode */ 00225 #define ADC_MR_SLEEP_NORMAL (0x0u << 5) /* (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions */ 00226 #define ADC_MR_SLEEP_SLEEP (0x1u << 5) /* (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions */ 00227 #define ADC_MR_FWUP (0x1u << 6) /* (ADC_MR) Fast Wake Up */ 00228 #define ADC_MR_FWUP_OFF (0x0u << 6) /* (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit */ 00229 #define ADC_MR_FWUP_ON (0x1u << 6) /* (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF */ 00230 #define ADC_MR_FREERUN (0x1u << 7) /* (ADC_MR) Free Run Mode */ 00231 #define ADC_MR_FREERUN_OFF (0x0u << 7) /* (ADC_MR) Normal Mode */ 00232 #define ADC_MR_FREERUN_ON (0x1u << 7) /* (ADC_MR) Free Run Mode: Never wait for any trigger. */ 00233 #define ADC_MR_PRESCAL_Pos 8 00234 #define ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) /* (ADC_MR) Prescaler Rate Selection */ 00235 #define ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) 00236 #define ADC_MR_STARTUP_Pos 16 00237 #define ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) /* (ADC_MR) Start Up Time */ 00238 #define ADC_MR_STARTUP_SUT0 (0x0u << 16) /* (ADC_MR) 0 periods of ADCClock */ 00239 #define ADC_MR_STARTUP_SUT8 (0x1u << 16) /* (ADC_MR) 8 periods of ADCClock */ 00240 #define ADC_MR_STARTUP_SUT16 (0x2u << 16) /* (ADC_MR) 16 periods of ADCClock */ 00241 #define ADC_MR_STARTUP_SUT24 (0x3u << 16) /* (ADC_MR) 24 periods of ADCClock */ 00242 #define ADC_MR_STARTUP_SUT64 (0x4u << 16) /* (ADC_MR) 64 periods of ADCClock */ 00243 #define ADC_MR_STARTUP_SUT80 (0x5u << 16) /* (ADC_MR) 80 periods of ADCClock */ 00244 #define ADC_MR_STARTUP_SUT96 (0x6u << 16) /* (ADC_MR) 96 periods of ADCClock */ 00245 #define ADC_MR_STARTUP_SUT112 (0x7u << 16) /* (ADC_MR) 112 periods of ADCClock */ 00246 #define ADC_MR_STARTUP_SUT512 (0x8u << 16) /* (ADC_MR) 512 periods of ADCClock */ 00247 #define ADC_MR_STARTUP_SUT576 (0x9u << 16) /* (ADC_MR) 576 periods of ADCClock */ 00248 #define ADC_MR_STARTUP_SUT640 (0xAu << 16) /* (ADC_MR) 640 periods of ADCClock */ 00249 #define ADC_MR_STARTUP_SUT704 (0xBu << 16) /* (ADC_MR) 704 periods of ADCClock */ 00250 #define ADC_MR_STARTUP_SUT768 (0xCu << 16) /* (ADC_MR) 768 periods of ADCClock */ 00251 #define ADC_MR_STARTUP_SUT832 (0xDu << 16) /* (ADC_MR) 832 periods of ADCClock */ 00252 #define ADC_MR_STARTUP_SUT896 (0xEu << 16) /* (ADC_MR) 896 periods of ADCClock */ 00253 #define ADC_MR_STARTUP_SUT960 (0xFu << 16) /* (ADC_MR) 960 periods of ADCClock */ 00254 #define ADC_MR_TRACKTIM_Pos 24 00255 #define ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) /* (ADC_MR) Tracking Time */ 00256 #define ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) 00257 #define ADC_MR_USEQ (0x1u << 31) /* (ADC_MR) Use Sequence Enable */ 00258 #define ADC_MR_USEQ_NUM_ORDER (0x0u << 31) /* (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order. */ 00259 #define ADC_MR_USEQ_REG_ORDER (0x1u << 31) /* (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers. */ 00260 /* -------- ADC_SEQR1 : (ADC Offset: 0x08) Channel Sequence Register 1 -------- */ 00261 #define ADC_SEQR1_USCH1_Pos 0 00262 #define ADC_SEQR1_USCH1_Msk (0xfu << ADC_SEQR1_USCH1_Pos) /* (ADC_SEQR1) User Sequence Number 1 */ 00263 #define ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) 00264 #define ADC_SEQR1_USCH2_Pos 4 00265 #define ADC_SEQR1_USCH2_Msk (0xfu << ADC_SEQR1_USCH2_Pos) /* (ADC_SEQR1) User Sequence Number 2 */ 00266 #define ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) 00267 #define ADC_SEQR1_USCH3_Pos 8 00268 #define ADC_SEQR1_USCH3_Msk (0xfu << ADC_SEQR1_USCH3_Pos) /* (ADC_SEQR1) User Sequence Number 3 */ 00269 #define ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) 00270 #define ADC_SEQR1_USCH4_Pos 12 00271 #define ADC_SEQR1_USCH4_Msk (0xfu << ADC_SEQR1_USCH4_Pos) /* (ADC_SEQR1) User Sequence Number 4 */ 00272 #define ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) 00273 #define ADC_SEQR1_USCH5_Pos 16 00274 #define ADC_SEQR1_USCH5_Msk (0xfu << ADC_SEQR1_USCH5_Pos) /* (ADC_SEQR1) User Sequence Number 5 */ 00275 #define ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) 00276 #define ADC_SEQR1_USCH6_Pos 20 00277 #define ADC_SEQR1_USCH6_Msk (0xfu << ADC_SEQR1_USCH6_Pos) /* (ADC_SEQR1) User Sequence Number 6 */ 00278 #define ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) 00279 #define ADC_SEQR1_USCH7_Pos 24 00280 #define ADC_SEQR1_USCH7_Msk (0xfu << ADC_SEQR1_USCH7_Pos) /* (ADC_SEQR1) User Sequence Number 7 */ 00281 #define ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) 00282 #define ADC_SEQR1_USCH8_Pos 28 00283 #define ADC_SEQR1_USCH8_Msk (0xfu << ADC_SEQR1_USCH8_Pos) /* (ADC_SEQR1) User Sequence Number 8 */ 00284 #define ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) 00285 /* -------- ADC_SEQR2 : (ADC Offset: 0x0C) Channel Sequence Register 2 -------- */ 00286 #define ADC_SEQR2_USCH9_Pos 0 00287 #define ADC_SEQR2_USCH9_Msk (0xfu << ADC_SEQR2_USCH9_Pos) /* (ADC_SEQR2) User Sequence Number 9 */ 00288 #define ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) 00289 #define ADC_SEQR2_USCH10_Pos 4 00290 #define ADC_SEQR2_USCH10_Msk (0xfu << ADC_SEQR2_USCH10_Pos) /* (ADC_SEQR2) User Sequence Number 10 */ 00291 #define ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) 00292 #define ADC_SEQR2_USCH11_Pos 8 00293 #define ADC_SEQR2_USCH11_Msk (0xfu << ADC_SEQR2_USCH11_Pos) /* (ADC_SEQR2) User Sequence Number 11 */ 00294 #define ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) 00295 #define ADC_SEQR2_USCH12_Pos 12 00296 #define ADC_SEQR2_USCH12_Msk (0xfu << ADC_SEQR2_USCH12_Pos) /* (ADC_SEQR2) User Sequence Number 12 */ 00297 #define ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) 00298 #define ADC_SEQR2_USCH13_Pos 16 00299 #define ADC_SEQR2_USCH13_Msk (0xfu << ADC_SEQR2_USCH13_Pos) /* (ADC_SEQR2) User Sequence Number 13 */ 00300 #define ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) 00301 #define ADC_SEQR2_USCH14_Pos 20 00302 #define ADC_SEQR2_USCH14_Msk (0xfu << ADC_SEQR2_USCH14_Pos) /* (ADC_SEQR2) User Sequence Number 14 */ 00303 #define ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) 00304 #define ADC_SEQR2_USCH15_Pos 24 00305 #define ADC_SEQR2_USCH15_Msk (0xfu << ADC_SEQR2_USCH15_Pos) /* (ADC_SEQR2) User Sequence Number 15 */ 00306 #define ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) 00307 #define ADC_SEQR2_USCH16_Pos 28 00308 #define ADC_SEQR2_USCH16_Msk (0xfu << ADC_SEQR2_USCH16_Pos) /* (ADC_SEQR2) User Sequence Number 16 */ 00309 #define ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) 00310 /* -------- ADC_CHER : (ADC Offset: 0x10) Channel Enable Register -------- */ 00311 #define ADC_CHER_CH0 (0x1u << 0) /* (ADC_CHER) Channel 0 Enable */ 00312 #define ADC_CHER_CH1 (0x1u << 1) /* (ADC_CHER) Channel 1 Enable */ 00313 #define ADC_CHER_CH2 (0x1u << 2) /* (ADC_CHER) Channel 2 Enable */ 00314 #define ADC_CHER_CH3 (0x1u << 3) /* (ADC_CHER) Channel 3 Enable */ 00315 #define ADC_CHER_CH4 (0x1u << 4) /* (ADC_CHER) Channel 4 Enable */ 00316 #define ADC_CHER_CH5 (0x1u << 5) /* (ADC_CHER) Channel 5 Enable */ 00317 #define ADC_CHER_CH6 (0x1u << 6) /* (ADC_CHER) Channel 6 Enable */ 00318 #define ADC_CHER_CH7 (0x1u << 7) /* (ADC_CHER) Channel 7 Enable */ 00319 #define ADC_CHER_CH8 (0x1u << 8) /* (ADC_CHER) Channel 8 Enable */ 00320 #define ADC_CHER_CH9 (0x1u << 9) /* (ADC_CHER) Channel 9 Enable */ 00321 #define ADC_CHER_CH10 (0x1u << 10) /* (ADC_CHER) Channel 10 Enable */ 00322 #define ADC_CHER_CH11 (0x1u << 11) /* (ADC_CHER) Channel 11 Enable */ 00323 #define ADC_CHER_CH12 (0x1u << 12) /* (ADC_CHER) Channel 12 Enable */ 00324 #define ADC_CHER_CH13 (0x1u << 13) /* (ADC_CHER) Channel 13 Enable */ 00325 #define ADC_CHER_CH14 (0x1u << 14) /* (ADC_CHER) Channel 14 Enable */ 00326 #define ADC_CHER_CH15 (0x1u << 15) /* (ADC_CHER) Channel 15 Enable */ 00327 /* -------- ADC_CHDR : (ADC Offset: 0x14) Channel Disable Register -------- */ 00328 #define ADC_CHDR_CH0 (0x1u << 0) /* (ADC_CHDR) Channel 0 Disable */ 00329 #define ADC_CHDR_CH1 (0x1u << 1) /* (ADC_CHDR) Channel 1 Disable */ 00330 #define ADC_CHDR_CH2 (0x1u << 2) /* (ADC_CHDR) Channel 2 Disable */ 00331 #define ADC_CHDR_CH3 (0x1u << 3) /* (ADC_CHDR) Channel 3 Disable */ 00332 #define ADC_CHDR_CH4 (0x1u << 4) /* (ADC_CHDR) Channel 4 Disable */ 00333 #define ADC_CHDR_CH5 (0x1u << 5) /* (ADC_CHDR) Channel 5 Disable */ 00334 #define ADC_CHDR_CH6 (0x1u << 6) /* (ADC_CHDR) Channel 6 Disable */ 00335 #define ADC_CHDR_CH7 (0x1u << 7) /* (ADC_CHDR) Channel 7 Disable */ 00336 #define ADC_CHDR_CH8 (0x1u << 8) /* (ADC_CHDR) Channel 8 Disable */ 00337 #define ADC_CHDR_CH9 (0x1u << 9) /* (ADC_CHDR) Channel 9 Disable */ 00338 #define ADC_CHDR_CH10 (0x1u << 10) /* (ADC_CHDR) Channel 10 Disable */ 00339 #define ADC_CHDR_CH11 (0x1u << 11) /* (ADC_CHDR) Channel 11 Disable */ 00340 #define ADC_CHDR_CH12 (0x1u << 12) /* (ADC_CHDR) Channel 12 Disable */ 00341 #define ADC_CHDR_CH13 (0x1u << 13) /* (ADC_CHDR) Channel 13 Disable */ 00342 #define ADC_CHDR_CH14 (0x1u << 14) /* (ADC_CHDR) Channel 14 Disable */ 00343 #define ADC_CHDR_CH15 (0x1u << 15) /* (ADC_CHDR) Channel 15 Disable */ 00344 /* -------- ADC_CHSR : (ADC Offset: 0x18) Channel Status Register -------- */ 00345 #define ADC_CHSR_CH0 (0x1u << 0) /* (ADC_CHSR) Channel 0 Status */ 00346 #define ADC_CHSR_CH1 (0x1u << 1) /* (ADC_CHSR) Channel 1 Status */ 00347 #define ADC_CHSR_CH2 (0x1u << 2) /* (ADC_CHSR) Channel 2 Status */ 00348 #define ADC_CHSR_CH3 (0x1u << 3) /* (ADC_CHSR) Channel 3 Status */ 00349 #define ADC_CHSR_CH4 (0x1u << 4) /* (ADC_CHSR) Channel 4 Status */ 00350 #define ADC_CHSR_CH5 (0x1u << 5) /* (ADC_CHSR) Channel 5 Status */ 00351 #define ADC_CHSR_CH6 (0x1u << 6) /* (ADC_CHSR) Channel 6 Status */ 00352 #define ADC_CHSR_CH7 (0x1u << 7) /* (ADC_CHSR) Channel 7 Status */ 00353 #define ADC_CHSR_CH8 (0x1u << 8) /* (ADC_CHSR) Channel 8 Status */ 00354 #define ADC_CHSR_CH9 (0x1u << 9) /* (ADC_CHSR) Channel 9 Status */ 00355 #define ADC_CHSR_CH10 (0x1u << 10) /* (ADC_CHSR) Channel 10 Status */ 00356 #define ADC_CHSR_CH11 (0x1u << 11) /* (ADC_CHSR) Channel 11 Status */ 00357 #define ADC_CHSR_CH12 (0x1u << 12) /* (ADC_CHSR) Channel 12 Status */ 00358 #define ADC_CHSR_CH13 (0x1u << 13) /* (ADC_CHSR) Channel 13 Status */ 00359 #define ADC_CHSR_CH14 (0x1u << 14) /* (ADC_CHSR) Channel 14 Status */ 00360 #define ADC_CHSR_CH15 (0x1u << 15) /* (ADC_CHSR) Channel 15 Status */ 00361 /* -------- ADC_LCDR : (ADC Offset: 0x20) Last Converted Data Register -------- */ 00362 #define ADC_LCDR_LDATA_Pos 0 00363 #define ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) /* (ADC_LCDR) Last Data Converted */ 00364 #define ADC_LCDR_CHNB_Pos 12 00365 #define ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) /* (ADC_LCDR) Channel Number */ 00366 /* -------- ADC_IER : (ADC Offset: 0x24) Interrupt Enable Register -------- */ 00367 #define ADC_IER_EOC0 (0x1u << 0) /* (ADC_IER) End of Conversion Interrupt Enable 0 */ 00368 #define ADC_IER_EOC1 (0x1u << 1) /* (ADC_IER) End of Conversion Interrupt Enable 1 */ 00369 #define ADC_IER_EOC2 (0x1u << 2) /* (ADC_IER) End of Conversion Interrupt Enable 2 */ 00370 #define ADC_IER_EOC3 (0x1u << 3) /* (ADC_IER) End of Conversion Interrupt Enable 3 */ 00371 #define ADC_IER_EOC4 (0x1u << 4) /* (ADC_IER) End of Conversion Interrupt Enable 4 */ 00372 #define ADC_IER_EOC5 (0x1u << 5) /* (ADC_IER) End of Conversion Interrupt Enable 5 */ 00373 #define ADC_IER_EOC6 (0x1u << 6) /* (ADC_IER) End of Conversion Interrupt Enable 6 */ 00374 #define ADC_IER_EOC7 (0x1u << 7) /* (ADC_IER) End of Conversion Interrupt Enable 7 */ 00375 #define ADC_IER_EOC8 (0x1u << 8) /* (ADC_IER) End of Conversion Interrupt Enable 8 */ 00376 #define ADC_IER_EOC9 (0x1u << 9) /* (ADC_IER) End of Conversion Interrupt Enable 9 */ 00377 #define ADC_IER_EOC10 (0x1u << 10) /* (ADC_IER) End of Conversion Interrupt Enable 10 */ 00378 #define ADC_IER_EOC11 (0x1u << 11) /* (ADC_IER) End of Conversion Interrupt Enable 11 */ 00379 #define ADC_IER_EOC12 (0x1u << 12) /* (ADC_IER) End of Conversion Interrupt Enable 12 */ 00380 #define ADC_IER_EOC13 (0x1u << 13) /* (ADC_IER) End of Conversion Interrupt Enable 13 */ 00381 #define ADC_IER_EOC14 (0x1u << 14) /* (ADC_IER) End of Conversion Interrupt Enable 14 */ 00382 #define ADC_IER_EOC15 (0x1u << 15) /* (ADC_IER) End of Conversion Interrupt Enable 15 */ 00383 #define ADC_IER_DRDY (0x1u << 24) /* (ADC_IER) Data Ready Interrupt Enable */ 00384 #define ADC_IER_GOVRE (0x1u << 25) /* (ADC_IER) General Overrun Error Interrupt Enable */ 00385 #define ADC_IER_COMPE (0x1u << 26) /* (ADC_IER) Comparison Event Interrupt Enable */ 00386 #define ADC_IER_ENDRX (0x1u << 27) /* (ADC_IER) End of Receive Buffer Interrupt Enable */ 00387 #define ADC_IER_RXBUFF (0x1u << 28) /* (ADC_IER) Receive Buffer Full Interrupt Enable */ 00388 /* -------- ADC_IDR : (ADC Offset: 0x28) Interrupt Disable Register -------- */ 00389 #define ADC_IDR_EOC0 (0x1u << 0) /* (ADC_IDR) End of Conversion Interrupt Disable 0 */ 00390 #define ADC_IDR_EOC1 (0x1u << 1) /* (ADC_IDR) End of Conversion Interrupt Disable 1 */ 00391 #define ADC_IDR_EOC2 (0x1u << 2) /* (ADC_IDR) End of Conversion Interrupt Disable 2 */ 00392 #define ADC_IDR_EOC3 (0x1u << 3) /* (ADC_IDR) End of Conversion Interrupt Disable 3 */ 00393 #define ADC_IDR_EOC4 (0x1u << 4) /* (ADC_IDR) End of Conversion Interrupt Disable 4 */ 00394 #define ADC_IDR_EOC5 (0x1u << 5) /* (ADC_IDR) End of Conversion Interrupt Disable 5 */ 00395 #define ADC_IDR_EOC6 (0x1u << 6) /* (ADC_IDR) End of Conversion Interrupt Disable 6 */ 00396 #define ADC_IDR_EOC7 (0x1u << 7) /* (ADC_IDR) End of Conversion Interrupt Disable 7 */ 00397 #define ADC_IDR_EOC8 (0x1u << 8) /* (ADC_IDR) End of Conversion Interrupt Disable 8 */ 00398 #define ADC_IDR_EOC9 (0x1u << 9) /* (ADC_IDR) End of Conversion Interrupt Disable 9 */ 00399 #define ADC_IDR_EOC10 (0x1u << 10) /* (ADC_IDR) End of Conversion Interrupt Disable 10 */ 00400 #define ADC_IDR_EOC11 (0x1u << 11) /* (ADC_IDR) End of Conversion Interrupt Disable 11 */ 00401 #define ADC_IDR_EOC12 (0x1u << 12) /* (ADC_IDR) End of Conversion Interrupt Disable 12 */ 00402 #define ADC_IDR_EOC13 (0x1u << 13) /* (ADC_IDR) End of Conversion Interrupt Disable 13 */ 00403 #define ADC_IDR_EOC14 (0x1u << 14) /* (ADC_IDR) End of Conversion Interrupt Disable 14 */ 00404 #define ADC_IDR_EOC15 (0x1u << 15) /* (ADC_IDR) End of Conversion Interrupt Disable 15 */ 00405 #define ADC_IDR_DRDY (0x1u << 24) /* (ADC_IDR) Data Ready Interrupt Disable */ 00406 #define ADC_IDR_GOVRE (0x1u << 25) /* (ADC_IDR) General Overrun Error Interrupt Disable */ 00407 #define ADC_IDR_COMPE (0x1u << 26) /* (ADC_IDR) Comparison Event Interrupt Disable */ 00408 #define ADC_IDR_ENDRX (0x1u << 27) /* (ADC_IDR) End of Receive Buffer Interrupt Disable */ 00409 #define ADC_IDR_RXBUFF (0x1u << 28) /* (ADC_IDR) Receive Buffer Full Interrupt Disable */ 00410 /* -------- ADC_IMR : (ADC Offset: 0x2C) Interrupt Mask Register -------- */ 00411 #define ADC_IMR_EOC0 (0x1u << 0) /* (ADC_IMR) End of Conversion Interrupt Mask 0 */ 00412 #define ADC_IMR_EOC1 (0x1u << 1) /* (ADC_IMR) End of Conversion Interrupt Mask 1 */ 00413 #define ADC_IMR_EOC2 (0x1u << 2) /* (ADC_IMR) End of Conversion Interrupt Mask 2 */ 00414 #define ADC_IMR_EOC3 (0x1u << 3) /* (ADC_IMR) End of Conversion Interrupt Mask 3 */ 00415 #define ADC_IMR_EOC4 (0x1u << 4) /* (ADC_IMR) End of Conversion Interrupt Mask 4 */ 00416 #define ADC_IMR_EOC5 (0x1u << 5) /* (ADC_IMR) End of Conversion Interrupt Mask 5 */ 00417 #define ADC_IMR_EOC6 (0x1u << 6) /* (ADC_IMR) End of Conversion Interrupt Mask 6 */ 00418 #define ADC_IMR_EOC7 (0x1u << 7) /* (ADC_IMR) End of Conversion Interrupt Mask 7 */ 00419 #define ADC_IMR_EOC8 (0x1u << 8) /* (ADC_IMR) End of Conversion Interrupt Mask 8 */ 00420 #define ADC_IMR_EOC9 (0x1u << 9) /* (ADC_IMR) End of Conversion Interrupt Mask 9 */ 00421 #define ADC_IMR_EOC10 (0x1u << 10) /* (ADC_IMR) End of Conversion Interrupt Mask 10 */ 00422 #define ADC_IMR_EOC11 (0x1u << 11) /* (ADC_IMR) End of Conversion Interrupt Mask 11 */ 00423 #define ADC_IMR_EOC12 (0x1u << 12) /* (ADC_IMR) End of Conversion Interrupt Mask 12 */ 00424 #define ADC_IMR_EOC13 (0x1u << 13) /* (ADC_IMR) End of Conversion Interrupt Mask 13 */ 00425 #define ADC_IMR_EOC14 (0x1u << 14) /* (ADC_IMR) End of Conversion Interrupt Mask 14 */ 00426 #define ADC_IMR_EOC15 (0x1u << 15) /* (ADC_IMR) End of Conversion Interrupt Mask 15 */ 00427 #define ADC_IMR_DRDY (0x1u << 24) /* (ADC_IMR) Data Ready Interrupt Mask */ 00428 #define ADC_IMR_GOVRE (0x1u << 25) /* (ADC_IMR) General Overrun Error Interrupt Mask */ 00429 #define ADC_IMR_COMPE (0x1u << 26) /* (ADC_IMR) Comparison Event Interrupt Mask */ 00430 #define ADC_IMR_ENDRX (0x1u << 27) /* (ADC_IMR) End of Receive Buffer Interrupt Mask */ 00431 #define ADC_IMR_RXBUFF (0x1u << 28) /* (ADC_IMR) Receive Buffer Full Interrupt Mask */ 00432 /* -------- ADC_ISR : (ADC Offset: 0x30) Interrupt Status Register -------- */ 00433 #define ADC_ISR_EOC0 (0x1u << 0) /* (ADC_ISR) End of Conversion 0 */ 00434 #define ADC_ISR_EOC1 (0x1u << 1) /* (ADC_ISR) End of Conversion 1 */ 00435 #define ADC_ISR_EOC2 (0x1u << 2) /* (ADC_ISR) End of Conversion 2 */ 00436 #define ADC_ISR_EOC3 (0x1u << 3) /* (ADC_ISR) End of Conversion 3 */ 00437 #define ADC_ISR_EOC4 (0x1u << 4) /* (ADC_ISR) End of Conversion 4 */ 00438 #define ADC_ISR_EOC5 (0x1u << 5) /* (ADC_ISR) End of Conversion 5 */ 00439 #define ADC_ISR_EOC6 (0x1u << 6) /* (ADC_ISR) End of Conversion 6 */ 00440 #define ADC_ISR_EOC7 (0x1u << 7) /* (ADC_ISR) End of Conversion 7 */ 00441 #define ADC_ISR_EOC8 (0x1u << 8) /* (ADC_ISR) End of Conversion 8 */ 00442 #define ADC_ISR_EOC9 (0x1u << 9) /* (ADC_ISR) End of Conversion 9 */ 00443 #define ADC_ISR_EOC10 (0x1u << 10) /* (ADC_ISR) End of Conversion 10 */ 00444 #define ADC_ISR_EOC11 (0x1u << 11) /* (ADC_ISR) End of Conversion 11 */ 00445 #define ADC_ISR_EOC12 (0x1u << 12) /* (ADC_ISR) End of Conversion 12 */ 00446 #define ADC_ISR_EOC13 (0x1u << 13) /* (ADC_ISR) End of Conversion 13 */ 00447 #define ADC_ISR_EOC14 (0x1u << 14) /* (ADC_ISR) End of Conversion 14 */ 00448 #define ADC_ISR_EOC15 (0x1u << 15) /* (ADC_ISR) End of Conversion 15 */ 00449 #define ADC_ISR_DRDY (0x1u << 24) /* (ADC_ISR) Data Ready */ 00450 #define ADC_ISR_GOVRE (0x1u << 25) /* (ADC_ISR) General Overrun Error */ 00451 #define ADC_ISR_COMPE (0x1u << 26) /* (ADC_ISR) Comparison Error */ 00452 #define ADC_ISR_ENDRX (0x1u << 27) /* (ADC_ISR) End of RX Buffer */ 00453 #define ADC_ISR_RXBUFF (0x1u << 28) /* (ADC_ISR) RX Buffer Full */ 00454 /* -------- ADC_OVER : (ADC Offset: 0x3C) Overrun Status Register -------- */ 00455 #define ADC_OVER_OVRE0 (0x1u << 0) /* (ADC_OVER) Overrun Error 0 */ 00456 #define ADC_OVER_OVRE1 (0x1u << 1) /* (ADC_OVER) Overrun Error 1 */ 00457 #define ADC_OVER_OVRE2 (0x1u << 2) /* (ADC_OVER) Overrun Error 2 */ 00458 #define ADC_OVER_OVRE3 (0x1u << 3) /* (ADC_OVER) Overrun Error 3 */ 00459 #define ADC_OVER_OVRE4 (0x1u << 4) /* (ADC_OVER) Overrun Error 4 */ 00460 #define ADC_OVER_OVRE5 (0x1u << 5) /* (ADC_OVER) Overrun Error 5 */ 00461 #define ADC_OVER_OVRE6 (0x1u << 6) /* (ADC_OVER) Overrun Error 6 */ 00462 #define ADC_OVER_OVRE7 (0x1u << 7) /* (ADC_OVER) Overrun Error 7 */ 00463 #define ADC_OVER_OVRE8 (0x1u << 8) /* (ADC_OVER) Overrun Error 8 */ 00464 #define ADC_OVER_OVRE9 (0x1u << 9) /* (ADC_OVER) Overrun Error 9 */ 00465 #define ADC_OVER_OVRE10 (0x1u << 10) /* (ADC_OVER) Overrun Error 10 */ 00466 #define ADC_OVER_OVRE11 (0x1u << 11) /* (ADC_OVER) Overrun Error 11 */ 00467 #define ADC_OVER_OVRE12 (0x1u << 12) /* (ADC_OVER) Overrun Error 12 */ 00468 #define ADC_OVER_OVRE13 (0x1u << 13) /* (ADC_OVER) Overrun Error 13 */ 00469 #define ADC_OVER_OVRE14 (0x1u << 14) /* (ADC_OVER) Overrun Error 14 */ 00470 #define ADC_OVER_OVRE15 (0x1u << 15) /* (ADC_OVER) Overrun Error 15 */ 00471 /* -------- ADC_EMR : (ADC Offset: 0x40) Extended Mode Register -------- */ 00472 #define ADC_EMR_CMPMODE_Pos 0 00473 #define ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) /* (ADC_EMR) Comparison Mode */ 00474 #define ADC_EMR_CMPMODE_LOW (0x0u << 0) /* (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window. */ 00475 #define ADC_EMR_CMPMODE_HIGH (0x1u << 0) /* (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window. */ 00476 #define ADC_EMR_CMPMODE_IN (0x2u << 0) /* (ADC_EMR) Generates an event when the converted data is in the comparison window. */ 00477 #define ADC_EMR_CMPMODE_OUT (0x3u << 0) /* (ADC_EMR) Generates an event when the converted data is out of the comparison window. */ 00478 #define ADC_EMR_CMPSEL_Pos 4 00479 #define ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) /* (ADC_EMR) Comparison Selected Channel */ 00480 #define ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) 00481 #define ADC_EMR_CMPALL (0x1u << 9) /* (ADC_EMR) Compare All Channels */ 00482 #define ADC_EMR_TAG (0x1u << 24) /* (ADC_EMR) TAG of ADC_LDCR register */ 00483 /* -------- ADC_CWR : (ADC Offset: 0x44) Compare Window Register -------- */ 00484 #define ADC_CWR_LOWTHRES_Pos 0 00485 #define ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) /* (ADC_CWR) Low Threshold */ 00486 #define ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) 00487 #define ADC_CWR_HIGHTHRES_Pos 16 00488 #define ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) /* (ADC_CWR) High Threshold */ 00489 #define ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) 00490 /* -------- ADC_CDR[16] : (ADC Offset: 0x50) Channel Data Register -------- */ 00491 #define ADC_CDR_DATA_Pos 0 00492 #define ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) /* (ADC_CDR[16]) Converted Data */ 00493 /* -------- ADC_WPMR : (ADC Offset: 0xE4) Write Protect Mode Register -------- */ 00494 #define ADC_WPMR_WPEN (0x1u << 0) /* (ADC_WPMR) Write Protect Enable */ 00495 #define ADC_WPMR_WPKEY_Pos 8 00496 #define ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) /* (ADC_WPMR) Write Protect KEY */ 00497 #define ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) 00498 /* -------- ADC_WPSR : (ADC Offset: 0xE8) Write Protect Status Register -------- */ 00499 #define ADC_WPSR_WPVS (0x1u << 0) /* (ADC_WPSR) Write Protect Violation Status */ 00500 #define ADC_WPSR_WPVSRC_Pos 8 00501 #define ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) /* (ADC_WPSR) Write Protect Violation Source */ 00502 /* -------- ADC_RPR : (ADC Offset: 0x100) Receive Pointer Register -------- */ 00503 #define ADC_RPR_RXPTR_Pos 0 00504 #define ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) /* (ADC_RPR) Receive Pointer Register */ 00505 #define ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) 00506 /* -------- ADC_RCR : (ADC Offset: 0x104) Receive Counter Register -------- */ 00507 #define ADC_RCR_RXCTR_Pos 0 00508 #define ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) /* (ADC_RCR) Receive Counter Register */ 00509 #define ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) 00510 /* -------- ADC_TPR : (ADC Offset: 0x108) Transmit Pointer Register -------- */ 00511 #define ADC_TPR_TXPTR_Pos 0 00512 #define ADC_TPR_TXPTR_Msk (0xffffffffu << ADC_TPR_TXPTR_Pos) /* (ADC_TPR) Transmit Counter Register */ 00513 #define ADC_TPR_TXPTR(value) ((ADC_TPR_TXPTR_Msk & ((value) << ADC_TPR_TXPTR_Pos))) 00514 /* -------- ADC_TCR : (ADC Offset: 0x10C) Transmit Counter Register -------- */ 00515 #define ADC_TCR_TXCTR_Pos 0 00516 #define ADC_TCR_TXCTR_Msk (0xffffu << ADC_TCR_TXCTR_Pos) /* (ADC_TCR) Transmit Counter Register */ 00517 #define ADC_TCR_TXCTR(value) ((ADC_TCR_TXCTR_Msk & ((value) << ADC_TCR_TXCTR_Pos))) 00518 /* -------- ADC_RNPR : (ADC Offset: 0x110) Receive Next Pointer Register -------- */ 00519 #define ADC_RNPR_RXNPTR_Pos 0 00520 #define ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) /* (ADC_RNPR) Receive Next Pointer */ 00521 #define ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) 00522 /* -------- ADC_RNCR : (ADC Offset: 0x114) Receive Next Counter Register -------- */ 00523 #define ADC_RNCR_RXNCTR_Pos 0 00524 #define ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) /* (ADC_RNCR) Receive Next Counter */ 00525 #define ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) 00526 /* -------- ADC_TNPR : (ADC Offset: 0x118) Transmit Next Pointer Register -------- */ 00527 #define ADC_TNPR_TXNPTR_Pos 0 00528 #define ADC_TNPR_TXNPTR_Msk (0xffffffffu << ADC_TNPR_TXNPTR_Pos) /* (ADC_TNPR) Transmit Next Pointer */ 00529 #define ADC_TNPR_TXNPTR(value) ((ADC_TNPR_TXNPTR_Msk & ((value) << ADC_TNPR_TXNPTR_Pos))) 00530 /* -------- ADC_TNCR : (ADC Offset: 0x11C) Transmit Next Counter Register -------- */ 00531 #define ADC_TNCR_TXNCTR_Pos 0 00532 #define ADC_TNCR_TXNCTR_Msk (0xffffu << ADC_TNCR_TXNCTR_Pos) /* (ADC_TNCR) Transmit Counter Next */ 00533 #define ADC_TNCR_TXNCTR(value) ((ADC_TNCR_TXNCTR_Msk & ((value) << ADC_TNCR_TXNCTR_Pos))) 00534 /* -------- ADC_PTCR : (ADC Offset: 0x120) Transfer Control Register -------- */ 00535 #define ADC_PTCR_RXTEN (0x1u << 0) /* (ADC_PTCR) Receiver Transfer Enable */ 00536 #define ADC_PTCR_RXTDIS (0x1u << 1) /* (ADC_PTCR) Receiver Transfer Disable */ 00537 #define ADC_PTCR_TXTEN (0x1u << 8) /* (ADC_PTCR) Transmitter Transfer Enable */ 00538 #define ADC_PTCR_TXTDIS (0x1u << 9) /* (ADC_PTCR) Transmitter Transfer Disable */ 00539 /* -------- ADC_PTSR : (ADC Offset: 0x124) Transfer Status Register -------- */ 00540 #define ADC_PTSR_RXTEN (0x1u << 0) /* (ADC_PTSR) Receiver Transfer Enable */ 00541 #define ADC_PTSR_TXTEN (0x1u << 8) /* (ADC_PTSR) Transmitter Transfer Enable */ 00542 00543 00544 /* ============================================================================= */ 00545 /* SOFTWARE API DEFINITION FOR Chip Identifier */ 00546 /* ============================================================================= */ 00547 00548 #ifndef __ASSEMBLY__ 00549 /* Chipid hardware registers */ 00550 typedef struct { 00551 RoReg CHIPID_CIDR; /* (Chipid Offset: 0x0) Chip ID Register */ 00552 RoReg CHIPID_EXID; /* (Chipid Offset: 0x4) Chip ID Extension Register */ 00553 } Chipid; 00554 #endif /* __ASSEMBLY__ */ 00555 /* -------- CHIPID_CIDR : (CHIPID Offset: 0x0) Chip ID Register -------- */ 00556 #define CHIPID_CIDR_VERSION_Pos 0 00557 #define CHIPID_CIDR_VERSION_Msk (0x1fu << CHIPID_CIDR_VERSION_Pos) /* (CHIPID_CIDR) Version of the Device */ 00558 #define CHIPID_CIDR_EPROC_Pos 5 00559 #define CHIPID_CIDR_EPROC_Msk (0x7u << CHIPID_CIDR_EPROC_Pos) /* (CHIPID_CIDR) Embedded Processor */ 00560 #define CHIPID_CIDR_EPROC_ARM946ES (0x1u << 5) /* (CHIPID_CIDR) ARM946ES */ 00561 #define CHIPID_CIDR_EPROC_ARM7TDMI (0x2u << 5) /* (CHIPID_CIDR) ARM7TDMI */ 00562 #define CHIPID_CIDR_EPROC_CM3 (0x3u << 5) /* (CHIPID_CIDR) Cortex-M3 */ 00563 #define CHIPID_CIDR_EPROC_ARM920T (0x4u << 5) /* (CHIPID_CIDR) ARM920T */ 00564 #define CHIPID_CIDR_EPROC_ARM926EJS (0x5u << 5) /* (CHIPID_CIDR) ARM926EJS */ 00565 #define CHIPID_CIDR_EPROC_CA5 (0x6u << 5) /* (CHIPID_CIDR) Cortex-A5 */ 00566 #define CHIPID_CIDR_NVPSIZ_Pos 8 00567 #define CHIPID_CIDR_NVPSIZ_Msk (0xfu << CHIPID_CIDR_NVPSIZ_Pos) /* (CHIPID_CIDR) Nonvolatile Program Memory Size */ 00568 #define CHIPID_CIDR_NVPSIZ_NONE (0x0u << 8) /* (CHIPID_CIDR) None */ 00569 #define CHIPID_CIDR_NVPSIZ_8K (0x1u << 8) /* (CHIPID_CIDR) 8K bytes */ 00570 #define CHIPID_CIDR_NVPSIZ_16K (0x2u << 8) /* (CHIPID_CIDR) 16K bytes */ 00571 #define CHIPID_CIDR_NVPSIZ_32K (0x3u << 8) /* (CHIPID_CIDR) 32K bytes */ 00572 #define CHIPID_CIDR_NVPSIZ_64K (0x5u << 8) /* (CHIPID_CIDR) 64K bytes */ 00573 #define CHIPID_CIDR_NVPSIZ_128K (0x7u << 8) /* (CHIPID_CIDR) 128K bytes */ 00574 #define CHIPID_CIDR_NVPSIZ_256K (0x9u << 8) /* (CHIPID_CIDR) 256K bytes */ 00575 #define CHIPID_CIDR_NVPSIZ_512K (0xAu << 8) /* (CHIPID_CIDR) 512K bytes */ 00576 #define CHIPID_CIDR_NVPSIZ_1024K (0xCu << 8) /* (CHIPID_CIDR) 1024K bytes */ 00577 #define CHIPID_CIDR_NVPSIZ_2048K (0xEu << 8) /* (CHIPID_CIDR) 2048K bytes */ 00578 #define CHIPID_CIDR_NVPSIZ2_Pos 12 00579 #define CHIPID_CIDR_NVPSIZ2_Msk (0xfu << CHIPID_CIDR_NVPSIZ2_Pos) /* (CHIPID_CIDR) */ 00580 #define CHIPID_CIDR_NVPSIZ2_NONE (0x0u << 12) /* (CHIPID_CIDR) None */ 00581 #define CHIPID_CIDR_NVPSIZ2_8K (0x1u << 12) /* (CHIPID_CIDR) 8K bytes */ 00582 #define CHIPID_CIDR_NVPSIZ2_16K (0x2u << 12) /* (CHIPID_CIDR) 16K bytes */ 00583 #define CHIPID_CIDR_NVPSIZ2_32K (0x3u << 12) /* (CHIPID_CIDR) 32K bytes */ 00584 #define CHIPID_CIDR_NVPSIZ2_64K (0x5u << 12) /* (CHIPID_CIDR) 64K bytes */ 00585 #define CHIPID_CIDR_NVPSIZ2_128K (0x7u << 12) /* (CHIPID_CIDR) 128K bytes */ 00586 #define CHIPID_CIDR_NVPSIZ2_256K (0x9u << 12) /* (CHIPID_CIDR) 256K bytes */ 00587 #define CHIPID_CIDR_NVPSIZ2_512K (0xAu << 12) /* (CHIPID_CIDR) 512K bytes */ 00588 #define CHIPID_CIDR_NVPSIZ2_1024K (0xCu << 12) /* (CHIPID_CIDR) 1024K bytes */ 00589 #define CHIPID_CIDR_NVPSIZ2_2048K (0xEu << 12) /* (CHIPID_CIDR) 2048K bytes */ 00590 #define CHIPID_CIDR_SRAMSIZ_Pos 16 00591 #define CHIPID_CIDR_SRAMSIZ_Msk (0xfu << CHIPID_CIDR_SRAMSIZ_Pos) /* (CHIPID_CIDR) Internal SRAM Size */ 00592 #define CHIPID_CIDR_SRAMSIZ_48K (0x0u << 16) /* (CHIPID_CIDR) 48K bytes */ 00593 #define CHIPID_CIDR_SRAMSIZ_1K (0x1u << 16) /* (CHIPID_CIDR) 1K bytes */ 00594 #define CHIPID_CIDR_SRAMSIZ_2K (0x2u << 16) /* (CHIPID_CIDR) 2K bytes */ 00595 #define CHIPID_CIDR_SRAMSIZ_6K (0x3u << 16) /* (CHIPID_CIDR) 6K bytes */ 00596 #define CHIPID_CIDR_SRAMSIZ_112K (0x4u << 16) /* (CHIPID_CIDR) 112K bytes */ 00597 #define CHIPID_CIDR_SRAMSIZ_4K (0x5u << 16) /* (CHIPID_CIDR) 4K bytes */ 00598 #define CHIPID_CIDR_SRAMSIZ_80K (0x6u << 16) /* (CHIPID_CIDR) 80K bytes */ 00599 #define CHIPID_CIDR_SRAMSIZ_160K (0x7u << 16) /* (CHIPID_CIDR) 160K bytes */ 00600 #define CHIPID_CIDR_SRAMSIZ_8K (0x8u << 16) /* (CHIPID_CIDR) 8K bytes */ 00601 #define CHIPID_CIDR_SRAMSIZ_16K (0x9u << 16) /* (CHIPID_CIDR) 16K bytes */ 00602 #define CHIPID_CIDR_SRAMSIZ_32K (0xAu << 16) /* (CHIPID_CIDR) 32K bytes */ 00603 #define CHIPID_CIDR_SRAMSIZ_64K (0xBu << 16) /* (CHIPID_CIDR) 64K bytes */ 00604 #define CHIPID_CIDR_SRAMSIZ_128K (0xCu << 16) /* (CHIPID_CIDR) 128K bytes */ 00605 #define CHIPID_CIDR_SRAMSIZ_256K (0xDu << 16) /* (CHIPID_CIDR) 256K bytes */ 00606 #define CHIPID_CIDR_SRAMSIZ_96K (0xEu << 16) /* (CHIPID_CIDR) 96K bytes */ 00607 #define CHIPID_CIDR_SRAMSIZ_512K (0xFu << 16) /* (CHIPID_CIDR) 512K bytes */ 00608 #define CHIPID_CIDR_ARCH_Pos 20 00609 #define CHIPID_CIDR_ARCH_Msk (0xffu << CHIPID_CIDR_ARCH_Pos) /* (CHIPID_CIDR) Architecture Identifier */ 00610 #define CHIPID_CIDR_ARCH_AT91SAM9xx (0x19u << 20) /* (CHIPID_CIDR) AT91SAM9xx Series */ 00611 #define CHIPID_CIDR_ARCH_AT91SAM9XExx (0x29u << 20) /* (CHIPID_CIDR) AT91SAM9XExx Series */ 00612 #define CHIPID_CIDR_ARCH_AT91x34 (0x34u << 20) /* (CHIPID_CIDR) AT91x34 Series */ 00613 #define CHIPID_CIDR_ARCH_CAP7 (0x37u << 20) /* (CHIPID_CIDR) CAP7 Series */ 00614 #define CHIPID_CIDR_ARCH_CAP9 (0x39u << 20) /* (CHIPID_CIDR) CAP9 Series */ 00615 #define CHIPID_CIDR_ARCH_CAP11 (0x3Bu << 20) /* (CHIPID_CIDR) CAP11 Series */ 00616 #define CHIPID_CIDR_ARCH_AT91x40 (0x40u << 20) /* (CHIPID_CIDR) AT91x40 Series */ 00617 #define CHIPID_CIDR_ARCH_AT91x42 (0x42u << 20) /* (CHIPID_CIDR) AT91x42 Series */ 00618 #define CHIPID_CIDR_ARCH_AT91x55 (0x55u << 20) /* (CHIPID_CIDR) AT91x55 Series */ 00619 #define CHIPID_CIDR_ARCH_AT91SAM7Axx (0x60u << 20) /* (CHIPID_CIDR) AT91SAM7Axx Series */ 00620 #define CHIPID_CIDR_ARCH_AT91SAM7AQxx (0x61u << 20) /* (CHIPID_CIDR) AT91SAM7AQxx Series */ 00621 #define CHIPID_CIDR_ARCH_AT91x63 (0x63u << 20) /* (CHIPID_CIDR) AT91x63 Series */ 00622 #define CHIPID_CIDR_ARCH_AT91SAM7Sxx (0x70u << 20) /* (CHIPID_CIDR) AT91SAM7Sxx Series */ 00623 #define CHIPID_CIDR_ARCH_AT91SAM7XCxx (0x71u << 20) /* (CHIPID_CIDR) AT91SAM7XCxx Series */ 00624 #define CHIPID_CIDR_ARCH_AT91SAM7SExx (0x72u << 20) /* (CHIPID_CIDR) AT91SAM7SExx Series */ 00625 #define CHIPID_CIDR_ARCH_AT91SAM7Lxx (0x73u << 20) /* (CHIPID_CIDR) AT91SAM7Lxx Series */ 00626 #define CHIPID_CIDR_ARCH_AT91SAM7Xxx (0x75u << 20) /* (CHIPID_CIDR) AT91SAM7Xxx Series */ 00627 #define CHIPID_CIDR_ARCH_AT91SAM7SLxx (0x76u << 20) /* (CHIPID_CIDR) AT91SAM7SLxx Series */ 00628 #define CHIPID_CIDR_ARCH_SAM3UxC (0x80u << 20) /* (CHIPID_CIDR) SAM3UxC Series (100-pin version) */ 00629 #define CHIPID_CIDR_ARCH_SAM3UxE (0x81u << 20) /* (CHIPID_CIDR) SAM3UxE Series (144-pin version) */ 00630 #define CHIPID_CIDR_ARCH_SAM3AxC (0x83u << 20) /* (CHIPID_CIDR) SAM3AxC Series (100-pin version) */ 00631 #define CHIPID_CIDR_ARCH_SAM3XxC (0x84u << 20) /* (CHIPID_CIDR) SAM3XxC Series (100-pin version) */ 00632 #define CHIPID_CIDR_ARCH_SAM3XxE (0x85u << 20) /* (CHIPID_CIDR) SAM3XxE Series (144-pin version) */ 00633 #define CHIPID_CIDR_ARCH_SAM3XxG (0x86u << 20) /* (CHIPID_CIDR) SAM3XxG Series (208/217-pin version) */ 00634 #define CHIPID_CIDR_ARCH_SAM3SxA (0x88u << 20) /* (CHIPID_CIDR) SAM3SxA Series (48-pin version) */ 00635 #define CHIPID_CIDR_ARCH_SAM3SxB (0x89u << 20) /* (CHIPID_CIDR) SAM3SxB Series (64-pin version) */ 00636 #define CHIPID_CIDR_ARCH_SAM3SxC (0x8Au << 20) /* (CHIPID_CIDR) SAM3SxC Series (100-pin version) */ 00637 #define CHIPID_CIDR_ARCH_AT91x92 (0x92u << 20) /* (CHIPID_CIDR) AT91x92 Series */ 00638 #define CHIPID_CIDR_ARCH_SAM3NxA (0x93u << 20) /* (CHIPID_CIDR) SAM3NxA Series (48-pin version) */ 00639 #define CHIPID_CIDR_ARCH_SAM3NxB (0x94u << 20) /* (CHIPID_CIDR) SAM3NxB Series (64-pin version) */ 00640 #define CHIPID_CIDR_ARCH_SAM3NxC (0x95u << 20) /* (CHIPID_CIDR) SAM3NxC Series (100-pin version) */ 00641 #define CHIPID_CIDR_ARCH_SAM3SDxA (0x98u << 20) /* (CHIPID_CIDR) SAM3SDxA Series (48-pin version) */ 00642 #define CHIPID_CIDR_ARCH_SAM3SDxB (0x99u << 20) /* (CHIPID_CIDR) SAM3SDxB Series (64-pin version) */ 00643 #define CHIPID_CIDR_ARCH_SAM3SDxC (0x9Au << 20) /* (CHIPID_CIDR) SAM3SDxC Series (100-pin version) */ 00644 #define CHIPID_CIDR_ARCH_SAM5A (0xA5u << 20) /* (CHIPID_CIDR) SAM5A */ 00645 #define CHIPID_CIDR_ARCH_AT75Cxx (0xF0u << 20) /* (CHIPID_CIDR) AT75Cxx Series */ 00646 #define CHIPID_CIDR_NVPTYP_Pos 28 00647 #define CHIPID_CIDR_NVPTYP_Msk (0x7u << CHIPID_CIDR_NVPTYP_Pos) /* (CHIPID_CIDR) Nonvolatile Program Memory Type */ 00648 #define CHIPID_CIDR_NVPTYP_ROM (0x0u << 28) /* (CHIPID_CIDR) ROM */ 00649 #define CHIPID_CIDR_NVPTYP_ROMLESS (0x1u << 28) /* (CHIPID_CIDR) ROMless or on-chip Flash */ 00650 #define CHIPID_CIDR_NVPTYP_FLASH (0x2u << 28) /* (CHIPID_CIDR) Embedded Flash Memory */ 00651 #define CHIPID_CIDR_NVPTYP_ROM_FLASH (0x3u << 28) /* (CHIPID_CIDR) ROM and Embedded Flash MemoryNVPSIZ is ROM size NVPSIZ2 is Flash size */ 00652 #define CHIPID_CIDR_NVPTYP_SRAM (0x4u << 28) /* (CHIPID_CIDR) SRAM emulating ROM */ 00653 #define CHIPID_CIDR_EXT (0x1u << 31) /* (CHIPID_CIDR) Extension Flag */ 00654 /* -------- CHIPID_EXID : (CHIPID Offset: 0x4) Chip ID Extension Register -------- */ 00655 #define CHIPID_EXID_EXID_Pos 0 00656 #define CHIPID_EXID_EXID_Msk (0xffffffffu << CHIPID_EXID_EXID_Pos) /* (CHIPID_EXID) Chip ID Extension */ 00657 00658 00659 /* ============================================================================= */ 00660 /* SOFTWARE API DEFINITION FOR Digital-to-Analog Converter Controller */ 00661 /* ============================================================================= */ 00662 00663 #ifndef __ASSEMBLY__ 00664 /* Dacc hardware registers */ 00665 typedef struct { 00666 WoReg DACC_CR; /* (Dacc Offset: 0x00) Control Register */ 00667 RwReg DACC_MR; /* (Dacc Offset: 0x04) Mode Register */ 00668 WoReg DACC_CDR; /* (Dacc Offset: 0x08) Conversion Data Register */ 00669 WoReg DACC_IER; /* (Dacc Offset: 0x0C) Interrupt Enable Register */ 00670 WoReg DACC_IDR; /* (Dacc Offset: 0x10) Interrupt Disable Register */ 00671 RoReg DACC_IMR; /* (Dacc Offset: 0x14) Interrupt Mask Register */ 00672 RoReg DACC_ISR; /* (Dacc Offset: 0x18) Interrupt Status Register */ 00673 RwReg Reserved1[50]; 00674 RwReg DACC_WPMR; /* (Dacc Offset: 0xE4) Write Protect Mode Register */ 00675 RoReg DACC_WPSR; /* (Dacc Offset: 0xE8) Write Protect Status Register */ 00676 RwReg Reserved2[5]; 00677 RwReg DACC_RPR; /* (Dacc Offset: 0x100) Receive Pointer Register */ 00678 RwReg DACC_RCR; /* (Dacc Offset: 0x104) Receive Counter Register */ 00679 RwReg DACC_TPR; /* (Dacc Offset: 0x108) Transmit Pointer Register */ 00680 RwReg DACC_TCR; /* (Dacc Offset: 0x10C) Transmit Counter Register */ 00681 RwReg DACC_RNPR; /* (Dacc Offset: 0x110) Receive Next Pointer Register */ 00682 RwReg DACC_RNCR; /* (Dacc Offset: 0x114) Receive Next Counter Register */ 00683 RwReg DACC_TNPR; /* (Dacc Offset: 0x118) Transmit Next Pointer Register */ 00684 RwReg DACC_TNCR; /* (Dacc Offset: 0x11C) Transmit Next Counter Register */ 00685 WoReg DACC_PTCR; /* (Dacc Offset: 0x120) Transfer Control Register */ 00686 RoReg DACC_PTSR; /* (Dacc Offset: 0x124) Transfer Status Register */ 00687 } Dacc; 00688 #endif /* __ASSEMBLY__ */ 00689 /* -------- DACC_CR : (DACC Offset: 0x00) Control Register -------- */ 00690 #define DACC_CR_SWRST (0x1u << 0) /* (DACC_CR) Software Reset */ 00691 /* -------- DACC_MR : (DACC Offset: 0x04) Mode Register -------- */ 00692 #define DACC_MR_TRGEN (0x1u << 0) /* (DACC_MR) Trigger Enable */ 00693 #define DACC_MR_TRGEN_DIS (0x0u << 0) /* (DACC_MR) External trigger mode disabled. DACC in free running mode. */ 00694 #define DACC_MR_TRGEN_EN (0x1u << 0) /* (DACC_MR) External trigger mode enabled. */ 00695 #define DACC_MR_TRGSEL_Pos 1 00696 #define DACC_MR_TRGSEL_Msk (0x7u << DACC_MR_TRGSEL_Pos) /* (DACC_MR) Trigger Selection */ 00697 #define DACC_MR_TRGSEL_TRGSEL0 (0x0u << 1) /* (DACC_MR) External trigger */ 00698 #define DACC_MR_TRGSEL_TRGSEL1 (0x1u << 1) /* (DACC_MR) TIO Output of the Timer Counter Channel 0 */ 00699 #define DACC_MR_TRGSEL_TRGSEL2 (0x2u << 1) /* (DACC_MR) TIO Output of the Timer Counter Channel 1 */ 00700 #define DACC_MR_TRGSEL_TRGSEL3 (0x3u << 1) /* (DACC_MR) TIO Output of the Timer Counter Channel 2 */ 00701 #define DACC_MR_DACEN (0x1u << 4) /* (DACC_MR) DAC enable */ 00702 #define DACC_MR_WORD (0x1u << 5) /* (DACC_MR) Word Transfer */ 00703 #define DACC_MR_WORD_HALF (0x0u << 5) /* (DACC_MR) Half-Word transfer */ 00704 #define DACC_MR_WORD_WORD (0x1u << 5) /* (DACC_MR) Word Transfer */ 00705 #define DACC_MR_STARTUP_Pos 8 00706 #define DACC_MR_STARTUP_Msk (0xffu << DACC_MR_STARTUP_Pos) /* (DACC_MR) Startup Time Selection */ 00707 #define DACC_MR_STARTUP(value) ((DACC_MR_STARTUP_Msk & ((value) << DACC_MR_STARTUP_Pos))) 00708 #define DACC_MR_CLKDIV_Pos 16 00709 #define DACC_MR_CLKDIV_Msk (0xffffu << DACC_MR_CLKDIV_Pos) /* (DACC_MR) DAC Clock Divider for Internal Trigger */ 00710 #define DACC_MR_CLKDIV(value) ((DACC_MR_CLKDIV_Msk & ((value) << DACC_MR_CLKDIV_Pos))) 00711 /* -------- DACC_CDR : (DACC Offset: 0x08) Conversion Data Register -------- */ 00712 #define DACC_CDR_DATA_Pos 0 00713 #define DACC_CDR_DATA_Msk (0xffffffffu << DACC_CDR_DATA_Pos) /* (DACC_CDR) Data to Convert */ 00714 #define DACC_CDR_DATA(value) ((DACC_CDR_DATA_Msk & ((value) << DACC_CDR_DATA_Pos))) 00715 /* -------- DACC_IER : (DACC Offset: 0x0C) Interrupt Enable Register -------- */ 00716 #define DACC_IER_TXRDY (0x1u << 0) /* (DACC_IER) Transmission Ready Interrupt Enable */ 00717 #define DACC_IER_ENDTX (0x1u << 1) /* (DACC_IER) End of PDC Interrupt Enable */ 00718 #define DACC_IER_TXBUFE (0x1u << 2) /* (DACC_IER) Buffer Empty Interrupt Enable */ 00719 /* -------- DACC_IDR : (DACC Offset: 0x10) Interrupt Disable Register -------- */ 00720 #define DACC_IDR_TXRDY (0x1u << 0) /* (DACC_IDR) Transmission Ready Interrupt Disable */ 00721 #define DACC_IDR_ENDTX (0x1u << 1) /* (DACC_IDR) End of PDC Interrupt Disable */ 00722 #define DACC_IDR_TXBUFE (0x1u << 2) /* (DACC_IDR) Buffer Empty Interrupt Disable */ 00723 /* -------- DACC_IMR : (DACC Offset: 0x14) Interrupt Mask Register -------- */ 00724 #define DACC_IMR_TXRDY (0x1u << 0) /* (DACC_IMR) Transmission Ready Interrupt Mask */ 00725 #define DACC_IMR_ENDTX (0x1u << 1) /* (DACC_IMR) End of PDC Interrupt Mask */ 00726 #define DACC_IMR_TXBUFE (0x1u << 2) /* (DACC_IMR) Buffer Empty Interrupt Mask */ 00727 /* -------- DACC_ISR : (DACC Offset: 0x18) Interrupt Status Register -------- */ 00728 #define DACC_ISR_TXRDY (0x1u << 0) /* (DACC_ISR) Transmission Ready Interrupt Flag */ 00729 #define DACC_ISR_ENDTX (0x1u << 1) /* (DACC_ISR) End of PDC Interrupt Flag */ 00730 #define DACC_ISR_TXBUFE (0x1u << 2) /* (DACC_ISR) Buffer Empty Interrupt Flag */ 00731 /* -------- DACC_WPMR : (DACC Offset: 0xE4) Write Protect Mode Register -------- */ 00732 #define DACC_WPMR_WPEN (0x1u << 0) /* (DACC_WPMR) Write Protect Enable */ 00733 #define DACC_WPMR_WPKEY_Pos 8 00734 #define DACC_WPMR_WPKEY_Msk (0xffffffu << DACC_WPMR_WPKEY_Pos) /* (DACC_WPMR) Write Protect KEY */ 00735 #define DACC_WPMR_WPKEY(value) ((DACC_WPMR_WPKEY_Msk & ((value) << DACC_WPMR_WPKEY_Pos))) 00736 /* -------- DACC_WPSR : (DACC Offset: 0xE8) Write Protect Status Register -------- */ 00737 #define DACC_WPSR_WPROTERR (0x1u << 0) /* (DACC_WPSR) Write protection error */ 00738 #define DACC_WPSR_WPROTADDR_Pos 8 00739 #define DACC_WPSR_WPROTADDR_Msk (0xffu << DACC_WPSR_WPROTADDR_Pos) /* (DACC_WPSR) Write protection error address */ 00740 /* -------- DACC_RPR : (DACC Offset: 0x100) Receive Pointer Register -------- */ 00741 #define DACC_RPR_RXPTR_Pos 0 00742 #define DACC_RPR_RXPTR_Msk (0xffffffffu << DACC_RPR_RXPTR_Pos) /* (DACC_RPR) Receive Pointer Register */ 00743 #define DACC_RPR_RXPTR(value) ((DACC_RPR_RXPTR_Msk & ((value) << DACC_RPR_RXPTR_Pos))) 00744 /* -------- DACC_RCR : (DACC Offset: 0x104) Receive Counter Register -------- */ 00745 #define DACC_RCR_RXCTR_Pos 0 00746 #define DACC_RCR_RXCTR_Msk (0xffffu << DACC_RCR_RXCTR_Pos) /* (DACC_RCR) Receive Counter Register */ 00747 #define DACC_RCR_RXCTR(value) ((DACC_RCR_RXCTR_Msk & ((value) << DACC_RCR_RXCTR_Pos))) 00748 /* -------- DACC_TPR : (DACC Offset: 0x108) Transmit Pointer Register -------- */ 00749 #define DACC_TPR_TXPTR_Pos 0 00750 #define DACC_TPR_TXPTR_Msk (0xffffffffu << DACC_TPR_TXPTR_Pos) /* (DACC_TPR) Transmit Counter Register */ 00751 #define DACC_TPR_TXPTR(value) ((DACC_TPR_TXPTR_Msk & ((value) << DACC_TPR_TXPTR_Pos))) 00752 /* -------- DACC_TCR : (DACC Offset: 0x10C) Transmit Counter Register -------- */ 00753 #define DACC_TCR_TXCTR_Pos 0 00754 #define DACC_TCR_TXCTR_Msk (0xffffu << DACC_TCR_TXCTR_Pos) /* (DACC_TCR) Transmit Counter Register */ 00755 #define DACC_TCR_TXCTR(value) ((DACC_TCR_TXCTR_Msk & ((value) << DACC_TCR_TXCTR_Pos))) 00756 /* -------- DACC_RNPR : (DACC Offset: 0x110) Receive Next Pointer Register -------- */ 00757 #define DACC_RNPR_RXNPTR_Pos 0 00758 #define DACC_RNPR_RXNPTR_Msk (0xffffffffu << DACC_RNPR_RXNPTR_Pos) /* (DACC_RNPR) Receive Next Pointer */ 00759 #define DACC_RNPR_RXNPTR(value) ((DACC_RNPR_RXNPTR_Msk & ((value) << DACC_RNPR_RXNPTR_Pos))) 00760 /* -------- DACC_RNCR : (DACC Offset: 0x114) Receive Next Counter Register -------- */ 00761 #define DACC_RNCR_RXNCTR_Pos 0 00762 #define DACC_RNCR_RXNCTR_Msk (0xffffu << DACC_RNCR_RXNCTR_Pos) /* (DACC_RNCR) Receive Next Counter */ 00763 #define DACC_RNCR_RXNCTR(value) ((DACC_RNCR_RXNCTR_Msk & ((value) << DACC_RNCR_RXNCTR_Pos))) 00764 /* -------- DACC_TNPR : (DACC Offset: 0x118) Transmit Next Pointer Register -------- */ 00765 #define DACC_TNPR_TXNPTR_Pos 0 00766 #define DACC_TNPR_TXNPTR_Msk (0xffffffffu << DACC_TNPR_TXNPTR_Pos) /* (DACC_TNPR) Transmit Next Pointer */ 00767 #define DACC_TNPR_TXNPTR(value) ((DACC_TNPR_TXNPTR_Msk & ((value) << DACC_TNPR_TXNPTR_Pos))) 00768 /* -------- DACC_TNCR : (DACC Offset: 0x11C) Transmit Next Counter Register -------- */ 00769 #define DACC_TNCR_TXNCTR_Pos 0 00770 #define DACC_TNCR_TXNCTR_Msk (0xffffu << DACC_TNCR_TXNCTR_Pos) /* (DACC_TNCR) Transmit Counter Next */ 00771 #define DACC_TNCR_TXNCTR(value) ((DACC_TNCR_TXNCTR_Msk & ((value) << DACC_TNCR_TXNCTR_Pos))) 00772 /* -------- DACC_PTCR : (DACC Offset: 0x120) Transfer Control Register -------- */ 00773 #define DACC_PTCR_RXTEN (0x1u << 0) /* (DACC_PTCR) Receiver Transfer Enable */ 00774 #define DACC_PTCR_RXTDIS (0x1u << 1) /* (DACC_PTCR) Receiver Transfer Disable */ 00775 #define DACC_PTCR_TXTEN (0x1u << 8) /* (DACC_PTCR) Transmitter Transfer Enable */ 00776 #define DACC_PTCR_TXTDIS (0x1u << 9) /* (DACC_PTCR) Transmitter Transfer Disable */ 00777 /* -------- DACC_PTSR : (DACC Offset: 0x124) Transfer Status Register -------- */ 00778 #define DACC_PTSR_RXTEN (0x1u << 0) /* (DACC_PTSR) Receiver Transfer Enable */ 00779 #define DACC_PTSR_TXTEN (0x1u << 8) /* (DACC_PTSR) Transmitter Transfer Enable */ 00780 00781 00782 00783 /* ============================================================================= */ 00784 /* SOFTWARE API DEFINITION FOR General Purpose Backup Register */ 00785 /* ============================================================================= */ 00786 00787 #ifndef __ASSEMBLY__ 00788 /* Gpbr hardware registers */ 00789 typedef struct { 00790 RwReg SYS_GPBR0; /* (Gpbr Offset: 0x0) General Purpose Backup Register 0 */ 00791 RwReg SYS_GPBR1; /* (Gpbr Offset: 0x4) General Purpose Backup Register 1 */ 00792 RwReg SYS_GPBR2; /* (Gpbr Offset: 0x8) General Purpose Backup Register 2 */ 00793 RwReg SYS_GPBR3; /* (Gpbr Offset: 0xC) General Purpose Backup Register 3 */ 00794 RwReg SYS_GPBR4; /* (Gpbr Offset: 0x10) General Purpose Backup Register 4 */ 00795 RwReg SYS_GPBR5; /* (Gpbr Offset: 0x14) General Purpose Backup Register 5 */ 00796 RwReg SYS_GPBR6; /* (Gpbr Offset: 0x18) General Purpose Backup Register 6 */ 00797 RwReg SYS_GPBR7; /* (Gpbr Offset: 0x1C) General Purpose Backup Register 7 */ 00798 } Gpbr; 00799 #endif /* __ASSEMBLY__ */ 00800 /* -------- SYS_GPBR0 : (GPBR Offset: 0x0) General Purpose Backup Register 0 -------- */ 00801 #define SYS_GPBR0_GPBR_VALUE0_Pos 0 00802 #define SYS_GPBR0_GPBR_VALUE0_Msk (0xffffffffu << SYS_GPBR0_GPBR_VALUE0_Pos) /* (SYS_GPBR0) Value of GPBR x */ 00803 #define SYS_GPBR0_GPBR_VALUE0(value) ((SYS_GPBR0_GPBR_VALUE0_Msk & ((value) << SYS_GPBR0_GPBR_VALUE0_Pos))) 00804 /* -------- SYS_GPBR1 : (GPBR Offset: 0x4) General Purpose Backup Register 1 -------- */ 00805 #define SYS_GPBR1_GPBR_VALUE1_Pos 0 00806 #define SYS_GPBR1_GPBR_VALUE1_Msk (0xffffffffu << SYS_GPBR1_GPBR_VALUE1_Pos) /* (SYS_GPBR1) Value of GPBR x */ 00807 #define SYS_GPBR1_GPBR_VALUE1(value) ((SYS_GPBR1_GPBR_VALUE1_Msk & ((value) << SYS_GPBR1_GPBR_VALUE1_Pos))) 00808 /* -------- SYS_GPBR2 : (GPBR Offset: 0x8) General Purpose Backup Register 2 -------- */ 00809 #define SYS_GPBR2_GPBR_VALUE2_Pos 0 00810 #define SYS_GPBR2_GPBR_VALUE2_Msk (0xffffffffu << SYS_GPBR2_GPBR_VALUE2_Pos) /* (SYS_GPBR2) Value of GPBR x */ 00811 #define SYS_GPBR2_GPBR_VALUE2(value) ((SYS_GPBR2_GPBR_VALUE2_Msk & ((value) << SYS_GPBR2_GPBR_VALUE2_Pos))) 00812 /* -------- SYS_GPBR3 : (GPBR Offset: 0xC) General Purpose Backup Register 3 -------- */ 00813 #define SYS_GPBR3_GPBR_VALUE3_Pos 0 00814 #define SYS_GPBR3_GPBR_VALUE3_Msk (0xffffffffu << SYS_GPBR3_GPBR_VALUE3_Pos) /* (SYS_GPBR3) Value of GPBR x */ 00815 #define SYS_GPBR3_GPBR_VALUE3(value) ((SYS_GPBR3_GPBR_VALUE3_Msk & ((value) << SYS_GPBR3_GPBR_VALUE3_Pos))) 00816 /* -------- SYS_GPBR4 : (GPBR Offset: 0x10) General Purpose Backup Register 4 -------- */ 00817 #define SYS_GPBR4_GPBR_VALUE4_Pos 0 00818 #define SYS_GPBR4_GPBR_VALUE4_Msk (0xffffffffu << SYS_GPBR4_GPBR_VALUE4_Pos) /* (SYS_GPBR4) Value of GPBR x */ 00819 #define SYS_GPBR4_GPBR_VALUE4(value) ((SYS_GPBR4_GPBR_VALUE4_Msk & ((value) << SYS_GPBR4_GPBR_VALUE4_Pos))) 00820 /* -------- SYS_GPBR5 : (GPBR Offset: 0x14) General Purpose Backup Register 5 -------- */ 00821 #define SYS_GPBR5_GPBR_VALUE5_Pos 0 00822 #define SYS_GPBR5_GPBR_VALUE5_Msk (0xffffffffu << SYS_GPBR5_GPBR_VALUE5_Pos) /* (SYS_GPBR5) Value of GPBR x */ 00823 #define SYS_GPBR5_GPBR_VALUE5(value) ((SYS_GPBR5_GPBR_VALUE5_Msk & ((value) << SYS_GPBR5_GPBR_VALUE5_Pos))) 00824 /* -------- SYS_GPBR6 : (GPBR Offset: 0x18) General Purpose Backup Register 6 -------- */ 00825 #define SYS_GPBR6_GPBR_VALUE6_Pos 0 00826 #define SYS_GPBR6_GPBR_VALUE6_Msk (0xffffffffu << SYS_GPBR6_GPBR_VALUE6_Pos) /* (SYS_GPBR6) Value of GPBR x */ 00827 #define SYS_GPBR6_GPBR_VALUE6(value) ((SYS_GPBR6_GPBR_VALUE6_Msk & ((value) << SYS_GPBR6_GPBR_VALUE6_Pos))) 00828 /* -------- SYS_GPBR7 : (GPBR Offset: 0x1C) General Purpose Backup Register 7 -------- */ 00829 #define SYS_GPBR7_GPBR_VALUE7_Pos 0 00830 #define SYS_GPBR7_GPBR_VALUE7_Msk (0xffffffffu << SYS_GPBR7_GPBR_VALUE7_Pos) /* (SYS_GPBR7) Value of GPBR x */ 00831 #define SYS_GPBR7_GPBR_VALUE7(value) ((SYS_GPBR7_GPBR_VALUE7_Msk & ((value) << SYS_GPBR7_GPBR_VALUE7_Pos))) 00832 00833 00834 /* ============================================================================= */ 00835 /* SOFTWARE API DEFINITION FOR AHB Bus Matrix */ 00836 /* ============================================================================= */ 00837 00838 #ifndef __ASSEMBLY__ 00839 /* Matrix hardware registers */ 00840 typedef struct { 00841 RwReg MATRIX_MCFG[3]; /* (Matrix Offset: 0x0000) Master Configuration Register */ 00842 RwReg Reserved1[13]; 00843 RwReg MATRIX_SCFG[4]; /* (Matrix Offset: 0x0040) Slave Configuration Register */ 00844 RwReg Reserved2[12]; 00845 RwReg MATRIX_PRAS0; /* (Matrix Offset: 0x0080) Priority Register A for Slave 0 */ 00846 RwReg Reserved3[1]; 00847 RwReg MATRIX_PRAS1; /* (Matrix Offset: 0x0088) Priority Register A for Slave 1 */ 00848 RwReg Reserved4[1]; 00849 RwReg MATRIX_PRAS2; /* (Matrix Offset: 0x0090) Priority Register A for Slave 2 */ 00850 RwReg Reserved5[1]; 00851 RwReg MATRIX_PRAS3; /* (Matrix Offset: 0x0098) Priority Register A for Slave 3 */ 00852 RwReg Reserved6[1]; 00853 RwReg Reserved7[29]; 00854 RwReg CCFG_SYSIO; /* (Matrix Offset: 0x0114) System I/O Configuration register */ 00855 RwReg Reserved8[51]; 00856 RwReg MATRIX_WPMR; /* (Matrix Offset: 0x1E4) Write Protect Mode Register */ 00857 RoReg MATRIX_WPSR; /* (Matrix Offset: 0x1E8) Write Protect Status Register */ 00858 } Matrix; 00859 #endif /* __ASSEMBLY__ */ 00860 /* -------- MATRIX_MCFG[3] : (MATRIX Offset: 0x0000) Master Configuration Register -------- */ 00861 #define MATRIX_MCFG_ULBT_Pos 0 00862 #define MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos) /* (MATRIX_MCFG[3]) Undefined Length Burst Type */ 00863 #define MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos))) 00864 /* -------- MATRIX_SCFG[4] : (MATRIX Offset: 0x0040) Slave Configuration Register -------- */ 00865 #define MATRIX_SCFG_SLOT_CYCLE_Pos 0 00866 #define MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos) /* (MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst */ 00867 #define MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos))) 00868 #define MATRIX_SCFG_DEFMSTR_TYPE_Pos 16 00869 #define MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos) /* (MATRIX_SCFG[4]) Default Master Type */ 00870 #define MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos))) 00871 #define MATRIX_SCFG_FIXED_DEFMSTR_Pos 18 00872 #define MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos) /* (MATRIX_SCFG[4]) Fixed Default Master */ 00873 #define MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos))) 00874 #define MATRIX_SCFG_ARBT_Pos 24 00875 #define MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos) /* (MATRIX_SCFG[4]) Arbitration Type */ 00876 #define MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos))) 00877 /* -------- MATRIX_PRAS0 : (MATRIX Offset: 0x0080) Priority Register A for Slave 0 -------- */ 00878 #define MATRIX_PRAS0_M0PR_Pos 0 00879 #define MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos) /* (MATRIX_PRAS0) Master 0 Priority */ 00880 #define MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos))) 00881 #define MATRIX_PRAS0_M1PR_Pos 4 00882 #define MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos) /* (MATRIX_PRAS0) Master 1 Priority */ 00883 #define MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos))) 00884 #define MATRIX_PRAS0_M2PR_Pos 8 00885 #define MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos) /* (MATRIX_PRAS0) Master 2 Priority */ 00886 #define MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos))) 00887 #define MATRIX_PRAS0_M3PR_Pos 12 00888 #define MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos) /* (MATRIX_PRAS0) Master 3 Priority */ 00889 #define MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos))) 00890 /* -------- MATRIX_PRAS1 : (MATRIX Offset: 0x0088) Priority Register A for Slave 1 -------- */ 00891 #define MATRIX_PRAS1_M0PR_Pos 0 00892 #define MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos) /* (MATRIX_PRAS1) Master 0 Priority */ 00893 #define MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos))) 00894 #define MATRIX_PRAS1_M1PR_Pos 4 00895 #define MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos) /* (MATRIX_PRAS1) Master 1 Priority */ 00896 #define MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos))) 00897 #define MATRIX_PRAS1_M2PR_Pos 8 00898 #define MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos) /* (MATRIX_PRAS1) Master 2 Priority */ 00899 #define MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos))) 00900 #define MATRIX_PRAS1_M3PR_Pos 12 00901 #define MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos) /* (MATRIX_PRAS1) Master 3 Priority */ 00902 #define MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos))) 00903 /* -------- MATRIX_PRAS2 : (MATRIX Offset: 0x0090) Priority Register A for Slave 2 -------- */ 00904 #define MATRIX_PRAS2_M0PR_Pos 0 00905 #define MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos) /* (MATRIX_PRAS2) Master 0 Priority */ 00906 #define MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos))) 00907 #define MATRIX_PRAS2_M1PR_Pos 4 00908 #define MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos) /* (MATRIX_PRAS2) Master 1 Priority */ 00909 #define MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos))) 00910 #define MATRIX_PRAS2_M2PR_Pos 8 00911 #define MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos) /* (MATRIX_PRAS2) Master 2 Priority */ 00912 #define MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos))) 00913 #define MATRIX_PRAS2_M3PR_Pos 12 00914 #define MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos) /* (MATRIX_PRAS2) Master 3 Priority */ 00915 #define MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos))) 00916 /* -------- MATRIX_PRAS3 : (MATRIX Offset: 0x0098) Priority Register A for Slave 3 -------- */ 00917 #define MATRIX_PRAS3_M0PR_Pos 0 00918 #define MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos) /* (MATRIX_PRAS3) Master 0 Priority */ 00919 #define MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos))) 00920 #define MATRIX_PRAS3_M1PR_Pos 4 00921 #define MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos) /* (MATRIX_PRAS3) Master 1 Priority */ 00922 #define MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos))) 00923 #define MATRIX_PRAS3_M2PR_Pos 8 00924 #define MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos) /* (MATRIX_PRAS3) Master 2 Priority */ 00925 #define MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos))) 00926 #define MATRIX_PRAS3_M3PR_Pos 12 00927 #define MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos) /* (MATRIX_PRAS3) Master 3 Priority */ 00928 #define MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos))) 00929 /* -------- CCFG_SYSIO : (MATRIX Offset: 0x0114) System I/O Configuration register -------- */ 00930 #define CCFG_SYSIO_SYSIO4 (0x1u << 4) /* (CCFG_SYSIO) PB4 or TDI Assignment */ 00931 #define CCFG_SYSIO_SYSIO5 (0x1u << 5) /* (CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment */ 00932 #define CCFG_SYSIO_SYSIO6 (0x1u << 6) /* (CCFG_SYSIO) PB6 or TMS/SWDIO Assignment */ 00933 #define CCFG_SYSIO_SYSIO7 (0x1u << 7) /* (CCFG_SYSIO) PB7 or TCK/SWCLK Assignment */ 00934 #define CCFG_SYSIO_SYSIO12 (0x1u << 12) /* (CCFG_SYSIO) PB12 or ERASE Assignment */ 00935 /* -------- MATRIX_WPMR : (MATRIX Offset: 0x1E4) Write Protect Mode Register -------- */ 00936 #define MATRIX_WPMR_WPEN (0x1u << 0) /* (MATRIX_WPMR) Write Protect ENable */ 00937 #define MATRIX_WPMR_WPKEY_Pos 8 00938 #define MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos) /* (MATRIX_WPMR) Write Protect KEY (Write-only) */ 00939 #define MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos))) 00940 /* -------- MATRIX_WPSR : (MATRIX Offset: 0x1E8) Write Protect Status Register -------- */ 00941 #define MATRIX_WPSR_WPVS (0x1u << 0) /* (MATRIX_WPSR) Write Protect Violation Status */ 00942 #define MATRIX_WPSR_WPVSRC_Pos 8 00943 #define MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos) /* (MATRIX_WPSR) Write Protect Violation Source */ 00944 00945 00946 /* ============================================================================= */ 00947 /* SOFTWARE API DEFINITION FOR Peripheral DMA Controller */ 00948 /* ============================================================================= */ 00949 00950 #ifndef __ASSEMBLY__ 00951 /* Pdc hardware registers */ 00952 typedef struct { 00953 RwReg Reserved1[64]; 00954 RwReg PERIPH_RPR; /* (Pdc Offset: 0x100) Receive Pointer Register */ 00955 RwReg PERIPH_RCR; /* (Pdc Offset: 0x104) Receive Counter Register */ 00956 RwReg PERIPH_TPR; /* (Pdc Offset: 0x108) Transmit Pointer Register */ 00957 RwReg PERIPH_TCR; /* (Pdc Offset: 0x10C) Transmit Counter Register */ 00958 RwReg PERIPH_RNPR; /* (Pdc Offset: 0x110) Receive Next Pointer Register */ 00959 RwReg PERIPH_RNCR; /* (Pdc Offset: 0x114) Receive Next Counter Register */ 00960 RwReg PERIPH_TNPR; /* (Pdc Offset: 0x118) Transmit Next Pointer Register */ 00961 RwReg PERIPH_TNCR; /* (Pdc Offset: 0x11C) Transmit Next Counter Register */ 00962 WoReg PERIPH_PTCR; /* (Pdc Offset: 0x120) Transfer Control Register */ 00963 RoReg PERIPH_PTSR; /* (Pdc Offset: 0x124) Transfer Status Register */ 00964 } Pdc; 00965 #endif /* __ASSEMBLY__ */ 00966 /* -------- PERIPH_RPR : (PDC Offset: 0x100) Receive Pointer Register -------- */ 00967 #define PERIPH_RPR_RXPTR_Pos 0 00968 #define PERIPH_RPR_RXPTR_Msk (0xffffffffu << PERIPH_RPR_RXPTR_Pos) /* (PERIPH_RPR) Receive Pointer Register */ 00969 #define PERIPH_RPR_RXPTR(value) ((PERIPH_RPR_RXPTR_Msk & ((value) << PERIPH_RPR_RXPTR_Pos))) 00970 /* -------- PERIPH_RCR : (PDC Offset: 0x104) Receive Counter Register -------- */ 00971 #define PERIPH_RCR_RXCTR_Pos 0 00972 #define PERIPH_RCR_RXCTR_Msk (0xffffu << PERIPH_RCR_RXCTR_Pos) /* (PERIPH_RCR) Receive Counter Register */ 00973 #define PERIPH_RCR_RXCTR(value) ((PERIPH_RCR_RXCTR_Msk & ((value) << PERIPH_RCR_RXCTR_Pos))) 00974 /* -------- PERIPH_TPR : (PDC Offset: 0x108) Transmit Pointer Register -------- */ 00975 #define PERIPH_TPR_TXPTR_Pos 0 00976 #define PERIPH_TPR_TXPTR_Msk (0xffffffffu << PERIPH_TPR_TXPTR_Pos) /* (PERIPH_TPR) Transmit Counter Register */ 00977 #define PERIPH_TPR_TXPTR(value) ((PERIPH_TPR_TXPTR_Msk & ((value) << PERIPH_TPR_TXPTR_Pos))) 00978 /* -------- PERIPH_TCR : (PDC Offset: 0x10C) Transmit Counter Register -------- */ 00979 #define PERIPH_TCR_TXCTR_Pos 0 00980 #define PERIPH_TCR_TXCTR_Msk (0xffffu << PERIPH_TCR_TXCTR_Pos) /* (PERIPH_TCR) Transmit Counter Register */ 00981 #define PERIPH_TCR_TXCTR(value) ((PERIPH_TCR_TXCTR_Msk & ((value) << PERIPH_TCR_TXCTR_Pos))) 00982 /* -------- PERIPH_RNPR : (PDC Offset: 0x110) Receive Next Pointer Register -------- */ 00983 #define PERIPH_RNPR_RXNPTR_Pos 0 00984 #define PERIPH_RNPR_RXNPTR_Msk (0xffffffffu << PERIPH_RNPR_RXNPTR_Pos) /* (PERIPH_RNPR) Receive Next Pointer */ 00985 #define PERIPH_RNPR_RXNPTR(value) ((PERIPH_RNPR_RXNPTR_Msk & ((value) << PERIPH_RNPR_RXNPTR_Pos))) 00986 /* -------- PERIPH_RNCR : (PDC Offset: 0x114) Receive Next Counter Register -------- */ 00987 #define PERIPH_RNCR_RXNCTR_Pos 0 00988 #define PERIPH_RNCR_RXNCTR_Msk (0xffffu << PERIPH_RNCR_RXNCTR_Pos) /* (PERIPH_RNCR) Receive Next Counter */ 00989 #define PERIPH_RNCR_RXNCTR(value) ((PERIPH_RNCR_RXNCTR_Msk & ((value) << PERIPH_RNCR_RXNCTR_Pos))) 00990 /* -------- PERIPH_TNPR : (PDC Offset: 0x118) Transmit Next Pointer Register -------- */ 00991 #define PERIPH_TNPR_TXNPTR_Pos 0 00992 #define PERIPH_TNPR_TXNPTR_Msk (0xffffffffu << PERIPH_TNPR_TXNPTR_Pos) /* (PERIPH_TNPR) Transmit Next Pointer */ 00993 #define PERIPH_TNPR_TXNPTR(value) ((PERIPH_TNPR_TXNPTR_Msk & ((value) << PERIPH_TNPR_TXNPTR_Pos))) 00994 /* -------- PERIPH_TNCR : (PDC Offset: 0x11C) Transmit Next Counter Register -------- */ 00995 #define PERIPH_TNCR_TXNCTR_Pos 0 00996 #define PERIPH_TNCR_TXNCTR_Msk (0xffffu << PERIPH_TNCR_TXNCTR_Pos) /* (PERIPH_TNCR) Transmit Counter Next */ 00997 #define PERIPH_TNCR_TXNCTR(value) ((PERIPH_TNCR_TXNCTR_Msk & ((value) << PERIPH_TNCR_TXNCTR_Pos))) 00998 /* -------- PERIPH_PTCR : (PDC Offset: 0x120) Transfer Control Register -------- */ 00999 #define PERIPH_PTCR_RXTEN (0x1u << 0) /* (PERIPH_PTCR) Receiver Transfer Enable */ 01000 #define PERIPH_PTCR_RXTDIS (0x1u << 1) /* (PERIPH_PTCR) Receiver Transfer Disable */ 01001 #define PERIPH_PTCR_TXTEN (0x1u << 8) /* (PERIPH_PTCR) Transmitter Transfer Enable */ 01002 #define PERIPH_PTCR_TXTDIS (0x1u << 9) /* (PERIPH_PTCR) Transmitter Transfer Disable */ 01003 /* -------- PERIPH_PTSR : (PDC Offset: 0x124) Transfer Status Register -------- */ 01004 #define PERIPH_PTSR_RXTEN (0x1u << 0) /* (PERIPH_PTSR) Receiver Transfer Enable */ 01005 #define PERIPH_PTSR_TXTEN (0x1u << 8) /* (PERIPH_PTSR) Transmitter Transfer Enable */ 01006 01007 01008 /* ============================================================================= */ 01009 /* SOFTWARE API DEFINITION FOR Parallel Input/Output */ 01010 /* ============================================================================= */ 01011 01012 #ifndef __ASSEMBLY__ 01013 /* Pio hardware registers */ 01014 typedef struct { 01015 WoReg PIO_PER; /* (Pio Offset: 0x0000) PIO Enable Register */ 01016 WoReg PIO_PDR; /* (Pio Offset: 0x0004) PIO Disable Register */ 01017 RoReg PIO_PSR; /* (Pio Offset: 0x0008) PIO Status Register */ 01018 RwReg Reserved1[1]; 01019 WoReg PIO_OER; /* (Pio Offset: 0x0010) Output Enable Register */ 01020 WoReg PIO_ODR; /* (Pio Offset: 0x0014) Output Disable Register */ 01021 RoReg PIO_OSR; /* (Pio Offset: 0x0018) Output Status Register */ 01022 RwReg Reserved2[1]; 01023 WoReg PIO_IFER; /* (Pio Offset: 0x0020) Glitch Input Filter Enable Register */ 01024 WoReg PIO_IFDR; /* (Pio Offset: 0x0024) Glitch Input Filter Disable Register */ 01025 RoReg PIO_IFSR; /* (Pio Offset: 0x0028) Glitch Input Filter Status Register */ 01026 RwReg Reserved3[1]; 01027 WoReg PIO_SODR; /* (Pio Offset: 0x0030) Set Output Data Register */ 01028 WoReg PIO_CODR; /* (Pio Offset: 0x0034) Clear Output Data Register */ 01029 RwReg PIO_ODSR; /* (Pio Offset: 0x0038) Output Data Status Register */ 01030 RoReg PIO_PDSR; /* (Pio Offset: 0x003C) Pin Data Status Register */ 01031 WoReg PIO_IER; /* (Pio Offset: 0x0040) Interrupt Enable Register */ 01032 WoReg PIO_IDR; /* (Pio Offset: 0x0044) Interrupt Disable Register */ 01033 RoReg PIO_IMR; /* (Pio Offset: 0x0048) Interrupt Mask Register */ 01034 RoReg PIO_ISR; /* (Pio Offset: 0x004C) Interrupt Status Register */ 01035 WoReg PIO_MDER; /* (Pio Offset: 0x0050) Multi-driver Enable Register */ 01036 WoReg PIO_MDDR; /* (Pio Offset: 0x0054) Multi-driver Disable Register */ 01037 RoReg PIO_MDSR; /* (Pio Offset: 0x0058) Multi-driver Status Register */ 01038 RwReg Reserved4[1]; 01039 WoReg PIO_PUDR; /* (Pio Offset: 0x0060) Pull-up Disable Register */ 01040 WoReg PIO_PUER; /* (Pio Offset: 0x0064) Pull-up Enable Register */ 01041 RoReg PIO_PUSR; /* (Pio Offset: 0x0068) Pad Pull-up Status Register */ 01042 RwReg Reserved5[1]; 01043 RwReg PIO_ABCDSR[2]; /* (Pio Offset: 0x0070) Peripheral Select Register */ 01044 RwReg Reserved6[2]; 01045 WoReg PIO_IFSCDR; /* (Pio Offset: 0x0080) Input Filter Slow Clock Disable Register */ 01046 WoReg PIO_IFSCER; /* (Pio Offset: 0x0084) Input Filter Slow Clock Enable Register */ 01047 RoReg PIO_IFSCSR; /* (Pio Offset: 0x0088) Input Filter Slow Clock Status Register */ 01048 RwReg PIO_SCDR; /* (Pio Offset: 0x008C) Slow Clock Divider Debouncing Register */ 01049 WoReg PIO_PPDDR; /* (Pio Offset: 0x0090) Pad Pull-down Disable Register */ 01050 WoReg PIO_PPDER; /* (Pio Offset: 0x0094) Pad Pull-down Enable Register */ 01051 RoReg PIO_PPDSR; /* (Pio Offset: 0x0098) Pad Pull-down Status Register */ 01052 RwReg Reserved7[1]; 01053 WoReg PIO_OWER; /* (Pio Offset: 0x00A0) Output Write Enable */ 01054 WoReg PIO_OWDR; /* (Pio Offset: 0x00A4) Output Write Disable */ 01055 RoReg PIO_OWSR; /* (Pio Offset: 0x00A8) Output Write Status Register */ 01056 RwReg Reserved8[1]; 01057 WoReg PIO_AIMER; /* (Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register */ 01058 WoReg PIO_AIMDR; /* (Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register */ 01059 RoReg PIO_AIMMR; /* (Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register */ 01060 RwReg Reserved9[1]; 01061 WoReg PIO_ESR; /* (Pio Offset: 0x00C0) Edge Select Register */ 01062 WoReg PIO_LSR; /* (Pio Offset: 0x00C4) Level Select Register */ 01063 RoReg PIO_ELSR; /* (Pio Offset: 0x00C8) Edge/Level Status Register */ 01064 RwReg Reserved10[1]; 01065 WoReg PIO_FELLSR; /* (Pio Offset: 0x00D0) Falling Edge/Low Level Select Register */ 01066 WoReg PIO_REHLSR; /* (Pio Offset: 0x00D4) Rising Edge/ High Level Select Register */ 01067 RoReg PIO_FRLHSR; /* (Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register */ 01068 RwReg Reserved11[1]; 01069 RoReg PIO_LOCKSR; /* (Pio Offset: 0x00E0) Lock Status */ 01070 RwReg PIO_WPMR; /* (Pio Offset: 0x00E4) Write Protect Mode Register */ 01071 RoReg PIO_WPSR; /* (Pio Offset: 0x00E8) Write Protect Status Register */ 01072 RwReg Reserved12[5]; 01073 RwReg PIO_SCHMITT; /* (Pio Offset: 0x0100) Schmitt Trigger Register */ 01074 } Pio; 01075 #endif /* __ASSEMBLY__ */ 01076 /* -------- PIO_PER : (PIO Offset: 0x0000) PIO Enable Register -------- */ 01077 #define PIO_PER_P0 (0x1u << 0) /* (PIO_PER) PIO Enable */ 01078 #define PIO_PER_P1 (0x1u << 1) /* (PIO_PER) PIO Enable */ 01079 #define PIO_PER_P2 (0x1u << 2) /* (PIO_PER) PIO Enable */ 01080 #define PIO_PER_P3 (0x1u << 3) /* (PIO_PER) PIO Enable */ 01081 #define PIO_PER_P4 (0x1u << 4) /* (PIO_PER) PIO Enable */ 01082 #define PIO_PER_P5 (0x1u << 5) /* (PIO_PER) PIO Enable */ 01083 #define PIO_PER_P6 (0x1u << 6) /* (PIO_PER) PIO Enable */ 01084 #define PIO_PER_P7 (0x1u << 7) /* (PIO_PER) PIO Enable */ 01085 #define PIO_PER_P8 (0x1u << 8) /* (PIO_PER) PIO Enable */ 01086 #define PIO_PER_P9 (0x1u << 9) /* (PIO_PER) PIO Enable */ 01087 #define PIO_PER_P10 (0x1u << 10) /* (PIO_PER) PIO Enable */ 01088 #define PIO_PER_P11 (0x1u << 11) /* (PIO_PER) PIO Enable */ 01089 #define PIO_PER_P12 (0x1u << 12) /* (PIO_PER) PIO Enable */ 01090 #define PIO_PER_P13 (0x1u << 13) /* (PIO_PER) PIO Enable */ 01091 #define PIO_PER_P14 (0x1u << 14) /* (PIO_PER) PIO Enable */ 01092 #define PIO_PER_P15 (0x1u << 15) /* (PIO_PER) PIO Enable */ 01093 #define PIO_PER_P16 (0x1u << 16) /* (PIO_PER) PIO Enable */ 01094 #define PIO_PER_P17 (0x1u << 17) /* (PIO_PER) PIO Enable */ 01095 #define PIO_PER_P18 (0x1u << 18) /* (PIO_PER) PIO Enable */ 01096 #define PIO_PER_P19 (0x1u << 19) /* (PIO_PER) PIO Enable */ 01097 #define PIO_PER_P20 (0x1u << 20) /* (PIO_PER) PIO Enable */ 01098 #define PIO_PER_P21 (0x1u << 21) /* (PIO_PER) PIO Enable */ 01099 #define PIO_PER_P22 (0x1u << 22) /* (PIO_PER) PIO Enable */ 01100 #define PIO_PER_P23 (0x1u << 23) /* (PIO_PER) PIO Enable */ 01101 #define PIO_PER_P24 (0x1u << 24) /* (PIO_PER) PIO Enable */ 01102 #define PIO_PER_P25 (0x1u << 25) /* (PIO_PER) PIO Enable */ 01103 #define PIO_PER_P26 (0x1u << 26) /* (PIO_PER) PIO Enable */ 01104 #define PIO_PER_P27 (0x1u << 27) /* (PIO_PER) PIO Enable */ 01105 #define PIO_PER_P28 (0x1u << 28) /* (PIO_PER) PIO Enable */ 01106 #define PIO_PER_P29 (0x1u << 29) /* (PIO_PER) PIO Enable */ 01107 #define PIO_PER_P30 (0x1u << 30) /* (PIO_PER) PIO Enable */ 01108 #define PIO_PER_P31 (0x1u << 31) /* (PIO_PER) PIO Enable */ 01109 /* -------- PIO_PDR : (PIO Offset: 0x0004) PIO Disable Register -------- */ 01110 #define PIO_PDR_P0 (0x1u << 0) /* (PIO_PDR) PIO Disable */ 01111 #define PIO_PDR_P1 (0x1u << 1) /* (PIO_PDR) PIO Disable */ 01112 #define PIO_PDR_P2 (0x1u << 2) /* (PIO_PDR) PIO Disable */ 01113 #define PIO_PDR_P3 (0x1u << 3) /* (PIO_PDR) PIO Disable */ 01114 #define PIO_PDR_P4 (0x1u << 4) /* (PIO_PDR) PIO Disable */ 01115 #define PIO_PDR_P5 (0x1u << 5) /* (PIO_PDR) PIO Disable */ 01116 #define PIO_PDR_P6 (0x1u << 6) /* (PIO_PDR) PIO Disable */ 01117 #define PIO_PDR_P7 (0x1u << 7) /* (PIO_PDR) PIO Disable */ 01118 #define PIO_PDR_P8 (0x1u << 8) /* (PIO_PDR) PIO Disable */ 01119 #define PIO_PDR_P9 (0x1u << 9) /* (PIO_PDR) PIO Disable */ 01120 #define PIO_PDR_P10 (0x1u << 10) /* (PIO_PDR) PIO Disable */ 01121 #define PIO_PDR_P11 (0x1u << 11) /* (PIO_PDR) PIO Disable */ 01122 #define PIO_PDR_P12 (0x1u << 12) /* (PIO_PDR) PIO Disable */ 01123 #define PIO_PDR_P13 (0x1u << 13) /* (PIO_PDR) PIO Disable */ 01124 #define PIO_PDR_P14 (0x1u << 14) /* (PIO_PDR) PIO Disable */ 01125 #define PIO_PDR_P15 (0x1u << 15) /* (PIO_PDR) PIO Disable */ 01126 #define PIO_PDR_P16 (0x1u << 16) /* (PIO_PDR) PIO Disable */ 01127 #define PIO_PDR_P17 (0x1u << 17) /* (PIO_PDR) PIO Disable */ 01128 #define PIO_PDR_P18 (0x1u << 18) /* (PIO_PDR) PIO Disable */ 01129 #define PIO_PDR_P19 (0x1u << 19) /* (PIO_PDR) PIO Disable */ 01130 #define PIO_PDR_P20 (0x1u << 20) /* (PIO_PDR) PIO Disable */ 01131 #define PIO_PDR_P21 (0x1u << 21) /* (PIO_PDR) PIO Disable */ 01132 #define PIO_PDR_P22 (0x1u << 22) /* (PIO_PDR) PIO Disable */ 01133 #define PIO_PDR_P23 (0x1u << 23) /* (PIO_PDR) PIO Disable */ 01134 #define PIO_PDR_P24 (0x1u << 24) /* (PIO_PDR) PIO Disable */ 01135 #define PIO_PDR_P25 (0x1u << 25) /* (PIO_PDR) PIO Disable */ 01136 #define PIO_PDR_P26 (0x1u << 26) /* (PIO_PDR) PIO Disable */ 01137 #define PIO_PDR_P27 (0x1u << 27) /* (PIO_PDR) PIO Disable */ 01138 #define PIO_PDR_P28 (0x1u << 28) /* (PIO_PDR) PIO Disable */ 01139 #define PIO_PDR_P29 (0x1u << 29) /* (PIO_PDR) PIO Disable */ 01140 #define PIO_PDR_P30 (0x1u << 30) /* (PIO_PDR) PIO Disable */ 01141 #define PIO_PDR_P31 (0x1u << 31) /* (PIO_PDR) PIO Disable */ 01142 /* -------- PIO_PSR : (PIO Offset: 0x0008) PIO Status Register -------- */ 01143 #define PIO_PSR_P0 (0x1u << 0) /* (PIO_PSR) PIO Status */ 01144 #define PIO_PSR_P1 (0x1u << 1) /* (PIO_PSR) PIO Status */ 01145 #define PIO_PSR_P2 (0x1u << 2) /* (PIO_PSR) PIO Status */ 01146 #define PIO_PSR_P3 (0x1u << 3) /* (PIO_PSR) PIO Status */ 01147 #define PIO_PSR_P4 (0x1u << 4) /* (PIO_PSR) PIO Status */ 01148 #define PIO_PSR_P5 (0x1u << 5) /* (PIO_PSR) PIO Status */ 01149 #define PIO_PSR_P6 (0x1u << 6) /* (PIO_PSR) PIO Status */ 01150 #define PIO_PSR_P7 (0x1u << 7) /* (PIO_PSR) PIO Status */ 01151 #define PIO_PSR_P8 (0x1u << 8) /* (PIO_PSR) PIO Status */ 01152 #define PIO_PSR_P9 (0x1u << 9) /* (PIO_PSR) PIO Status */ 01153 #define PIO_PSR_P10 (0x1u << 10) /* (PIO_PSR) PIO Status */ 01154 #define PIO_PSR_P11 (0x1u << 11) /* (PIO_PSR) PIO Status */ 01155 #define PIO_PSR_P12 (0x1u << 12) /* (PIO_PSR) PIO Status */ 01156 #define PIO_PSR_P13 (0x1u << 13) /* (PIO_PSR) PIO Status */ 01157 #define PIO_PSR_P14 (0x1u << 14) /* (PIO_PSR) PIO Status */ 01158 #define PIO_PSR_P15 (0x1u << 15) /* (PIO_PSR) PIO Status */ 01159 #define PIO_PSR_P16 (0x1u << 16) /* (PIO_PSR) PIO Status */ 01160 #define PIO_PSR_P17 (0x1u << 17) /* (PIO_PSR) PIO Status */ 01161 #define PIO_PSR_P18 (0x1u << 18) /* (PIO_PSR) PIO Status */ 01162 #define PIO_PSR_P19 (0x1u << 19) /* (PIO_PSR) PIO Status */ 01163 #define PIO_PSR_P20 (0x1u << 20) /* (PIO_PSR) PIO Status */ 01164 #define PIO_PSR_P21 (0x1u << 21) /* (PIO_PSR) PIO Status */ 01165 #define PIO_PSR_P22 (0x1u << 22) /* (PIO_PSR) PIO Status */ 01166 #define PIO_PSR_P23 (0x1u << 23) /* (PIO_PSR) PIO Status */ 01167 #define PIO_PSR_P24 (0x1u << 24) /* (PIO_PSR) PIO Status */ 01168 #define PIO_PSR_P25 (0x1u << 25) /* (PIO_PSR) PIO Status */ 01169 #define PIO_PSR_P26 (0x1u << 26) /* (PIO_PSR) PIO Status */ 01170 #define PIO_PSR_P27 (0x1u << 27) /* (PIO_PSR) PIO Status */ 01171 #define PIO_PSR_P28 (0x1u << 28) /* (PIO_PSR) PIO Status */ 01172 #define PIO_PSR_P29 (0x1u << 29) /* (PIO_PSR) PIO Status */ 01173 #define PIO_PSR_P30 (0x1u << 30) /* (PIO_PSR) PIO Status */ 01174 #define PIO_PSR_P31 (0x1u << 31) /* (PIO_PSR) PIO Status */ 01175 /* -------- PIO_OER : (PIO Offset: 0x0010) Output Enable Register -------- */ 01176 #define PIO_OER_P0 (0x1u << 0) /* (PIO_OER) Output Enable */ 01177 #define PIO_OER_P1 (0x1u << 1) /* (PIO_OER) Output Enable */ 01178 #define PIO_OER_P2 (0x1u << 2) /* (PIO_OER) Output Enable */ 01179 #define PIO_OER_P3 (0x1u << 3) /* (PIO_OER) Output Enable */ 01180 #define PIO_OER_P4 (0x1u << 4) /* (PIO_OER) Output Enable */ 01181 #define PIO_OER_P5 (0x1u << 5) /* (PIO_OER) Output Enable */ 01182 #define PIO_OER_P6 (0x1u << 6) /* (PIO_OER) Output Enable */ 01183 #define PIO_OER_P7 (0x1u << 7) /* (PIO_OER) Output Enable */ 01184 #define PIO_OER_P8 (0x1u << 8) /* (PIO_OER) Output Enable */ 01185 #define PIO_OER_P9 (0x1u << 9) /* (PIO_OER) Output Enable */ 01186 #define PIO_OER_P10 (0x1u << 10) /* (PIO_OER) Output Enable */ 01187 #define PIO_OER_P11 (0x1u << 11) /* (PIO_OER) Output Enable */ 01188 #define PIO_OER_P12 (0x1u << 12) /* (PIO_OER) Output Enable */ 01189 #define PIO_OER_P13 (0x1u << 13) /* (PIO_OER) Output Enable */ 01190 #define PIO_OER_P14 (0x1u << 14) /* (PIO_OER) Output Enable */ 01191 #define PIO_OER_P15 (0x1u << 15) /* (PIO_OER) Output Enable */ 01192 #define PIO_OER_P16 (0x1u << 16) /* (PIO_OER) Output Enable */ 01193 #define PIO_OER_P17 (0x1u << 17) /* (PIO_OER) Output Enable */ 01194 #define PIO_OER_P18 (0x1u << 18) /* (PIO_OER) Output Enable */ 01195 #define PIO_OER_P19 (0x1u << 19) /* (PIO_OER) Output Enable */ 01196 #define PIO_OER_P20 (0x1u << 20) /* (PIO_OER) Output Enable */ 01197 #define PIO_OER_P21 (0x1u << 21) /* (PIO_OER) Output Enable */ 01198 #define PIO_OER_P22 (0x1u << 22) /* (PIO_OER) Output Enable */ 01199 #define PIO_OER_P23 (0x1u << 23) /* (PIO_OER) Output Enable */ 01200 #define PIO_OER_P24 (0x1u << 24) /* (PIO_OER) Output Enable */ 01201 #define PIO_OER_P25 (0x1u << 25) /* (PIO_OER) Output Enable */ 01202 #define PIO_OER_P26 (0x1u << 26) /* (PIO_OER) Output Enable */ 01203 #define PIO_OER_P27 (0x1u << 27) /* (PIO_OER) Output Enable */ 01204 #define PIO_OER_P28 (0x1u << 28) /* (PIO_OER) Output Enable */ 01205 #define PIO_OER_P29 (0x1u << 29) /* (PIO_OER) Output Enable */ 01206 #define PIO_OER_P30 (0x1u << 30) /* (PIO_OER) Output Enable */ 01207 #define PIO_OER_P31 (0x1u << 31) /* (PIO_OER) Output Enable */ 01208 /* -------- PIO_ODR : (PIO Offset: 0x0014) Output Disable Register -------- */ 01209 #define PIO_ODR_P0 (0x1u << 0) /* (PIO_ODR) Output Disable */ 01210 #define PIO_ODR_P1 (0x1u << 1) /* (PIO_ODR) Output Disable */ 01211 #define PIO_ODR_P2 (0x1u << 2) /* (PIO_ODR) Output Disable */ 01212 #define PIO_ODR_P3 (0x1u << 3) /* (PIO_ODR) Output Disable */ 01213 #define PIO_ODR_P4 (0x1u << 4) /* (PIO_ODR) Output Disable */ 01214 #define PIO_ODR_P5 (0x1u << 5) /* (PIO_ODR) Output Disable */ 01215 #define PIO_ODR_P6 (0x1u << 6) /* (PIO_ODR) Output Disable */ 01216 #define PIO_ODR_P7 (0x1u << 7) /* (PIO_ODR) Output Disable */ 01217 #define PIO_ODR_P8 (0x1u << 8) /* (PIO_ODR) Output Disable */ 01218 #define PIO_ODR_P9 (0x1u << 9) /* (PIO_ODR) Output Disable */ 01219 #define PIO_ODR_P10 (0x1u << 10) /* (PIO_ODR) Output Disable */ 01220 #define PIO_ODR_P11 (0x1u << 11) /* (PIO_ODR) Output Disable */ 01221 #define PIO_ODR_P12 (0x1u << 12) /* (PIO_ODR) Output Disable */ 01222 #define PIO_ODR_P13 (0x1u << 13) /* (PIO_ODR) Output Disable */ 01223 #define PIO_ODR_P14 (0x1u << 14) /* (PIO_ODR) Output Disable */ 01224 #define PIO_ODR_P15 (0x1u << 15) /* (PIO_ODR) Output Disable */ 01225 #define PIO_ODR_P16 (0x1u << 16) /* (PIO_ODR) Output Disable */ 01226 #define PIO_ODR_P17 (0x1u << 17) /* (PIO_ODR) Output Disable */ 01227 #define PIO_ODR_P18 (0x1u << 18) /* (PIO_ODR) Output Disable */ 01228 #define PIO_ODR_P19 (0x1u << 19) /* (PIO_ODR) Output Disable */ 01229 #define PIO_ODR_P20 (0x1u << 20) /* (PIO_ODR) Output Disable */ 01230 #define PIO_ODR_P21 (0x1u << 21) /* (PIO_ODR) Output Disable */ 01231 #define PIO_ODR_P22 (0x1u << 22) /* (PIO_ODR) Output Disable */ 01232 #define PIO_ODR_P23 (0x1u << 23) /* (PIO_ODR) Output Disable */ 01233 #define PIO_ODR_P24 (0x1u << 24) /* (PIO_ODR) Output Disable */ 01234 #define PIO_ODR_P25 (0x1u << 25) /* (PIO_ODR) Output Disable */ 01235 #define PIO_ODR_P26 (0x1u << 26) /* (PIO_ODR) Output Disable */ 01236 #define PIO_ODR_P27 (0x1u << 27) /* (PIO_ODR) Output Disable */ 01237 #define PIO_ODR_P28 (0x1u << 28) /* (PIO_ODR) Output Disable */ 01238 #define PIO_ODR_P29 (0x1u << 29) /* (PIO_ODR) Output Disable */ 01239 #define PIO_ODR_P30 (0x1u << 30) /* (PIO_ODR) Output Disable */ 01240 #define PIO_ODR_P31 (0x1u << 31) /* (PIO_ODR) Output Disable */ 01241 /* -------- PIO_OSR : (PIO Offset: 0x0018) Output Status Register -------- */ 01242 #define PIO_OSR_P0 (0x1u << 0) /* (PIO_OSR) Output Status */ 01243 #define PIO_OSR_P1 (0x1u << 1) /* (PIO_OSR) Output Status */ 01244 #define PIO_OSR_P2 (0x1u << 2) /* (PIO_OSR) Output Status */ 01245 #define PIO_OSR_P3 (0x1u << 3) /* (PIO_OSR) Output Status */ 01246 #define PIO_OSR_P4 (0x1u << 4) /* (PIO_OSR) Output Status */ 01247 #define PIO_OSR_P5 (0x1u << 5) /* (PIO_OSR) Output Status */ 01248 #define PIO_OSR_P6 (0x1u << 6) /* (PIO_OSR) Output Status */ 01249 #define PIO_OSR_P7 (0x1u << 7) /* (PIO_OSR) Output Status */ 01250 #define PIO_OSR_P8 (0x1u << 8) /* (PIO_OSR) Output Status */ 01251 #define PIO_OSR_P9 (0x1u << 9) /* (PIO_OSR) Output Status */ 01252 #define PIO_OSR_P10 (0x1u << 10) /* (PIO_OSR) Output Status */ 01253 #define PIO_OSR_P11 (0x1u << 11) /* (PIO_OSR) Output Status */ 01254 #define PIO_OSR_P12 (0x1u << 12) /* (PIO_OSR) Output Status */ 01255 #define PIO_OSR_P13 (0x1u << 13) /* (PIO_OSR) Output Status */ 01256 #define PIO_OSR_P14 (0x1u << 14) /* (PIO_OSR) Output Status */ 01257 #define PIO_OSR_P15 (0x1u << 15) /* (PIO_OSR) Output Status */ 01258 #define PIO_OSR_P16 (0x1u << 16) /* (PIO_OSR) Output Status */ 01259 #define PIO_OSR_P17 (0x1u << 17) /* (PIO_OSR) Output Status */ 01260 #define PIO_OSR_P18 (0x1u << 18) /* (PIO_OSR) Output Status */ 01261 #define PIO_OSR_P19 (0x1u << 19) /* (PIO_OSR) Output Status */ 01262 #define PIO_OSR_P20 (0x1u << 20) /* (PIO_OSR) Output Status */ 01263 #define PIO_OSR_P21 (0x1u << 21) /* (PIO_OSR) Output Status */ 01264 #define PIO_OSR_P22 (0x1u << 22) /* (PIO_OSR) Output Status */ 01265 #define PIO_OSR_P23 (0x1u << 23) /* (PIO_OSR) Output Status */ 01266 #define PIO_OSR_P24 (0x1u << 24) /* (PIO_OSR) Output Status */ 01267 #define PIO_OSR_P25 (0x1u << 25) /* (PIO_OSR) Output Status */ 01268 #define PIO_OSR_P26 (0x1u << 26) /* (PIO_OSR) Output Status */ 01269 #define PIO_OSR_P27 (0x1u << 27) /* (PIO_OSR) Output Status */ 01270 #define PIO_OSR_P28 (0x1u << 28) /* (PIO_OSR) Output Status */ 01271 #define PIO_OSR_P29 (0x1u << 29) /* (PIO_OSR) Output Status */ 01272 #define PIO_OSR_P30 (0x1u << 30) /* (PIO_OSR) Output Status */ 01273 #define PIO_OSR_P31 (0x1u << 31) /* (PIO_OSR) Output Status */ 01274 /* -------- PIO_IFER : (PIO Offset: 0x0020) Glitch Input Filter Enable Register -------- */ 01275 #define PIO_IFER_P0 (0x1u << 0) /* (PIO_IFER) Input Filter Enable */ 01276 #define PIO_IFER_P1 (0x1u << 1) /* (PIO_IFER) Input Filter Enable */ 01277 #define PIO_IFER_P2 (0x1u << 2) /* (PIO_IFER) Input Filter Enable */ 01278 #define PIO_IFER_P3 (0x1u << 3) /* (PIO_IFER) Input Filter Enable */ 01279 #define PIO_IFER_P4 (0x1u << 4) /* (PIO_IFER) Input Filter Enable */ 01280 #define PIO_IFER_P5 (0x1u << 5) /* (PIO_IFER) Input Filter Enable */ 01281 #define PIO_IFER_P6 (0x1u << 6) /* (PIO_IFER) Input Filter Enable */ 01282 #define PIO_IFER_P7 (0x1u << 7) /* (PIO_IFER) Input Filter Enable */ 01283 #define PIO_IFER_P8 (0x1u << 8) /* (PIO_IFER) Input Filter Enable */ 01284 #define PIO_IFER_P9 (0x1u << 9) /* (PIO_IFER) Input Filter Enable */ 01285 #define PIO_IFER_P10 (0x1u << 10) /* (PIO_IFER) Input Filter Enable */ 01286 #define PIO_IFER_P11 (0x1u << 11) /* (PIO_IFER) Input Filter Enable */ 01287 #define PIO_IFER_P12 (0x1u << 12) /* (PIO_IFER) Input Filter Enable */ 01288 #define PIO_IFER_P13 (0x1u << 13) /* (PIO_IFER) Input Filter Enable */ 01289 #define PIO_IFER_P14 (0x1u << 14) /* (PIO_IFER) Input Filter Enable */ 01290 #define PIO_IFER_P15 (0x1u << 15) /* (PIO_IFER) Input Filter Enable */ 01291 #define PIO_IFER_P16 (0x1u << 16) /* (PIO_IFER) Input Filter Enable */ 01292 #define PIO_IFER_P17 (0x1u << 17) /* (PIO_IFER) Input Filter Enable */ 01293 #define PIO_IFER_P18 (0x1u << 18) /* (PIO_IFER) Input Filter Enable */ 01294 #define PIO_IFER_P19 (0x1u << 19) /* (PIO_IFER) Input Filter Enable */ 01295 #define PIO_IFER_P20 (0x1u << 20) /* (PIO_IFER) Input Filter Enable */ 01296 #define PIO_IFER_P21 (0x1u << 21) /* (PIO_IFER) Input Filter Enable */ 01297 #define PIO_IFER_P22 (0x1u << 22) /* (PIO_IFER) Input Filter Enable */ 01298 #define PIO_IFER_P23 (0x1u << 23) /* (PIO_IFER) Input Filter Enable */ 01299 #define PIO_IFER_P24 (0x1u << 24) /* (PIO_IFER) Input Filter Enable */ 01300 #define PIO_IFER_P25 (0x1u << 25) /* (PIO_IFER) Input Filter Enable */ 01301 #define PIO_IFER_P26 (0x1u << 26) /* (PIO_IFER) Input Filter Enable */ 01302 #define PIO_IFER_P27 (0x1u << 27) /* (PIO_IFER) Input Filter Enable */ 01303 #define PIO_IFER_P28 (0x1u << 28) /* (PIO_IFER) Input Filter Enable */ 01304 #define PIO_IFER_P29 (0x1u << 29) /* (PIO_IFER) Input Filter Enable */ 01305 #define PIO_IFER_P30 (0x1u << 30) /* (PIO_IFER) Input Filter Enable */ 01306 #define PIO_IFER_P31 (0x1u << 31) /* (PIO_IFER) Input Filter Enable */ 01307 /* -------- PIO_IFDR : (PIO Offset: 0x0024) Glitch Input Filter Disable Register -------- */ 01308 #define PIO_IFDR_P0 (0x1u << 0) /* (PIO_IFDR) Input Filter Disable */ 01309 #define PIO_IFDR_P1 (0x1u << 1) /* (PIO_IFDR) Input Filter Disable */ 01310 #define PIO_IFDR_P2 (0x1u << 2) /* (PIO_IFDR) Input Filter Disable */ 01311 #define PIO_IFDR_P3 (0x1u << 3) /* (PIO_IFDR) Input Filter Disable */ 01312 #define PIO_IFDR_P4 (0x1u << 4) /* (PIO_IFDR) Input Filter Disable */ 01313 #define PIO_IFDR_P5 (0x1u << 5) /* (PIO_IFDR) Input Filter Disable */ 01314 #define PIO_IFDR_P6 (0x1u << 6) /* (PIO_IFDR) Input Filter Disable */ 01315 #define PIO_IFDR_P7 (0x1u << 7) /* (PIO_IFDR) Input Filter Disable */ 01316 #define PIO_IFDR_P8 (0x1u << 8) /* (PIO_IFDR) Input Filter Disable */ 01317 #define PIO_IFDR_P9 (0x1u << 9) /* (PIO_IFDR) Input Filter Disable */ 01318 #define PIO_IFDR_P10 (0x1u << 10) /* (PIO_IFDR) Input Filter Disable */ 01319 #define PIO_IFDR_P11 (0x1u << 11) /* (PIO_IFDR) Input Filter Disable */ 01320 #define PIO_IFDR_P12 (0x1u << 12) /* (PIO_IFDR) Input Filter Disable */ 01321 #define PIO_IFDR_P13 (0x1u << 13) /* (PIO_IFDR) Input Filter Disable */ 01322 #define PIO_IFDR_P14 (0x1u << 14) /* (PIO_IFDR) Input Filter Disable */ 01323 #define PIO_IFDR_P15 (0x1u << 15) /* (PIO_IFDR) Input Filter Disable */ 01324 #define PIO_IFDR_P16 (0x1u << 16) /* (PIO_IFDR) Input Filter Disable */ 01325 #define PIO_IFDR_P17 (0x1u << 17) /* (PIO_IFDR) Input Filter Disable */ 01326 #define PIO_IFDR_P18 (0x1u << 18) /* (PIO_IFDR) Input Filter Disable */ 01327 #define PIO_IFDR_P19 (0x1u << 19) /* (PIO_IFDR) Input Filter Disable */ 01328 #define PIO_IFDR_P20 (0x1u << 20) /* (PIO_IFDR) Input Filter Disable */ 01329 #define PIO_IFDR_P21 (0x1u << 21) /* (PIO_IFDR) Input Filter Disable */ 01330 #define PIO_IFDR_P22 (0x1u << 22) /* (PIO_IFDR) Input Filter Disable */ 01331 #define PIO_IFDR_P23 (0x1u << 23) /* (PIO_IFDR) Input Filter Disable */ 01332 #define PIO_IFDR_P24 (0x1u << 24) /* (PIO_IFDR) Input Filter Disable */ 01333 #define PIO_IFDR_P25 (0x1u << 25) /* (PIO_IFDR) Input Filter Disable */ 01334 #define PIO_IFDR_P26 (0x1u << 26) /* (PIO_IFDR) Input Filter Disable */ 01335 #define PIO_IFDR_P27 (0x1u << 27) /* (PIO_IFDR) Input Filter Disable */ 01336 #define PIO_IFDR_P28 (0x1u << 28) /* (PIO_IFDR) Input Filter Disable */ 01337 #define PIO_IFDR_P29 (0x1u << 29) /* (PIO_IFDR) Input Filter Disable */ 01338 #define PIO_IFDR_P30 (0x1u << 30) /* (PIO_IFDR) Input Filter Disable */ 01339 #define PIO_IFDR_P31 (0x1u << 31) /* (PIO_IFDR) Input Filter Disable */ 01340 /* -------- PIO_IFSR : (PIO Offset: 0x0028) Glitch Input Filter Status Register -------- */ 01341 #define PIO_IFSR_P0 (0x1u << 0) /* (PIO_IFSR) Input Filer Status */ 01342 #define PIO_IFSR_P1 (0x1u << 1) /* (PIO_IFSR) Input Filer Status */ 01343 #define PIO_IFSR_P2 (0x1u << 2) /* (PIO_IFSR) Input Filer Status */ 01344 #define PIO_IFSR_P3 (0x1u << 3) /* (PIO_IFSR) Input Filer Status */ 01345 #define PIO_IFSR_P4 (0x1u << 4) /* (PIO_IFSR) Input Filer Status */ 01346 #define PIO_IFSR_P5 (0x1u << 5) /* (PIO_IFSR) Input Filer Status */ 01347 #define PIO_IFSR_P6 (0x1u << 6) /* (PIO_IFSR) Input Filer Status */ 01348 #define PIO_IFSR_P7 (0x1u << 7) /* (PIO_IFSR) Input Filer Status */ 01349 #define PIO_IFSR_P8 (0x1u << 8) /* (PIO_IFSR) Input Filer Status */ 01350 #define PIO_IFSR_P9 (0x1u << 9) /* (PIO_IFSR) Input Filer Status */ 01351 #define PIO_IFSR_P10 (0x1u << 10) /* (PIO_IFSR) Input Filer Status */ 01352 #define PIO_IFSR_P11 (0x1u << 11) /* (PIO_IFSR) Input Filer Status */ 01353 #define PIO_IFSR_P12 (0x1u << 12) /* (PIO_IFSR) Input Filer Status */ 01354 #define PIO_IFSR_P13 (0x1u << 13) /* (PIO_IFSR) Input Filer Status */ 01355 #define PIO_IFSR_P14 (0x1u << 14) /* (PIO_IFSR) Input Filer Status */ 01356 #define PIO_IFSR_P15 (0x1u << 15) /* (PIO_IFSR) Input Filer Status */ 01357 #define PIO_IFSR_P16 (0x1u << 16) /* (PIO_IFSR) Input Filer Status */ 01358 #define PIO_IFSR_P17 (0x1u << 17) /* (PIO_IFSR) Input Filer Status */ 01359 #define PIO_IFSR_P18 (0x1u << 18) /* (PIO_IFSR) Input Filer Status */ 01360 #define PIO_IFSR_P19 (0x1u << 19) /* (PIO_IFSR) Input Filer Status */ 01361 #define PIO_IFSR_P20 (0x1u << 20) /* (PIO_IFSR) Input Filer Status */ 01362 #define PIO_IFSR_P21 (0x1u << 21) /* (PIO_IFSR) Input Filer Status */ 01363 #define PIO_IFSR_P22 (0x1u << 22) /* (PIO_IFSR) Input Filer Status */ 01364 #define PIO_IFSR_P23 (0x1u << 23) /* (PIO_IFSR) Input Filer Status */ 01365 #define PIO_IFSR_P24 (0x1u << 24) /* (PIO_IFSR) Input Filer Status */ 01366 #define PIO_IFSR_P25 (0x1u << 25) /* (PIO_IFSR) Input Filer Status */ 01367 #define PIO_IFSR_P26 (0x1u << 26) /* (PIO_IFSR) Input Filer Status */ 01368 #define PIO_IFSR_P27 (0x1u << 27) /* (PIO_IFSR) Input Filer Status */ 01369 #define PIO_IFSR_P28 (0x1u << 28) /* (PIO_IFSR) Input Filer Status */ 01370 #define PIO_IFSR_P29 (0x1u << 29) /* (PIO_IFSR) Input Filer Status */ 01371 #define PIO_IFSR_P30 (0x1u << 30) /* (PIO_IFSR) Input Filer Status */ 01372 #define PIO_IFSR_P31 (0x1u << 31) /* (PIO_IFSR) Input Filer Status */ 01373 /* -------- PIO_SODR : (PIO Offset: 0x0030) Set Output Data Register -------- */ 01374 #define PIO_SODR_P0 (0x1u << 0) /* (PIO_SODR) Set Output Data */ 01375 #define PIO_SODR_P1 (0x1u << 1) /* (PIO_SODR) Set Output Data */ 01376 #define PIO_SODR_P2 (0x1u << 2) /* (PIO_SODR) Set Output Data */ 01377 #define PIO_SODR_P3 (0x1u << 3) /* (PIO_SODR) Set Output Data */ 01378 #define PIO_SODR_P4 (0x1u << 4) /* (PIO_SODR) Set Output Data */ 01379 #define PIO_SODR_P5 (0x1u << 5) /* (PIO_SODR) Set Output Data */ 01380 #define PIO_SODR_P6 (0x1u << 6) /* (PIO_SODR) Set Output Data */ 01381 #define PIO_SODR_P7 (0x1u << 7) /* (PIO_SODR) Set Output Data */ 01382 #define PIO_SODR_P8 (0x1u << 8) /* (PIO_SODR) Set Output Data */ 01383 #define PIO_SODR_P9 (0x1u << 9) /* (PIO_SODR) Set Output Data */ 01384 #define PIO_SODR_P10 (0x1u << 10) /* (PIO_SODR) Set Output Data */ 01385 #define PIO_SODR_P11 (0x1u << 11) /* (PIO_SODR) Set Output Data */ 01386 #define PIO_SODR_P12 (0x1u << 12) /* (PIO_SODR) Set Output Data */ 01387 #define PIO_SODR_P13 (0x1u << 13) /* (PIO_SODR) Set Output Data */ 01388 #define PIO_SODR_P14 (0x1u << 14) /* (PIO_SODR) Set Output Data */ 01389 #define PIO_SODR_P15 (0x1u << 15) /* (PIO_SODR) Set Output Data */ 01390 #define PIO_SODR_P16 (0x1u << 16) /* (PIO_SODR) Set Output Data */ 01391 #define PIO_SODR_P17 (0x1u << 17) /* (PIO_SODR) Set Output Data */ 01392 #define PIO_SODR_P18 (0x1u << 18) /* (PIO_SODR) Set Output Data */ 01393 #define PIO_SODR_P19 (0x1u << 19) /* (PIO_SODR) Set Output Data */ 01394 #define PIO_SODR_P20 (0x1u << 20) /* (PIO_SODR) Set Output Data */ 01395 #define PIO_SODR_P21 (0x1u << 21) /* (PIO_SODR) Set Output Data */ 01396 #define PIO_SODR_P22 (0x1u << 22) /* (PIO_SODR) Set Output Data */ 01397 #define PIO_SODR_P23 (0x1u << 23) /* (PIO_SODR) Set Output Data */ 01398 #define PIO_SODR_P24 (0x1u << 24) /* (PIO_SODR) Set Output Data */ 01399 #define PIO_SODR_P25 (0x1u << 25) /* (PIO_SODR) Set Output Data */ 01400 #define PIO_SODR_P26 (0x1u << 26) /* (PIO_SODR) Set Output Data */ 01401 #define PIO_SODR_P27 (0x1u << 27) /* (PIO_SODR) Set Output Data */ 01402 #define PIO_SODR_P28 (0x1u << 28) /* (PIO_SODR) Set Output Data */ 01403 #define PIO_SODR_P29 (0x1u << 29) /* (PIO_SODR) Set Output Data */ 01404 #define PIO_SODR_P30 (0x1u << 30) /* (PIO_SODR) Set Output Data */ 01405 #define PIO_SODR_P31 (0x1u << 31) /* (PIO_SODR) Set Output Data */ 01406 /* -------- PIO_CODR : (PIO Offset: 0x0034) Clear Output Data Register -------- */ 01407 #define PIO_CODR_P0 (0x1u << 0) /* (PIO_CODR) Clear Output Data */ 01408 #define PIO_CODR_P1 (0x1u << 1) /* (PIO_CODR) Clear Output Data */ 01409 #define PIO_CODR_P2 (0x1u << 2) /* (PIO_CODR) Clear Output Data */ 01410 #define PIO_CODR_P3 (0x1u << 3) /* (PIO_CODR) Clear Output Data */ 01411 #define PIO_CODR_P4 (0x1u << 4) /* (PIO_CODR) Clear Output Data */ 01412 #define PIO_CODR_P5 (0x1u << 5) /* (PIO_CODR) Clear Output Data */ 01413 #define PIO_CODR_P6 (0x1u << 6) /* (PIO_CODR) Clear Output Data */ 01414 #define PIO_CODR_P7 (0x1u << 7) /* (PIO_CODR) Clear Output Data */ 01415 #define PIO_CODR_P8 (0x1u << 8) /* (PIO_CODR) Clear Output Data */ 01416 #define PIO_CODR_P9 (0x1u << 9) /* (PIO_CODR) Clear Output Data */ 01417 #define PIO_CODR_P10 (0x1u << 10) /* (PIO_CODR) Clear Output Data */ 01418 #define PIO_CODR_P11 (0x1u << 11) /* (PIO_CODR) Clear Output Data */ 01419 #define PIO_CODR_P12 (0x1u << 12) /* (PIO_CODR) Clear Output Data */ 01420 #define PIO_CODR_P13 (0x1u << 13) /* (PIO_CODR) Clear Output Data */ 01421 #define PIO_CODR_P14 (0x1u << 14) /* (PIO_CODR) Clear Output Data */ 01422 #define PIO_CODR_P15 (0x1u << 15) /* (PIO_CODR) Clear Output Data */ 01423 #define PIO_CODR_P16 (0x1u << 16) /* (PIO_CODR) Clear Output Data */ 01424 #define PIO_CODR_P17 (0x1u << 17) /* (PIO_CODR) Clear Output Data */ 01425 #define PIO_CODR_P18 (0x1u << 18) /* (PIO_CODR) Clear Output Data */ 01426 #define PIO_CODR_P19 (0x1u << 19) /* (PIO_CODR) Clear Output Data */ 01427 #define PIO_CODR_P20 (0x1u << 20) /* (PIO_CODR) Clear Output Data */ 01428 #define PIO_CODR_P21 (0x1u << 21) /* (PIO_CODR) Clear Output Data */ 01429 #define PIO_CODR_P22 (0x1u << 22) /* (PIO_CODR) Clear Output Data */ 01430 #define PIO_CODR_P23 (0x1u << 23) /* (PIO_CODR) Clear Output Data */ 01431 #define PIO_CODR_P24 (0x1u << 24) /* (PIO_CODR) Clear Output Data */ 01432 #define PIO_CODR_P25 (0x1u << 25) /* (PIO_CODR) Clear Output Data */ 01433 #define PIO_CODR_P26 (0x1u << 26) /* (PIO_CODR) Clear Output Data */ 01434 #define PIO_CODR_P27 (0x1u << 27) /* (PIO_CODR) Clear Output Data */ 01435 #define PIO_CODR_P28 (0x1u << 28) /* (PIO_CODR) Clear Output Data */ 01436 #define PIO_CODR_P29 (0x1u << 29) /* (PIO_CODR) Clear Output Data */ 01437 #define PIO_CODR_P30 (0x1u << 30) /* (PIO_CODR) Clear Output Data */ 01438 #define PIO_CODR_P31 (0x1u << 31) /* (PIO_CODR) Clear Output Data */ 01439 /* -------- PIO_ODSR : (PIO Offset: 0x0038) Output Data Status Register -------- */ 01440 #define PIO_ODSR_P0 (0x1u << 0) /* (PIO_ODSR) Output Data Status */ 01441 #define PIO_ODSR_P1 (0x1u << 1) /* (PIO_ODSR) Output Data Status */ 01442 #define PIO_ODSR_P2 (0x1u << 2) /* (PIO_ODSR) Output Data Status */ 01443 #define PIO_ODSR_P3 (0x1u << 3) /* (PIO_ODSR) Output Data Status */ 01444 #define PIO_ODSR_P4 (0x1u << 4) /* (PIO_ODSR) Output Data Status */ 01445 #define PIO_ODSR_P5 (0x1u << 5) /* (PIO_ODSR) Output Data Status */ 01446 #define PIO_ODSR_P6 (0x1u << 6) /* (PIO_ODSR) Output Data Status */ 01447 #define PIO_ODSR_P7 (0x1u << 7) /* (PIO_ODSR) Output Data Status */ 01448 #define PIO_ODSR_P8 (0x1u << 8) /* (PIO_ODSR) Output Data Status */ 01449 #define PIO_ODSR_P9 (0x1u << 9) /* (PIO_ODSR) Output Data Status */ 01450 #define PIO_ODSR_P10 (0x1u << 10) /* (PIO_ODSR) Output Data Status */ 01451 #define PIO_ODSR_P11 (0x1u << 11) /* (PIO_ODSR) Output Data Status */ 01452 #define PIO_ODSR_P12 (0x1u << 12) /* (PIO_ODSR) Output Data Status */ 01453 #define PIO_ODSR_P13 (0x1u << 13) /* (PIO_ODSR) Output Data Status */ 01454 #define PIO_ODSR_P14 (0x1u << 14) /* (PIO_ODSR) Output Data Status */ 01455 #define PIO_ODSR_P15 (0x1u << 15) /* (PIO_ODSR) Output Data Status */ 01456 #define PIO_ODSR_P16 (0x1u << 16) /* (PIO_ODSR) Output Data Status */ 01457 #define PIO_ODSR_P17 (0x1u << 17) /* (PIO_ODSR) Output Data Status */ 01458 #define PIO_ODSR_P18 (0x1u << 18) /* (PIO_ODSR) Output Data Status */ 01459 #define PIO_ODSR_P19 (0x1u << 19) /* (PIO_ODSR) Output Data Status */ 01460 #define PIO_ODSR_P20 (0x1u << 20) /* (PIO_ODSR) Output Data Status */ 01461 #define PIO_ODSR_P21 (0x1u << 21) /* (PIO_ODSR) Output Data Status */ 01462 #define PIO_ODSR_P22 (0x1u << 22) /* (PIO_ODSR) Output Data Status */ 01463 #define PIO_ODSR_P23 (0x1u << 23) /* (PIO_ODSR) Output Data Status */ 01464 #define PIO_ODSR_P24 (0x1u << 24) /* (PIO_ODSR) Output Data Status */ 01465 #define PIO_ODSR_P25 (0x1u << 25) /* (PIO_ODSR) Output Data Status */ 01466 #define PIO_ODSR_P26 (0x1u << 26) /* (PIO_ODSR) Output Data Status */ 01467 #define PIO_ODSR_P27 (0x1u << 27) /* (PIO_ODSR) Output Data Status */ 01468 #define PIO_ODSR_P28 (0x1u << 28) /* (PIO_ODSR) Output Data Status */ 01469 #define PIO_ODSR_P29 (0x1u << 29) /* (PIO_ODSR) Output Data Status */ 01470 #define PIO_ODSR_P30 (0x1u << 30) /* (PIO_ODSR) Output Data Status */ 01471 #define PIO_ODSR_P31 (0x1u << 31) /* (PIO_ODSR) Output Data Status */ 01472 /* -------- PIO_PDSR : (PIO Offset: 0x003C) Pin Data Status Register -------- */ 01473 #define PIO_PDSR_P0 (0x1u << 0) /* (PIO_PDSR) Output Data Status */ 01474 #define PIO_PDSR_P1 (0x1u << 1) /* (PIO_PDSR) Output Data Status */ 01475 #define PIO_PDSR_P2 (0x1u << 2) /* (PIO_PDSR) Output Data Status */ 01476 #define PIO_PDSR_P3 (0x1u << 3) /* (PIO_PDSR) Output Data Status */ 01477 #define PIO_PDSR_P4 (0x1u << 4) /* (PIO_PDSR) Output Data Status */ 01478 #define PIO_PDSR_P5 (0x1u << 5) /* (PIO_PDSR) Output Data Status */ 01479 #define PIO_PDSR_P6 (0x1u << 6) /* (PIO_PDSR) Output Data Status */ 01480 #define PIO_PDSR_P7 (0x1u << 7) /* (PIO_PDSR) Output Data Status */ 01481 #define PIO_PDSR_P8 (0x1u << 8) /* (PIO_PDSR) Output Data Status */ 01482 #define PIO_PDSR_P9 (0x1u << 9) /* (PIO_PDSR) Output Data Status */ 01483 #define PIO_PDSR_P10 (0x1u << 10) /* (PIO_PDSR) Output Data Status */ 01484 #define PIO_PDSR_P11 (0x1u << 11) /* (PIO_PDSR) Output Data Status */ 01485 #define PIO_PDSR_P12 (0x1u << 12) /* (PIO_PDSR) Output Data Status */ 01486 #define PIO_PDSR_P13 (0x1u << 13) /* (PIO_PDSR) Output Data Status */ 01487 #define PIO_PDSR_P14 (0x1u << 14) /* (PIO_PDSR) Output Data Status */ 01488 #define PIO_PDSR_P15 (0x1u << 15) /* (PIO_PDSR) Output Data Status */ 01489 #define PIO_PDSR_P16 (0x1u << 16) /* (PIO_PDSR) Output Data Status */ 01490 #define PIO_PDSR_P17 (0x1u << 17) /* (PIO_PDSR) Output Data Status */ 01491 #define PIO_PDSR_P18 (0x1u << 18) /* (PIO_PDSR) Output Data Status */ 01492 #define PIO_PDSR_P19 (0x1u << 19) /* (PIO_PDSR) Output Data Status */ 01493 #define PIO_PDSR_P20 (0x1u << 20) /* (PIO_PDSR) Output Data Status */ 01494 #define PIO_PDSR_P21 (0x1u << 21) /* (PIO_PDSR) Output Data Status */ 01495 #define PIO_PDSR_P22 (0x1u << 22) /* (PIO_PDSR) Output Data Status */ 01496 #define PIO_PDSR_P23 (0x1u << 23) /* (PIO_PDSR) Output Data Status */ 01497 #define PIO_PDSR_P24 (0x1u << 24) /* (PIO_PDSR) Output Data Status */ 01498 #define PIO_PDSR_P25 (0x1u << 25) /* (PIO_PDSR) Output Data Status */ 01499 #define PIO_PDSR_P26 (0x1u << 26) /* (PIO_PDSR) Output Data Status */ 01500 #define PIO_PDSR_P27 (0x1u << 27) /* (PIO_PDSR) Output Data Status */ 01501 #define PIO_PDSR_P28 (0x1u << 28) /* (PIO_PDSR) Output Data Status */ 01502 #define PIO_PDSR_P29 (0x1u << 29) /* (PIO_PDSR) Output Data Status */ 01503 #define PIO_PDSR_P30 (0x1u << 30) /* (PIO_PDSR) Output Data Status */ 01504 #define PIO_PDSR_P31 (0x1u << 31) /* (PIO_PDSR) Output Data Status */ 01505 /* -------- PIO_IER : (PIO Offset: 0x0040) Interrupt Enable Register -------- */ 01506 #define PIO_IER_P0 (0x1u << 0) /* (PIO_IER) Input Change Interrupt Enable */ 01507 #define PIO_IER_P1 (0x1u << 1) /* (PIO_IER) Input Change Interrupt Enable */ 01508 #define PIO_IER_P2 (0x1u << 2) /* (PIO_IER) Input Change Interrupt Enable */ 01509 #define PIO_IER_P3 (0x1u << 3) /* (PIO_IER) Input Change Interrupt Enable */ 01510 #define PIO_IER_P4 (0x1u << 4) /* (PIO_IER) Input Change Interrupt Enable */ 01511 #define PIO_IER_P5 (0x1u << 5) /* (PIO_IER) Input Change Interrupt Enable */ 01512 #define PIO_IER_P6 (0x1u << 6) /* (PIO_IER) Input Change Interrupt Enable */ 01513 #define PIO_IER_P7 (0x1u << 7) /* (PIO_IER) Input Change Interrupt Enable */ 01514 #define PIO_IER_P8 (0x1u << 8) /* (PIO_IER) Input Change Interrupt Enable */ 01515 #define PIO_IER_P9 (0x1u << 9) /* (PIO_IER) Input Change Interrupt Enable */ 01516 #define PIO_IER_P10 (0x1u << 10) /* (PIO_IER) Input Change Interrupt Enable */ 01517 #define PIO_IER_P11 (0x1u << 11) /* (PIO_IER) Input Change Interrupt Enable */ 01518 #define PIO_IER_P12 (0x1u << 12) /* (PIO_IER) Input Change Interrupt Enable */ 01519 #define PIO_IER_P13 (0x1u << 13) /* (PIO_IER) Input Change Interrupt Enable */ 01520 #define PIO_IER_P14 (0x1u << 14) /* (PIO_IER) Input Change Interrupt Enable */ 01521 #define PIO_IER_P15 (0x1u << 15) /* (PIO_IER) Input Change Interrupt Enable */ 01522 #define PIO_IER_P16 (0x1u << 16) /* (PIO_IER) Input Change Interrupt Enable */ 01523 #define PIO_IER_P17 (0x1u << 17) /* (PIO_IER) Input Change Interrupt Enable */ 01524 #define PIO_IER_P18 (0x1u << 18) /* (PIO_IER) Input Change Interrupt Enable */ 01525 #define PIO_IER_P19 (0x1u << 19) /* (PIO_IER) Input Change Interrupt Enable */ 01526 #define PIO_IER_P20 (0x1u << 20) /* (PIO_IER) Input Change Interrupt Enable */ 01527 #define PIO_IER_P21 (0x1u << 21) /* (PIO_IER) Input Change Interrupt Enable */ 01528 #define PIO_IER_P22 (0x1u << 22) /* (PIO_IER) Input Change Interrupt Enable */ 01529 #define PIO_IER_P23 (0x1u << 23) /* (PIO_IER) Input Change Interrupt Enable */ 01530 #define PIO_IER_P24 (0x1u << 24) /* (PIO_IER) Input Change Interrupt Enable */ 01531 #define PIO_IER_P25 (0x1u << 25) /* (PIO_IER) Input Change Interrupt Enable */ 01532 #define PIO_IER_P26 (0x1u << 26) /* (PIO_IER) Input Change Interrupt Enable */ 01533 #define PIO_IER_P27 (0x1u << 27) /* (PIO_IER) Input Change Interrupt Enable */ 01534 #define PIO_IER_P28 (0x1u << 28) /* (PIO_IER) Input Change Interrupt Enable */ 01535 #define PIO_IER_P29 (0x1u << 29) /* (PIO_IER) Input Change Interrupt Enable */ 01536 #define PIO_IER_P30 (0x1u << 30) /* (PIO_IER) Input Change Interrupt Enable */ 01537 #define PIO_IER_P31 (0x1u << 31) /* (PIO_IER) Input Change Interrupt Enable */ 01538 /* -------- PIO_IDR : (PIO Offset: 0x0044) Interrupt Disable Register -------- */ 01539 #define PIO_IDR_P0 (0x1u << 0) /* (PIO_IDR) Input Change Interrupt Disable */ 01540 #define PIO_IDR_P1 (0x1u << 1) /* (PIO_IDR) Input Change Interrupt Disable */ 01541 #define PIO_IDR_P2 (0x1u << 2) /* (PIO_IDR) Input Change Interrupt Disable */ 01542 #define PIO_IDR_P3 (0x1u << 3) /* (PIO_IDR) Input Change Interrupt Disable */ 01543 #define PIO_IDR_P4 (0x1u << 4) /* (PIO_IDR) Input Change Interrupt Disable */ 01544 #define PIO_IDR_P5 (0x1u << 5) /* (PIO_IDR) Input Change Interrupt Disable */ 01545 #define PIO_IDR_P6 (0x1u << 6) /* (PIO_IDR) Input Change Interrupt Disable */ 01546 #define PIO_IDR_P7 (0x1u << 7) /* (PIO_IDR) Input Change Interrupt Disable */ 01547 #define PIO_IDR_P8 (0x1u << 8) /* (PIO_IDR) Input Change Interrupt Disable */ 01548 #define PIO_IDR_P9 (0x1u << 9) /* (PIO_IDR) Input Change Interrupt Disable */ 01549 #define PIO_IDR_P10 (0x1u << 10) /* (PIO_IDR) Input Change Interrupt Disable */ 01550 #define PIO_IDR_P11 (0x1u << 11) /* (PIO_IDR) Input Change Interrupt Disable */ 01551 #define PIO_IDR_P12 (0x1u << 12) /* (PIO_IDR) Input Change Interrupt Disable */ 01552 #define PIO_IDR_P13 (0x1u << 13) /* (PIO_IDR) Input Change Interrupt Disable */ 01553 #define PIO_IDR_P14 (0x1u << 14) /* (PIO_IDR) Input Change Interrupt Disable */ 01554 #define PIO_IDR_P15 (0x1u << 15) /* (PIO_IDR) Input Change Interrupt Disable */ 01555 #define PIO_IDR_P16 (0x1u << 16) /* (PIO_IDR) Input Change Interrupt Disable */ 01556 #define PIO_IDR_P17 (0x1u << 17) /* (PIO_IDR) Input Change Interrupt Disable */ 01557 #define PIO_IDR_P18 (0x1u << 18) /* (PIO_IDR) Input Change Interrupt Disable */ 01558 #define PIO_IDR_P19 (0x1u << 19) /* (PIO_IDR) Input Change Interrupt Disable */ 01559 #define PIO_IDR_P20 (0x1u << 20) /* (PIO_IDR) Input Change Interrupt Disable */ 01560 #define PIO_IDR_P21 (0x1u << 21) /* (PIO_IDR) Input Change Interrupt Disable */ 01561 #define PIO_IDR_P22 (0x1u << 22) /* (PIO_IDR) Input Change Interrupt Disable */ 01562 #define PIO_IDR_P23 (0x1u << 23) /* (PIO_IDR) Input Change Interrupt Disable */ 01563 #define PIO_IDR_P24 (0x1u << 24) /* (PIO_IDR) Input Change Interrupt Disable */ 01564 #define PIO_IDR_P25 (0x1u << 25) /* (PIO_IDR) Input Change Interrupt Disable */ 01565 #define PIO_IDR_P26 (0x1u << 26) /* (PIO_IDR) Input Change Interrupt Disable */ 01566 #define PIO_IDR_P27 (0x1u << 27) /* (PIO_IDR) Input Change Interrupt Disable */ 01567 #define PIO_IDR_P28 (0x1u << 28) /* (PIO_IDR) Input Change Interrupt Disable */ 01568 #define PIO_IDR_P29 (0x1u << 29) /* (PIO_IDR) Input Change Interrupt Disable */ 01569 #define PIO_IDR_P30 (0x1u << 30) /* (PIO_IDR) Input Change Interrupt Disable */ 01570 #define PIO_IDR_P31 (0x1u << 31) /* (PIO_IDR) Input Change Interrupt Disable */ 01571 /* -------- PIO_IMR : (PIO Offset: 0x0048) Interrupt Mask Register -------- */ 01572 #define PIO_IMR_P0 (0x1u << 0) /* (PIO_IMR) Input Change Interrupt Mask */ 01573 #define PIO_IMR_P1 (0x1u << 1) /* (PIO_IMR) Input Change Interrupt Mask */ 01574 #define PIO_IMR_P2 (0x1u << 2) /* (PIO_IMR) Input Change Interrupt Mask */ 01575 #define PIO_IMR_P3 (0x1u << 3) /* (PIO_IMR) Input Change Interrupt Mask */ 01576 #define PIO_IMR_P4 (0x1u << 4) /* (PIO_IMR) Input Change Interrupt Mask */ 01577 #define PIO_IMR_P5 (0x1u << 5) /* (PIO_IMR) Input Change Interrupt Mask */ 01578 #define PIO_IMR_P6 (0x1u << 6) /* (PIO_IMR) Input Change Interrupt Mask */ 01579 #define PIO_IMR_P7 (0x1u << 7) /* (PIO_IMR) Input Change Interrupt Mask */ 01580 #define PIO_IMR_P8 (0x1u << 8) /* (PIO_IMR) Input Change Interrupt Mask */ 01581 #define PIO_IMR_P9 (0x1u << 9) /* (PIO_IMR) Input Change Interrupt Mask */ 01582 #define PIO_IMR_P10 (0x1u << 10) /* (PIO_IMR) Input Change Interrupt Mask */ 01583 #define PIO_IMR_P11 (0x1u << 11) /* (PIO_IMR) Input Change Interrupt Mask */ 01584 #define PIO_IMR_P12 (0x1u << 12) /* (PIO_IMR) Input Change Interrupt Mask */ 01585 #define PIO_IMR_P13 (0x1u << 13) /* (PIO_IMR) Input Change Interrupt Mask */ 01586 #define PIO_IMR_P14 (0x1u << 14) /* (PIO_IMR) Input Change Interrupt Mask */ 01587 #define PIO_IMR_P15 (0x1u << 15) /* (PIO_IMR) Input Change Interrupt Mask */ 01588 #define PIO_IMR_P16 (0x1u << 16) /* (PIO_IMR) Input Change Interrupt Mask */ 01589 #define PIO_IMR_P17 (0x1u << 17) /* (PIO_IMR) Input Change Interrupt Mask */ 01590 #define PIO_IMR_P18 (0x1u << 18) /* (PIO_IMR) Input Change Interrupt Mask */ 01591 #define PIO_IMR_P19 (0x1u << 19) /* (PIO_IMR) Input Change Interrupt Mask */ 01592 #define PIO_IMR_P20 (0x1u << 20) /* (PIO_IMR) Input Change Interrupt Mask */ 01593 #define PIO_IMR_P21 (0x1u << 21) /* (PIO_IMR) Input Change Interrupt Mask */ 01594 #define PIO_IMR_P22 (0x1u << 22) /* (PIO_IMR) Input Change Interrupt Mask */ 01595 #define PIO_IMR_P23 (0x1u << 23) /* (PIO_IMR) Input Change Interrupt Mask */ 01596 #define PIO_IMR_P24 (0x1u << 24) /* (PIO_IMR) Input Change Interrupt Mask */ 01597 #define PIO_IMR_P25 (0x1u << 25) /* (PIO_IMR) Input Change Interrupt Mask */ 01598 #define PIO_IMR_P26 (0x1u << 26) /* (PIO_IMR) Input Change Interrupt Mask */ 01599 #define PIO_IMR_P27 (0x1u << 27) /* (PIO_IMR) Input Change Interrupt Mask */ 01600 #define PIO_IMR_P28 (0x1u << 28) /* (PIO_IMR) Input Change Interrupt Mask */ 01601 #define PIO_IMR_P29 (0x1u << 29) /* (PIO_IMR) Input Change Interrupt Mask */ 01602 #define PIO_IMR_P30 (0x1u << 30) /* (PIO_IMR) Input Change Interrupt Mask */ 01603 #define PIO_IMR_P31 (0x1u << 31) /* (PIO_IMR) Input Change Interrupt Mask */ 01604 /* -------- PIO_ISR : (PIO Offset: 0x004C) Interrupt Status Register -------- */ 01605 #define PIO_ISR_P0 (0x1u << 0) /* (PIO_ISR) Input Change Interrupt Status */ 01606 #define PIO_ISR_P1 (0x1u << 1) /* (PIO_ISR) Input Change Interrupt Status */ 01607 #define PIO_ISR_P2 (0x1u << 2) /* (PIO_ISR) Input Change Interrupt Status */ 01608 #define PIO_ISR_P3 (0x1u << 3) /* (PIO_ISR) Input Change Interrupt Status */ 01609 #define PIO_ISR_P4 (0x1u << 4) /* (PIO_ISR) Input Change Interrupt Status */ 01610 #define PIO_ISR_P5 (0x1u << 5) /* (PIO_ISR) Input Change Interrupt Status */ 01611 #define PIO_ISR_P6 (0x1u << 6) /* (PIO_ISR) Input Change Interrupt Status */ 01612 #define PIO_ISR_P7 (0x1u << 7) /* (PIO_ISR) Input Change Interrupt Status */ 01613 #define PIO_ISR_P8 (0x1u << 8) /* (PIO_ISR) Input Change Interrupt Status */ 01614 #define PIO_ISR_P9 (0x1u << 9) /* (PIO_ISR) Input Change Interrupt Status */ 01615 #define PIO_ISR_P10 (0x1u << 10) /* (PIO_ISR) Input Change Interrupt Status */ 01616 #define PIO_ISR_P11 (0x1u << 11) /* (PIO_ISR) Input Change Interrupt Status */ 01617 #define PIO_ISR_P12 (0x1u << 12) /* (PIO_ISR) Input Change Interrupt Status */ 01618 #define PIO_ISR_P13 (0x1u << 13) /* (PIO_ISR) Input Change Interrupt Status */ 01619 #define PIO_ISR_P14 (0x1u << 14) /* (PIO_ISR) Input Change Interrupt Status */ 01620 #define PIO_ISR_P15 (0x1u << 15) /* (PIO_ISR) Input Change Interrupt Status */ 01621 #define PIO_ISR_P16 (0x1u << 16) /* (PIO_ISR) Input Change Interrupt Status */ 01622 #define PIO_ISR_P17 (0x1u << 17) /* (PIO_ISR) Input Change Interrupt Status */ 01623 #define PIO_ISR_P18 (0x1u << 18) /* (PIO_ISR) Input Change Interrupt Status */ 01624 #define PIO_ISR_P19 (0x1u << 19) /* (PIO_ISR) Input Change Interrupt Status */ 01625 #define PIO_ISR_P20 (0x1u << 20) /* (PIO_ISR) Input Change Interrupt Status */ 01626 #define PIO_ISR_P21 (0x1u << 21) /* (PIO_ISR) Input Change Interrupt Status */ 01627 #define PIO_ISR_P22 (0x1u << 22) /* (PIO_ISR) Input Change Interrupt Status */ 01628 #define PIO_ISR_P23 (0x1u << 23) /* (PIO_ISR) Input Change Interrupt Status */ 01629 #define PIO_ISR_P24 (0x1u << 24) /* (PIO_ISR) Input Change Interrupt Status */ 01630 #define PIO_ISR_P25 (0x1u << 25) /* (PIO_ISR) Input Change Interrupt Status */ 01631 #define PIO_ISR_P26 (0x1u << 26) /* (PIO_ISR) Input Change Interrupt Status */ 01632 #define PIO_ISR_P27 (0x1u << 27) /* (PIO_ISR) Input Change Interrupt Status */ 01633 #define PIO_ISR_P28 (0x1u << 28) /* (PIO_ISR) Input Change Interrupt Status */ 01634 #define PIO_ISR_P29 (0x1u << 29) /* (PIO_ISR) Input Change Interrupt Status */ 01635 #define PIO_ISR_P30 (0x1u << 30) /* (PIO_ISR) Input Change Interrupt Status */ 01636 #define PIO_ISR_P31 (0x1u << 31) /* (PIO_ISR) Input Change Interrupt Status */ 01637 /* -------- PIO_MDER : (PIO Offset: 0x0050) Multi-driver Enable Register -------- */ 01638 #define PIO_MDER_P0 (0x1u << 0) /* (PIO_MDER) Multi Drive Enable. */ 01639 #define PIO_MDER_P1 (0x1u << 1) /* (PIO_MDER) Multi Drive Enable. */ 01640 #define PIO_MDER_P2 (0x1u << 2) /* (PIO_MDER) Multi Drive Enable. */ 01641 #define PIO_MDER_P3 (0x1u << 3) /* (PIO_MDER) Multi Drive Enable. */ 01642 #define PIO_MDER_P4 (0x1u << 4) /* (PIO_MDER) Multi Drive Enable. */ 01643 #define PIO_MDER_P5 (0x1u << 5) /* (PIO_MDER) Multi Drive Enable. */ 01644 #define PIO_MDER_P6 (0x1u << 6) /* (PIO_MDER) Multi Drive Enable. */ 01645 #define PIO_MDER_P7 (0x1u << 7) /* (PIO_MDER) Multi Drive Enable. */ 01646 #define PIO_MDER_P8 (0x1u << 8) /* (PIO_MDER) Multi Drive Enable. */ 01647 #define PIO_MDER_P9 (0x1u << 9) /* (PIO_MDER) Multi Drive Enable. */ 01648 #define PIO_MDER_P10 (0x1u << 10) /* (PIO_MDER) Multi Drive Enable. */ 01649 #define PIO_MDER_P11 (0x1u << 11) /* (PIO_MDER) Multi Drive Enable. */ 01650 #define PIO_MDER_P12 (0x1u << 12) /* (PIO_MDER) Multi Drive Enable. */ 01651 #define PIO_MDER_P13 (0x1u << 13) /* (PIO_MDER) Multi Drive Enable. */ 01652 #define PIO_MDER_P14 (0x1u << 14) /* (PIO_MDER) Multi Drive Enable. */ 01653 #define PIO_MDER_P15 (0x1u << 15) /* (PIO_MDER) Multi Drive Enable. */ 01654 #define PIO_MDER_P16 (0x1u << 16) /* (PIO_MDER) Multi Drive Enable. */ 01655 #define PIO_MDER_P17 (0x1u << 17) /* (PIO_MDER) Multi Drive Enable. */ 01656 #define PIO_MDER_P18 (0x1u << 18) /* (PIO_MDER) Multi Drive Enable. */ 01657 #define PIO_MDER_P19 (0x1u << 19) /* (PIO_MDER) Multi Drive Enable. */ 01658 #define PIO_MDER_P20 (0x1u << 20) /* (PIO_MDER) Multi Drive Enable. */ 01659 #define PIO_MDER_P21 (0x1u << 21) /* (PIO_MDER) Multi Drive Enable. */ 01660 #define PIO_MDER_P22 (0x1u << 22) /* (PIO_MDER) Multi Drive Enable. */ 01661 #define PIO_MDER_P23 (0x1u << 23) /* (PIO_MDER) Multi Drive Enable. */ 01662 #define PIO_MDER_P24 (0x1u << 24) /* (PIO_MDER) Multi Drive Enable. */ 01663 #define PIO_MDER_P25 (0x1u << 25) /* (PIO_MDER) Multi Drive Enable. */ 01664 #define PIO_MDER_P26 (0x1u << 26) /* (PIO_MDER) Multi Drive Enable. */ 01665 #define PIO_MDER_P27 (0x1u << 27) /* (PIO_MDER) Multi Drive Enable. */ 01666 #define PIO_MDER_P28 (0x1u << 28) /* (PIO_MDER) Multi Drive Enable. */ 01667 #define PIO_MDER_P29 (0x1u << 29) /* (PIO_MDER) Multi Drive Enable. */ 01668 #define PIO_MDER_P30 (0x1u << 30) /* (PIO_MDER) Multi Drive Enable. */ 01669 #define PIO_MDER_P31 (0x1u << 31) /* (PIO_MDER) Multi Drive Enable. */ 01670 /* -------- PIO_MDDR : (PIO Offset: 0x0054) Multi-driver Disable Register -------- */ 01671 #define PIO_MDDR_P0 (0x1u << 0) /* (PIO_MDDR) Multi Drive Disable. */ 01672 #define PIO_MDDR_P1 (0x1u << 1) /* (PIO_MDDR) Multi Drive Disable. */ 01673 #define PIO_MDDR_P2 (0x1u << 2) /* (PIO_MDDR) Multi Drive Disable. */ 01674 #define PIO_MDDR_P3 (0x1u << 3) /* (PIO_MDDR) Multi Drive Disable. */ 01675 #define PIO_MDDR_P4 (0x1u << 4) /* (PIO_MDDR) Multi Drive Disable. */ 01676 #define PIO_MDDR_P5 (0x1u << 5) /* (PIO_MDDR) Multi Drive Disable. */ 01677 #define PIO_MDDR_P6 (0x1u << 6) /* (PIO_MDDR) Multi Drive Disable. */ 01678 #define PIO_MDDR_P7 (0x1u << 7) /* (PIO_MDDR) Multi Drive Disable. */ 01679 #define PIO_MDDR_P8 (0x1u << 8) /* (PIO_MDDR) Multi Drive Disable. */ 01680 #define PIO_MDDR_P9 (0x1u << 9) /* (PIO_MDDR) Multi Drive Disable. */ 01681 #define PIO_MDDR_P10 (0x1u << 10) /* (PIO_MDDR) Multi Drive Disable. */ 01682 #define PIO_MDDR_P11 (0x1u << 11) /* (PIO_MDDR) Multi Drive Disable. */ 01683 #define PIO_MDDR_P12 (0x1u << 12) /* (PIO_MDDR) Multi Drive Disable. */ 01684 #define PIO_MDDR_P13 (0x1u << 13) /* (PIO_MDDR) Multi Drive Disable. */ 01685 #define PIO_MDDR_P14 (0x1u << 14) /* (PIO_MDDR) Multi Drive Disable. */ 01686 #define PIO_MDDR_P15 (0x1u << 15) /* (PIO_MDDR) Multi Drive Disable. */ 01687 #define PIO_MDDR_P16 (0x1u << 16) /* (PIO_MDDR) Multi Drive Disable. */ 01688 #define PIO_MDDR_P17 (0x1u << 17) /* (PIO_MDDR) Multi Drive Disable. */ 01689 #define PIO_MDDR_P18 (0x1u << 18) /* (PIO_MDDR) Multi Drive Disable. */ 01690 #define PIO_MDDR_P19 (0x1u << 19) /* (PIO_MDDR) Multi Drive Disable. */ 01691 #define PIO_MDDR_P20 (0x1u << 20) /* (PIO_MDDR) Multi Drive Disable. */ 01692 #define PIO_MDDR_P21 (0x1u << 21) /* (PIO_MDDR) Multi Drive Disable. */ 01693 #define PIO_MDDR_P22 (0x1u << 22) /* (PIO_MDDR) Multi Drive Disable. */ 01694 #define PIO_MDDR_P23 (0x1u << 23) /* (PIO_MDDR) Multi Drive Disable. */ 01695 #define PIO_MDDR_P24 (0x1u << 24) /* (PIO_MDDR) Multi Drive Disable. */ 01696 #define PIO_MDDR_P25 (0x1u << 25) /* (PIO_MDDR) Multi Drive Disable. */ 01697 #define PIO_MDDR_P26 (0x1u << 26) /* (PIO_MDDR) Multi Drive Disable. */ 01698 #define PIO_MDDR_P27 (0x1u << 27) /* (PIO_MDDR) Multi Drive Disable. */ 01699 #define PIO_MDDR_P28 (0x1u << 28) /* (PIO_MDDR) Multi Drive Disable. */ 01700 #define PIO_MDDR_P29 (0x1u << 29) /* (PIO_MDDR) Multi Drive Disable. */ 01701 #define PIO_MDDR_P30 (0x1u << 30) /* (PIO_MDDR) Multi Drive Disable. */ 01702 #define PIO_MDDR_P31 (0x1u << 31) /* (PIO_MDDR) Multi Drive Disable. */ 01703 /* -------- PIO_MDSR : (PIO Offset: 0x0058) Multi-driver Status Register -------- */ 01704 #define PIO_MDSR_P0 (0x1u << 0) /* (PIO_MDSR) Multi Drive Status. */ 01705 #define PIO_MDSR_P1 (0x1u << 1) /* (PIO_MDSR) Multi Drive Status. */ 01706 #define PIO_MDSR_P2 (0x1u << 2) /* (PIO_MDSR) Multi Drive Status. */ 01707 #define PIO_MDSR_P3 (0x1u << 3) /* (PIO_MDSR) Multi Drive Status. */ 01708 #define PIO_MDSR_P4 (0x1u << 4) /* (PIO_MDSR) Multi Drive Status. */ 01709 #define PIO_MDSR_P5 (0x1u << 5) /* (PIO_MDSR) Multi Drive Status. */ 01710 #define PIO_MDSR_P6 (0x1u << 6) /* (PIO_MDSR) Multi Drive Status. */ 01711 #define PIO_MDSR_P7 (0x1u << 7) /* (PIO_MDSR) Multi Drive Status. */ 01712 #define PIO_MDSR_P8 (0x1u << 8) /* (PIO_MDSR) Multi Drive Status. */ 01713 #define PIO_MDSR_P9 (0x1u << 9) /* (PIO_MDSR) Multi Drive Status. */ 01714 #define PIO_MDSR_P10 (0x1u << 10) /* (PIO_MDSR) Multi Drive Status. */ 01715 #define PIO_MDSR_P11 (0x1u << 11) /* (PIO_MDSR) Multi Drive Status. */ 01716 #define PIO_MDSR_P12 (0x1u << 12) /* (PIO_MDSR) Multi Drive Status. */ 01717 #define PIO_MDSR_P13 (0x1u << 13) /* (PIO_MDSR) Multi Drive Status. */ 01718 #define PIO_MDSR_P14 (0x1u << 14) /* (PIO_MDSR) Multi Drive Status. */ 01719 #define PIO_MDSR_P15 (0x1u << 15) /* (PIO_MDSR) Multi Drive Status. */ 01720 #define PIO_MDSR_P16 (0x1u << 16) /* (PIO_MDSR) Multi Drive Status. */ 01721 #define PIO_MDSR_P17 (0x1u << 17) /* (PIO_MDSR) Multi Drive Status. */ 01722 #define PIO_MDSR_P18 (0x1u << 18) /* (PIO_MDSR) Multi Drive Status. */ 01723 #define PIO_MDSR_P19 (0x1u << 19) /* (PIO_MDSR) Multi Drive Status. */ 01724 #define PIO_MDSR_P20 (0x1u << 20) /* (PIO_MDSR) Multi Drive Status. */ 01725 #define PIO_MDSR_P21 (0x1u << 21) /* (PIO_MDSR) Multi Drive Status. */ 01726 #define PIO_MDSR_P22 (0x1u << 22) /* (PIO_MDSR) Multi Drive Status. */ 01727 #define PIO_MDSR_P23 (0x1u << 23) /* (PIO_MDSR) Multi Drive Status. */ 01728 #define PIO_MDSR_P24 (0x1u << 24) /* (PIO_MDSR) Multi Drive Status. */ 01729 #define PIO_MDSR_P25 (0x1u << 25) /* (PIO_MDSR) Multi Drive Status. */ 01730 #define PIO_MDSR_P26 (0x1u << 26) /* (PIO_MDSR) Multi Drive Status. */ 01731 #define PIO_MDSR_P27 (0x1u << 27) /* (PIO_MDSR) Multi Drive Status. */ 01732 #define PIO_MDSR_P28 (0x1u << 28) /* (PIO_MDSR) Multi Drive Status. */ 01733 #define PIO_MDSR_P29 (0x1u << 29) /* (PIO_MDSR) Multi Drive Status. */ 01734 #define PIO_MDSR_P30 (0x1u << 30) /* (PIO_MDSR) Multi Drive Status. */ 01735 #define PIO_MDSR_P31 (0x1u << 31) /* (PIO_MDSR) Multi Drive Status. */ 01736 /* -------- PIO_PUDR : (PIO Offset: 0x0060) Pull-up Disable Register -------- */ 01737 #define PIO_PUDR_P0 (0x1u << 0) /* (PIO_PUDR) Pull Up Disable. */ 01738 #define PIO_PUDR_P1 (0x1u << 1) /* (PIO_PUDR) Pull Up Disable. */ 01739 #define PIO_PUDR_P2 (0x1u << 2) /* (PIO_PUDR) Pull Up Disable. */ 01740 #define PIO_PUDR_P3 (0x1u << 3) /* (PIO_PUDR) Pull Up Disable. */ 01741 #define PIO_PUDR_P4 (0x1u << 4) /* (PIO_PUDR) Pull Up Disable. */ 01742 #define PIO_PUDR_P5 (0x1u << 5) /* (PIO_PUDR) Pull Up Disable. */ 01743 #define PIO_PUDR_P6 (0x1u << 6) /* (PIO_PUDR) Pull Up Disable. */ 01744 #define PIO_PUDR_P7 (0x1u << 7) /* (PIO_PUDR) Pull Up Disable. */ 01745 #define PIO_PUDR_P8 (0x1u << 8) /* (PIO_PUDR) Pull Up Disable. */ 01746 #define PIO_PUDR_P9 (0x1u << 9) /* (PIO_PUDR) Pull Up Disable. */ 01747 #define PIO_PUDR_P10 (0x1u << 10) /* (PIO_PUDR) Pull Up Disable. */ 01748 #define PIO_PUDR_P11 (0x1u << 11) /* (PIO_PUDR) Pull Up Disable. */ 01749 #define PIO_PUDR_P12 (0x1u << 12) /* (PIO_PUDR) Pull Up Disable. */ 01750 #define PIO_PUDR_P13 (0x1u << 13) /* (PIO_PUDR) Pull Up Disable. */ 01751 #define PIO_PUDR_P14 (0x1u << 14) /* (PIO_PUDR) Pull Up Disable. */ 01752 #define PIO_PUDR_P15 (0x1u << 15) /* (PIO_PUDR) Pull Up Disable. */ 01753 #define PIO_PUDR_P16 (0x1u << 16) /* (PIO_PUDR) Pull Up Disable. */ 01754 #define PIO_PUDR_P17 (0x1u << 17) /* (PIO_PUDR) Pull Up Disable. */ 01755 #define PIO_PUDR_P18 (0x1u << 18) /* (PIO_PUDR) Pull Up Disable. */ 01756 #define PIO_PUDR_P19 (0x1u << 19) /* (PIO_PUDR) Pull Up Disable. */ 01757 #define PIO_PUDR_P20 (0x1u << 20) /* (PIO_PUDR) Pull Up Disable. */ 01758 #define PIO_PUDR_P21 (0x1u << 21) /* (PIO_PUDR) Pull Up Disable. */ 01759 #define PIO_PUDR_P22 (0x1u << 22) /* (PIO_PUDR) Pull Up Disable. */ 01760 #define PIO_PUDR_P23 (0x1u << 23) /* (PIO_PUDR) Pull Up Disable. */ 01761 #define PIO_PUDR_P24 (0x1u << 24) /* (PIO_PUDR) Pull Up Disable. */ 01762 #define PIO_PUDR_P25 (0x1u << 25) /* (PIO_PUDR) Pull Up Disable. */ 01763 #define PIO_PUDR_P26 (0x1u << 26) /* (PIO_PUDR) Pull Up Disable. */ 01764 #define PIO_PUDR_P27 (0x1u << 27) /* (PIO_PUDR) Pull Up Disable. */ 01765 #define PIO_PUDR_P28 (0x1u << 28) /* (PIO_PUDR) Pull Up Disable. */ 01766 #define PIO_PUDR_P29 (0x1u << 29) /* (PIO_PUDR) Pull Up Disable. */ 01767 #define PIO_PUDR_P30 (0x1u << 30) /* (PIO_PUDR) Pull Up Disable. */ 01768 #define PIO_PUDR_P31 (0x1u << 31) /* (PIO_PUDR) Pull Up Disable. */ 01769 /* -------- PIO_PUER : (PIO Offset: 0x0064) Pull-up Enable Register -------- */ 01770 #define PIO_PUER_P0 (0x1u << 0) /* (PIO_PUER) Pull Up Enable. */ 01771 #define PIO_PUER_P1 (0x1u << 1) /* (PIO_PUER) Pull Up Enable. */ 01772 #define PIO_PUER_P2 (0x1u << 2) /* (PIO_PUER) Pull Up Enable. */ 01773 #define PIO_PUER_P3 (0x1u << 3) /* (PIO_PUER) Pull Up Enable. */ 01774 #define PIO_PUER_P4 (0x1u << 4) /* (PIO_PUER) Pull Up Enable. */ 01775 #define PIO_PUER_P5 (0x1u << 5) /* (PIO_PUER) Pull Up Enable. */ 01776 #define PIO_PUER_P6 (0x1u << 6) /* (PIO_PUER) Pull Up Enable. */ 01777 #define PIO_PUER_P7 (0x1u << 7) /* (PIO_PUER) Pull Up Enable. */ 01778 #define PIO_PUER_P8 (0x1u << 8) /* (PIO_PUER) Pull Up Enable. */ 01779 #define PIO_PUER_P9 (0x1u << 9) /* (PIO_PUER) Pull Up Enable. */ 01780 #define PIO_PUER_P10 (0x1u << 10) /* (PIO_PUER) Pull Up Enable. */ 01781 #define PIO_PUER_P11 (0x1u << 11) /* (PIO_PUER) Pull Up Enable. */ 01782 #define PIO_PUER_P12 (0x1u << 12) /* (PIO_PUER) Pull Up Enable. */ 01783 #define PIO_PUER_P13 (0x1u << 13) /* (PIO_PUER) Pull Up Enable. */ 01784 #define PIO_PUER_P14 (0x1u << 14) /* (PIO_PUER) Pull Up Enable. */ 01785 #define PIO_PUER_P15 (0x1u << 15) /* (PIO_PUER) Pull Up Enable. */ 01786 #define PIO_PUER_P16 (0x1u << 16) /* (PIO_PUER) Pull Up Enable. */ 01787 #define PIO_PUER_P17 (0x1u << 17) /* (PIO_PUER) Pull Up Enable. */ 01788 #define PIO_PUER_P18 (0x1u << 18) /* (PIO_PUER) Pull Up Enable. */ 01789 #define PIO_PUER_P19 (0x1u << 19) /* (PIO_PUER) Pull Up Enable. */ 01790 #define PIO_PUER_P20 (0x1u << 20) /* (PIO_PUER) Pull Up Enable. */ 01791 #define PIO_PUER_P21 (0x1u << 21) /* (PIO_PUER) Pull Up Enable. */ 01792 #define PIO_PUER_P22 (0x1u << 22) /* (PIO_PUER) Pull Up Enable. */ 01793 #define PIO_PUER_P23 (0x1u << 23) /* (PIO_PUER) Pull Up Enable. */ 01794 #define PIO_PUER_P24 (0x1u << 24) /* (PIO_PUER) Pull Up Enable. */ 01795 #define PIO_PUER_P25 (0x1u << 25) /* (PIO_PUER) Pull Up Enable. */ 01796 #define PIO_PUER_P26 (0x1u << 26) /* (PIO_PUER) Pull Up Enable. */ 01797 #define PIO_PUER_P27 (0x1u << 27) /* (PIO_PUER) Pull Up Enable. */ 01798 #define PIO_PUER_P28 (0x1u << 28) /* (PIO_PUER) Pull Up Enable. */ 01799 #define PIO_PUER_P29 (0x1u << 29) /* (PIO_PUER) Pull Up Enable. */ 01800 #define PIO_PUER_P30 (0x1u << 30) /* (PIO_PUER) Pull Up Enable. */ 01801 #define PIO_PUER_P31 (0x1u << 31) /* (PIO_PUER) Pull Up Enable. */ 01802 /* -------- PIO_PUSR : (PIO Offset: 0x0068) Pad Pull-up Status Register -------- */ 01803 #define PIO_PUSR_P0 (0x1u << 0) /* (PIO_PUSR) Pull Up Status. */ 01804 #define PIO_PUSR_P1 (0x1u << 1) /* (PIO_PUSR) Pull Up Status. */ 01805 #define PIO_PUSR_P2 (0x1u << 2) /* (PIO_PUSR) Pull Up Status. */ 01806 #define PIO_PUSR_P3 (0x1u << 3) /* (PIO_PUSR) Pull Up Status. */ 01807 #define PIO_PUSR_P4 (0x1u << 4) /* (PIO_PUSR) Pull Up Status. */ 01808 #define PIO_PUSR_P5 (0x1u << 5) /* (PIO_PUSR) Pull Up Status. */ 01809 #define PIO_PUSR_P6 (0x1u << 6) /* (PIO_PUSR) Pull Up Status. */ 01810 #define PIO_PUSR_P7 (0x1u << 7) /* (PIO_PUSR) Pull Up Status. */ 01811 #define PIO_PUSR_P8 (0x1u << 8) /* (PIO_PUSR) Pull Up Status. */ 01812 #define PIO_PUSR_P9 (0x1u << 9) /* (PIO_PUSR) Pull Up Status. */ 01813 #define PIO_PUSR_P10 (0x1u << 10) /* (PIO_PUSR) Pull Up Status. */ 01814 #define PIO_PUSR_P11 (0x1u << 11) /* (PIO_PUSR) Pull Up Status. */ 01815 #define PIO_PUSR_P12 (0x1u << 12) /* (PIO_PUSR) Pull Up Status. */ 01816 #define PIO_PUSR_P13 (0x1u << 13) /* (PIO_PUSR) Pull Up Status. */ 01817 #define PIO_PUSR_P14 (0x1u << 14) /* (PIO_PUSR) Pull Up Status. */ 01818 #define PIO_PUSR_P15 (0x1u << 15) /* (PIO_PUSR) Pull Up Status. */ 01819 #define PIO_PUSR_P16 (0x1u << 16) /* (PIO_PUSR) Pull Up Status. */ 01820 #define PIO_PUSR_P17 (0x1u << 17) /* (PIO_PUSR) Pull Up Status. */ 01821 #define PIO_PUSR_P18 (0x1u << 18) /* (PIO_PUSR) Pull Up Status. */ 01822 #define PIO_PUSR_P19 (0x1u << 19) /* (PIO_PUSR) Pull Up Status. */ 01823 #define PIO_PUSR_P20 (0x1u << 20) /* (PIO_PUSR) Pull Up Status. */ 01824 #define PIO_PUSR_P21 (0x1u << 21) /* (PIO_PUSR) Pull Up Status. */ 01825 #define PIO_PUSR_P22 (0x1u << 22) /* (PIO_PUSR) Pull Up Status. */ 01826 #define PIO_PUSR_P23 (0x1u << 23) /* (PIO_PUSR) Pull Up Status. */ 01827 #define PIO_PUSR_P24 (0x1u << 24) /* (PIO_PUSR) Pull Up Status. */ 01828 #define PIO_PUSR_P25 (0x1u << 25) /* (PIO_PUSR) Pull Up Status. */ 01829 #define PIO_PUSR_P26 (0x1u << 26) /* (PIO_PUSR) Pull Up Status. */ 01830 #define PIO_PUSR_P27 (0x1u << 27) /* (PIO_PUSR) Pull Up Status. */ 01831 #define PIO_PUSR_P28 (0x1u << 28) /* (PIO_PUSR) Pull Up Status. */ 01832 #define PIO_PUSR_P29 (0x1u << 29) /* (PIO_PUSR) Pull Up Status. */ 01833 #define PIO_PUSR_P30 (0x1u << 30) /* (PIO_PUSR) Pull Up Status. */ 01834 #define PIO_PUSR_P31 (0x1u << 31) /* (PIO_PUSR) Pull Up Status. */ 01835 /* -------- PIO_ABCDSR[2] : (PIO Offset: 0x0070) Peripheral Select Register -------- */ 01836 #define PIO_ABCDSR_P0 (0x1u << 0) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01837 #define PIO_ABCDSR_P1 (0x1u << 1) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01838 #define PIO_ABCDSR_P2 (0x1u << 2) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01839 #define PIO_ABCDSR_P3 (0x1u << 3) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01840 #define PIO_ABCDSR_P4 (0x1u << 4) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01841 #define PIO_ABCDSR_P5 (0x1u << 5) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01842 #define PIO_ABCDSR_P6 (0x1u << 6) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01843 #define PIO_ABCDSR_P7 (0x1u << 7) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01844 #define PIO_ABCDSR_P8 (0x1u << 8) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01845 #define PIO_ABCDSR_P9 (0x1u << 9) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01846 #define PIO_ABCDSR_P10 (0x1u << 10) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01847 #define PIO_ABCDSR_P11 (0x1u << 11) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01848 #define PIO_ABCDSR_P12 (0x1u << 12) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01849 #define PIO_ABCDSR_P13 (0x1u << 13) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01850 #define PIO_ABCDSR_P14 (0x1u << 14) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01851 #define PIO_ABCDSR_P15 (0x1u << 15) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01852 #define PIO_ABCDSR_P16 (0x1u << 16) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01853 #define PIO_ABCDSR_P17 (0x1u << 17) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01854 #define PIO_ABCDSR_P18 (0x1u << 18) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01855 #define PIO_ABCDSR_P19 (0x1u << 19) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01856 #define PIO_ABCDSR_P20 (0x1u << 20) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01857 #define PIO_ABCDSR_P21 (0x1u << 21) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01858 #define PIO_ABCDSR_P22 (0x1u << 22) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01859 #define PIO_ABCDSR_P23 (0x1u << 23) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01860 #define PIO_ABCDSR_P24 (0x1u << 24) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01861 #define PIO_ABCDSR_P25 (0x1u << 25) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01862 #define PIO_ABCDSR_P26 (0x1u << 26) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01863 #define PIO_ABCDSR_P27 (0x1u << 27) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01864 #define PIO_ABCDSR_P28 (0x1u << 28) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01865 #define PIO_ABCDSR_P29 (0x1u << 29) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01866 #define PIO_ABCDSR_P30 (0x1u << 30) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01867 #define PIO_ABCDSR_P31 (0x1u << 31) /* (PIO_ABCDSR[2]) Peripheral Select. */ 01868 /* -------- PIO_IFSCDR : (PIO Offset: 0x0080) Input Filter Slow Clock Disable Register -------- */ 01869 #define PIO_IFSCDR_P0 (0x1u << 0) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01870 #define PIO_IFSCDR_P1 (0x1u << 1) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01871 #define PIO_IFSCDR_P2 (0x1u << 2) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01872 #define PIO_IFSCDR_P3 (0x1u << 3) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01873 #define PIO_IFSCDR_P4 (0x1u << 4) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01874 #define PIO_IFSCDR_P5 (0x1u << 5) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01875 #define PIO_IFSCDR_P6 (0x1u << 6) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01876 #define PIO_IFSCDR_P7 (0x1u << 7) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01877 #define PIO_IFSCDR_P8 (0x1u << 8) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01878 #define PIO_IFSCDR_P9 (0x1u << 9) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01879 #define PIO_IFSCDR_P10 (0x1u << 10) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01880 #define PIO_IFSCDR_P11 (0x1u << 11) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01881 #define PIO_IFSCDR_P12 (0x1u << 12) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01882 #define PIO_IFSCDR_P13 (0x1u << 13) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01883 #define PIO_IFSCDR_P14 (0x1u << 14) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01884 #define PIO_IFSCDR_P15 (0x1u << 15) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01885 #define PIO_IFSCDR_P16 (0x1u << 16) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01886 #define PIO_IFSCDR_P17 (0x1u << 17) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01887 #define PIO_IFSCDR_P18 (0x1u << 18) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01888 #define PIO_IFSCDR_P19 (0x1u << 19) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01889 #define PIO_IFSCDR_P20 (0x1u << 20) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01890 #define PIO_IFSCDR_P21 (0x1u << 21) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01891 #define PIO_IFSCDR_P22 (0x1u << 22) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01892 #define PIO_IFSCDR_P23 (0x1u << 23) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01893 #define PIO_IFSCDR_P24 (0x1u << 24) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01894 #define PIO_IFSCDR_P25 (0x1u << 25) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01895 #define PIO_IFSCDR_P26 (0x1u << 26) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01896 #define PIO_IFSCDR_P27 (0x1u << 27) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01897 #define PIO_IFSCDR_P28 (0x1u << 28) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01898 #define PIO_IFSCDR_P29 (0x1u << 29) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01899 #define PIO_IFSCDR_P30 (0x1u << 30) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01900 #define PIO_IFSCDR_P31 (0x1u << 31) /* (PIO_IFSCDR) PIO Clock Glitch Filtering Select. */ 01901 /* -------- PIO_IFSCER : (PIO Offset: 0x0084) Input Filter Slow Clock Enable Register -------- */ 01902 #define PIO_IFSCER_P0 (0x1u << 0) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01903 #define PIO_IFSCER_P1 (0x1u << 1) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01904 #define PIO_IFSCER_P2 (0x1u << 2) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01905 #define PIO_IFSCER_P3 (0x1u << 3) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01906 #define PIO_IFSCER_P4 (0x1u << 4) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01907 #define PIO_IFSCER_P5 (0x1u << 5) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01908 #define PIO_IFSCER_P6 (0x1u << 6) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01909 #define PIO_IFSCER_P7 (0x1u << 7) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01910 #define PIO_IFSCER_P8 (0x1u << 8) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01911 #define PIO_IFSCER_P9 (0x1u << 9) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01912 #define PIO_IFSCER_P10 (0x1u << 10) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01913 #define PIO_IFSCER_P11 (0x1u << 11) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01914 #define PIO_IFSCER_P12 (0x1u << 12) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01915 #define PIO_IFSCER_P13 (0x1u << 13) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01916 #define PIO_IFSCER_P14 (0x1u << 14) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01917 #define PIO_IFSCER_P15 (0x1u << 15) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01918 #define PIO_IFSCER_P16 (0x1u << 16) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01919 #define PIO_IFSCER_P17 (0x1u << 17) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01920 #define PIO_IFSCER_P18 (0x1u << 18) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01921 #define PIO_IFSCER_P19 (0x1u << 19) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01922 #define PIO_IFSCER_P20 (0x1u << 20) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01923 #define PIO_IFSCER_P21 (0x1u << 21) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01924 #define PIO_IFSCER_P22 (0x1u << 22) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01925 #define PIO_IFSCER_P23 (0x1u << 23) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01926 #define PIO_IFSCER_P24 (0x1u << 24) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01927 #define PIO_IFSCER_P25 (0x1u << 25) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01928 #define PIO_IFSCER_P26 (0x1u << 26) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01929 #define PIO_IFSCER_P27 (0x1u << 27) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01930 #define PIO_IFSCER_P28 (0x1u << 28) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01931 #define PIO_IFSCER_P29 (0x1u << 29) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01932 #define PIO_IFSCER_P30 (0x1u << 30) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01933 #define PIO_IFSCER_P31 (0x1u << 31) /* (PIO_IFSCER) Debouncing Filtering Select. */ 01934 /* -------- PIO_IFSCSR : (PIO Offset: 0x0088) Input Filter Slow Clock Status Register -------- */ 01935 #define PIO_IFSCSR_P0 (0x1u << 0) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01936 #define PIO_IFSCSR_P1 (0x1u << 1) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01937 #define PIO_IFSCSR_P2 (0x1u << 2) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01938 #define PIO_IFSCSR_P3 (0x1u << 3) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01939 #define PIO_IFSCSR_P4 (0x1u << 4) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01940 #define PIO_IFSCSR_P5 (0x1u << 5) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01941 #define PIO_IFSCSR_P6 (0x1u << 6) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01942 #define PIO_IFSCSR_P7 (0x1u << 7) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01943 #define PIO_IFSCSR_P8 (0x1u << 8) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01944 #define PIO_IFSCSR_P9 (0x1u << 9) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01945 #define PIO_IFSCSR_P10 (0x1u << 10) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01946 #define PIO_IFSCSR_P11 (0x1u << 11) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01947 #define PIO_IFSCSR_P12 (0x1u << 12) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01948 #define PIO_IFSCSR_P13 (0x1u << 13) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01949 #define PIO_IFSCSR_P14 (0x1u << 14) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01950 #define PIO_IFSCSR_P15 (0x1u << 15) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01951 #define PIO_IFSCSR_P16 (0x1u << 16) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01952 #define PIO_IFSCSR_P17 (0x1u << 17) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01953 #define PIO_IFSCSR_P18 (0x1u << 18) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01954 #define PIO_IFSCSR_P19 (0x1u << 19) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01955 #define PIO_IFSCSR_P20 (0x1u << 20) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01956 #define PIO_IFSCSR_P21 (0x1u << 21) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01957 #define PIO_IFSCSR_P22 (0x1u << 22) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01958 #define PIO_IFSCSR_P23 (0x1u << 23) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01959 #define PIO_IFSCSR_P24 (0x1u << 24) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01960 #define PIO_IFSCSR_P25 (0x1u << 25) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01961 #define PIO_IFSCSR_P26 (0x1u << 26) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01962 #define PIO_IFSCSR_P27 (0x1u << 27) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01963 #define PIO_IFSCSR_P28 (0x1u << 28) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01964 #define PIO_IFSCSR_P29 (0x1u << 29) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01965 #define PIO_IFSCSR_P30 (0x1u << 30) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01966 #define PIO_IFSCSR_P31 (0x1u << 31) /* (PIO_IFSCSR) Glitch or Debouncing Filter Selection Status */ 01967 /* -------- PIO_SCDR : (PIO Offset: 0x008C) Slow Clock Divider Debouncing Register -------- */ 01968 #define PIO_SCDR_DIV0 (0x1u << 0) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01969 #define PIO_SCDR_DIV1 (0x1u << 1) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01970 #define PIO_SCDR_DIV2 (0x1u << 2) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01971 #define PIO_SCDR_DIV3 (0x1u << 3) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01972 #define PIO_SCDR_DIV4 (0x1u << 4) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01973 #define PIO_SCDR_DIV5 (0x1u << 5) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01974 #define PIO_SCDR_DIV6 (0x1u << 6) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01975 #define PIO_SCDR_DIV7 (0x1u << 7) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01976 #define PIO_SCDR_DIV8 (0x1u << 8) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01977 #define PIO_SCDR_DIV9 (0x1u << 9) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01978 #define PIO_SCDR_DIV10 (0x1u << 10) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01979 #define PIO_SCDR_DIV11 (0x1u << 11) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01980 #define PIO_SCDR_DIV12 (0x1u << 12) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01981 #define PIO_SCDR_DIV13 (0x1u << 13) /* (PIO_SCDR) Slow Clock Divider Selection for Debouncing */ 01982 /* -------- PIO_PPDDR : (PIO Offset: 0x0090) Pad Pull-down Disable Register -------- */ 01983 #define PIO_PPDDR_P0 (0x1u << 0) /* (PIO_PPDDR) Pull Down Disable. */ 01984 #define PIO_PPDDR_P1 (0x1u << 1) /* (PIO_PPDDR) Pull Down Disable. */ 01985 #define PIO_PPDDR_P2 (0x1u << 2) /* (PIO_PPDDR) Pull Down Disable. */ 01986 #define PIO_PPDDR_P3 (0x1u << 3) /* (PIO_PPDDR) Pull Down Disable. */ 01987 #define PIO_PPDDR_P4 (0x1u << 4) /* (PIO_PPDDR) Pull Down Disable. */ 01988 #define PIO_PPDDR_P5 (0x1u << 5) /* (PIO_PPDDR) Pull Down Disable. */ 01989 #define PIO_PPDDR_P6 (0x1u << 6) /* (PIO_PPDDR) Pull Down Disable. */ 01990 #define PIO_PPDDR_P7 (0x1u << 7) /* (PIO_PPDDR) Pull Down Disable. */ 01991 #define PIO_PPDDR_P8 (0x1u << 8) /* (PIO_PPDDR) Pull Down Disable. */ 01992 #define PIO_PPDDR_P9 (0x1u << 9) /* (PIO_PPDDR) Pull Down Disable. */ 01993 #define PIO_PPDDR_P10 (0x1u << 10) /* (PIO_PPDDR) Pull Down Disable. */ 01994 #define PIO_PPDDR_P11 (0x1u << 11) /* (PIO_PPDDR) Pull Down Disable. */ 01995 #define PIO_PPDDR_P12 (0x1u << 12) /* (PIO_PPDDR) Pull Down Disable. */ 01996 #define PIO_PPDDR_P13 (0x1u << 13) /* (PIO_PPDDR) Pull Down Disable. */ 01997 #define PIO_PPDDR_P14 (0x1u << 14) /* (PIO_PPDDR) Pull Down Disable. */ 01998 #define PIO_PPDDR_P15 (0x1u << 15) /* (PIO_PPDDR) Pull Down Disable. */ 01999 #define PIO_PPDDR_P16 (0x1u << 16) /* (PIO_PPDDR) Pull Down Disable. */ 02000 #define PIO_PPDDR_P17 (0x1u << 17) /* (PIO_PPDDR) Pull Down Disable. */ 02001 #define PIO_PPDDR_P18 (0x1u << 18) /* (PIO_PPDDR) Pull Down Disable. */ 02002 #define PIO_PPDDR_P19 (0x1u << 19) /* (PIO_PPDDR) Pull Down Disable. */ 02003 #define PIO_PPDDR_P20 (0x1u << 20) /* (PIO_PPDDR) Pull Down Disable. */ 02004 #define PIO_PPDDR_P21 (0x1u << 21) /* (PIO_PPDDR) Pull Down Disable. */ 02005 #define PIO_PPDDR_P22 (0x1u << 22) /* (PIO_PPDDR) Pull Down Disable. */ 02006 #define PIO_PPDDR_P23 (0x1u << 23) /* (PIO_PPDDR) Pull Down Disable. */ 02007 #define PIO_PPDDR_P24 (0x1u << 24) /* (PIO_PPDDR) Pull Down Disable. */ 02008 #define PIO_PPDDR_P25 (0x1u << 25) /* (PIO_PPDDR) Pull Down Disable. */ 02009 #define PIO_PPDDR_P26 (0x1u << 26) /* (PIO_PPDDR) Pull Down Disable. */ 02010 #define PIO_PPDDR_P27 (0x1u << 27) /* (PIO_PPDDR) Pull Down Disable. */ 02011 #define PIO_PPDDR_P28 (0x1u << 28) /* (PIO_PPDDR) Pull Down Disable. */ 02012 #define PIO_PPDDR_P29 (0x1u << 29) /* (PIO_PPDDR) Pull Down Disable. */ 02013 #define PIO_PPDDR_P30 (0x1u << 30) /* (PIO_PPDDR) Pull Down Disable. */ 02014 #define PIO_PPDDR_P31 (0x1u << 31) /* (PIO_PPDDR) Pull Down Disable. */ 02015 /* -------- PIO_PPDER : (PIO Offset: 0x0094) Pad Pull-down Enable Register -------- */ 02016 #define PIO_PPDER_P0 (0x1u << 0) /* (PIO_PPDER) Pull Down Enable. */ 02017 #define PIO_PPDER_P1 (0x1u << 1) /* (PIO_PPDER) Pull Down Enable. */ 02018 #define PIO_PPDER_P2 (0x1u << 2) /* (PIO_PPDER) Pull Down Enable. */ 02019 #define PIO_PPDER_P3 (0x1u << 3) /* (PIO_PPDER) Pull Down Enable. */ 02020 #define PIO_PPDER_P4 (0x1u << 4) /* (PIO_PPDER) Pull Down Enable. */ 02021 #define PIO_PPDER_P5 (0x1u << 5) /* (PIO_PPDER) Pull Down Enable. */ 02022 #define PIO_PPDER_P6 (0x1u << 6) /* (PIO_PPDER) Pull Down Enable. */ 02023 #define PIO_PPDER_P7 (0x1u << 7) /* (PIO_PPDER) Pull Down Enable. */ 02024 #define PIO_PPDER_P8 (0x1u << 8) /* (PIO_PPDER) Pull Down Enable. */ 02025 #define PIO_PPDER_P9 (0x1u << 9) /* (PIO_PPDER) Pull Down Enable. */ 02026 #define PIO_PPDER_P10 (0x1u << 10) /* (PIO_PPDER) Pull Down Enable. */ 02027 #define PIO_PPDER_P11 (0x1u << 11) /* (PIO_PPDER) Pull Down Enable. */ 02028 #define PIO_PPDER_P12 (0x1u << 12) /* (PIO_PPDER) Pull Down Enable. */ 02029 #define PIO_PPDER_P13 (0x1u << 13) /* (PIO_PPDER) Pull Down Enable. */ 02030 #define PIO_PPDER_P14 (0x1u << 14) /* (PIO_PPDER) Pull Down Enable. */ 02031 #define PIO_PPDER_P15 (0x1u << 15) /* (PIO_PPDER) Pull Down Enable. */ 02032 #define PIO_PPDER_P16 (0x1u << 16) /* (PIO_PPDER) Pull Down Enable. */ 02033 #define PIO_PPDER_P17 (0x1u << 17) /* (PIO_PPDER) Pull Down Enable. */ 02034 #define PIO_PPDER_P18 (0x1u << 18) /* (PIO_PPDER) Pull Down Enable. */ 02035 #define PIO_PPDER_P19 (0x1u << 19) /* (PIO_PPDER) Pull Down Enable. */ 02036 #define PIO_PPDER_P20 (0x1u << 20) /* (PIO_PPDER) Pull Down Enable. */ 02037 #define PIO_PPDER_P21 (0x1u << 21) /* (PIO_PPDER) Pull Down Enable. */ 02038 #define PIO_PPDER_P22 (0x1u << 22) /* (PIO_PPDER) Pull Down Enable. */ 02039 #define PIO_PPDER_P23 (0x1u << 23) /* (PIO_PPDER) Pull Down Enable. */ 02040 #define PIO_PPDER_P24 (0x1u << 24) /* (PIO_PPDER) Pull Down Enable. */ 02041 #define PIO_PPDER_P25 (0x1u << 25) /* (PIO_PPDER) Pull Down Enable. */ 02042 #define PIO_PPDER_P26 (0x1u << 26) /* (PIO_PPDER) Pull Down Enable. */ 02043 #define PIO_PPDER_P27 (0x1u << 27) /* (PIO_PPDER) Pull Down Enable. */ 02044 #define PIO_PPDER_P28 (0x1u << 28) /* (PIO_PPDER) Pull Down Enable. */ 02045 #define PIO_PPDER_P29 (0x1u << 29) /* (PIO_PPDER) Pull Down Enable. */ 02046 #define PIO_PPDER_P30 (0x1u << 30) /* (PIO_PPDER) Pull Down Enable. */ 02047 #define PIO_PPDER_P31 (0x1u << 31) /* (PIO_PPDER) Pull Down Enable. */ 02048 /* -------- PIO_PPDSR : (PIO Offset: 0x0098) Pad Pull-down Status Register -------- */ 02049 #define PIO_PPDSR_P0 (0x1u << 0) /* (PIO_PPDSR) Pull Down Status. */ 02050 #define PIO_PPDSR_P1 (0x1u << 1) /* (PIO_PPDSR) Pull Down Status. */ 02051 #define PIO_PPDSR_P2 (0x1u << 2) /* (PIO_PPDSR) Pull Down Status. */ 02052 #define PIO_PPDSR_P3 (0x1u << 3) /* (PIO_PPDSR) Pull Down Status. */ 02053 #define PIO_PPDSR_P4 (0x1u << 4) /* (PIO_PPDSR) Pull Down Status. */ 02054 #define PIO_PPDSR_P5 (0x1u << 5) /* (PIO_PPDSR) Pull Down Status. */ 02055 #define PIO_PPDSR_P6 (0x1u << 6) /* (PIO_PPDSR) Pull Down Status. */ 02056 #define PIO_PPDSR_P7 (0x1u << 7) /* (PIO_PPDSR) Pull Down Status. */ 02057 #define PIO_PPDSR_P8 (0x1u << 8) /* (PIO_PPDSR) Pull Down Status. */ 02058 #define PIO_PPDSR_P9 (0x1u << 9) /* (PIO_PPDSR) Pull Down Status. */ 02059 #define PIO_PPDSR_P10 (0x1u << 10) /* (PIO_PPDSR) Pull Down Status. */ 02060 #define PIO_PPDSR_P11 (0x1u << 11) /* (PIO_PPDSR) Pull Down Status. */ 02061 #define PIO_PPDSR_P12 (0x1u << 12) /* (PIO_PPDSR) Pull Down Status. */ 02062 #define PIO_PPDSR_P13 (0x1u << 13) /* (PIO_PPDSR) Pull Down Status. */ 02063 #define PIO_PPDSR_P14 (0x1u << 14) /* (PIO_PPDSR) Pull Down Status. */ 02064 #define PIO_PPDSR_P15 (0x1u << 15) /* (PIO_PPDSR) Pull Down Status. */ 02065 #define PIO_PPDSR_P16 (0x1u << 16) /* (PIO_PPDSR) Pull Down Status. */ 02066 #define PIO_PPDSR_P17 (0x1u << 17) /* (PIO_PPDSR) Pull Down Status. */ 02067 #define PIO_PPDSR_P18 (0x1u << 18) /* (PIO_PPDSR) Pull Down Status. */ 02068 #define PIO_PPDSR_P19 (0x1u << 19) /* (PIO_PPDSR) Pull Down Status. */ 02069 #define PIO_PPDSR_P20 (0x1u << 20) /* (PIO_PPDSR) Pull Down Status. */ 02070 #define PIO_PPDSR_P21 (0x1u << 21) /* (PIO_PPDSR) Pull Down Status. */ 02071 #define PIO_PPDSR_P22 (0x1u << 22) /* (PIO_PPDSR) Pull Down Status. */ 02072 #define PIO_PPDSR_P23 (0x1u << 23) /* (PIO_PPDSR) Pull Down Status. */ 02073 #define PIO_PPDSR_P24 (0x1u << 24) /* (PIO_PPDSR) Pull Down Status. */ 02074 #define PIO_PPDSR_P25 (0x1u << 25) /* (PIO_PPDSR) Pull Down Status. */ 02075 #define PIO_PPDSR_P26 (0x1u << 26) /* (PIO_PPDSR) Pull Down Status. */ 02076 #define PIO_PPDSR_P27 (0x1u << 27) /* (PIO_PPDSR) Pull Down Status. */ 02077 #define PIO_PPDSR_P28 (0x1u << 28) /* (PIO_PPDSR) Pull Down Status. */ 02078 #define PIO_PPDSR_P29 (0x1u << 29) /* (PIO_PPDSR) Pull Down Status. */ 02079 #define PIO_PPDSR_P30 (0x1u << 30) /* (PIO_PPDSR) Pull Down Status. */ 02080 #define PIO_PPDSR_P31 (0x1u << 31) /* (PIO_PPDSR) Pull Down Status. */ 02081 /* -------- PIO_OWER : (PIO Offset: 0x00A0) Output Write Enable -------- */ 02082 #define PIO_OWER_P0 (0x1u << 0) /* (PIO_OWER) Output Write Enable. */ 02083 #define PIO_OWER_P1 (0x1u << 1) /* (PIO_OWER) Output Write Enable. */ 02084 #define PIO_OWER_P2 (0x1u << 2) /* (PIO_OWER) Output Write Enable. */ 02085 #define PIO_OWER_P3 (0x1u << 3) /* (PIO_OWER) Output Write Enable. */ 02086 #define PIO_OWER_P4 (0x1u << 4) /* (PIO_OWER) Output Write Enable. */ 02087 #define PIO_OWER_P5 (0x1u << 5) /* (PIO_OWER) Output Write Enable. */ 02088 #define PIO_OWER_P6 (0x1u << 6) /* (PIO_OWER) Output Write Enable. */ 02089 #define PIO_OWER_P7 (0x1u << 7) /* (PIO_OWER) Output Write Enable. */ 02090 #define PIO_OWER_P8 (0x1u << 8) /* (PIO_OWER) Output Write Enable. */ 02091 #define PIO_OWER_P9 (0x1u << 9) /* (PIO_OWER) Output Write Enable. */ 02092 #define PIO_OWER_P10 (0x1u << 10) /* (PIO_OWER) Output Write Enable. */ 02093 #define PIO_OWER_P11 (0x1u << 11) /* (PIO_OWER) Output Write Enable. */ 02094 #define PIO_OWER_P12 (0x1u << 12) /* (PIO_OWER) Output Write Enable. */ 02095 #define PIO_OWER_P13 (0x1u << 13) /* (PIO_OWER) Output Write Enable. */ 02096 #define PIO_OWER_P14 (0x1u << 14) /* (PIO_OWER) Output Write Enable. */ 02097 #define PIO_OWER_P15 (0x1u << 15) /* (PIO_OWER) Output Write Enable. */ 02098 #define PIO_OWER_P16 (0x1u << 16) /* (PIO_OWER) Output Write Enable. */ 02099 #define PIO_OWER_P17 (0x1u << 17) /* (PIO_OWER) Output Write Enable. */ 02100 #define PIO_OWER_P18 (0x1u << 18) /* (PIO_OWER) Output Write Enable. */ 02101 #define PIO_OWER_P19 (0x1u << 19) /* (PIO_OWER) Output Write Enable. */ 02102 #define PIO_OWER_P20 (0x1u << 20) /* (PIO_OWER) Output Write Enable. */ 02103 #define PIO_OWER_P21 (0x1u << 21) /* (PIO_OWER) Output Write Enable. */ 02104 #define PIO_OWER_P22 (0x1u << 22) /* (PIO_OWER) Output Write Enable. */ 02105 #define PIO_OWER_P23 (0x1u << 23) /* (PIO_OWER) Output Write Enable. */ 02106 #define PIO_OWER_P24 (0x1u << 24) /* (PIO_OWER) Output Write Enable. */ 02107 #define PIO_OWER_P25 (0x1u << 25) /* (PIO_OWER) Output Write Enable. */ 02108 #define PIO_OWER_P26 (0x1u << 26) /* (PIO_OWER) Output Write Enable. */ 02109 #define PIO_OWER_P27 (0x1u << 27) /* (PIO_OWER) Output Write Enable. */ 02110 #define PIO_OWER_P28 (0x1u << 28) /* (PIO_OWER) Output Write Enable. */ 02111 #define PIO_OWER_P29 (0x1u << 29) /* (PIO_OWER) Output Write Enable. */ 02112 #define PIO_OWER_P30 (0x1u << 30) /* (PIO_OWER) Output Write Enable. */ 02113 #define PIO_OWER_P31 (0x1u << 31) /* (PIO_OWER) Output Write Enable. */ 02114 /* -------- PIO_OWDR : (PIO Offset: 0x00A4) Output Write Disable -------- */ 02115 #define PIO_OWDR_P0 (0x1u << 0) /* (PIO_OWDR) Output Write Disable. */ 02116 #define PIO_OWDR_P1 (0x1u << 1) /* (PIO_OWDR) Output Write Disable. */ 02117 #define PIO_OWDR_P2 (0x1u << 2) /* (PIO_OWDR) Output Write Disable. */ 02118 #define PIO_OWDR_P3 (0x1u << 3) /* (PIO_OWDR) Output Write Disable. */ 02119 #define PIO_OWDR_P4 (0x1u << 4) /* (PIO_OWDR) Output Write Disable. */ 02120 #define PIO_OWDR_P5 (0x1u << 5) /* (PIO_OWDR) Output Write Disable. */ 02121 #define PIO_OWDR_P6 (0x1u << 6) /* (PIO_OWDR) Output Write Disable. */ 02122 #define PIO_OWDR_P7 (0x1u << 7) /* (PIO_OWDR) Output Write Disable. */ 02123 #define PIO_OWDR_P8 (0x1u << 8) /* (PIO_OWDR) Output Write Disable. */ 02124 #define PIO_OWDR_P9 (0x1u << 9) /* (PIO_OWDR) Output Write Disable. */ 02125 #define PIO_OWDR_P10 (0x1u << 10) /* (PIO_OWDR) Output Write Disable. */ 02126 #define PIO_OWDR_P11 (0x1u << 11) /* (PIO_OWDR) Output Write Disable. */ 02127 #define PIO_OWDR_P12 (0x1u << 12) /* (PIO_OWDR) Output Write Disable. */ 02128 #define PIO_OWDR_P13 (0x1u << 13) /* (PIO_OWDR) Output Write Disable. */ 02129 #define PIO_OWDR_P14 (0x1u << 14) /* (PIO_OWDR) Output Write Disable. */ 02130 #define PIO_OWDR_P15 (0x1u << 15) /* (PIO_OWDR) Output Write Disable. */ 02131 #define PIO_OWDR_P16 (0x1u << 16) /* (PIO_OWDR) Output Write Disable. */ 02132 #define PIO_OWDR_P17 (0x1u << 17) /* (PIO_OWDR) Output Write Disable. */ 02133 #define PIO_OWDR_P18 (0x1u << 18) /* (PIO_OWDR) Output Write Disable. */ 02134 #define PIO_OWDR_P19 (0x1u << 19) /* (PIO_OWDR) Output Write Disable. */ 02135 #define PIO_OWDR_P20 (0x1u << 20) /* (PIO_OWDR) Output Write Disable. */ 02136 #define PIO_OWDR_P21 (0x1u << 21) /* (PIO_OWDR) Output Write Disable. */ 02137 #define PIO_OWDR_P22 (0x1u << 22) /* (PIO_OWDR) Output Write Disable. */ 02138 #define PIO_OWDR_P23 (0x1u << 23) /* (PIO_OWDR) Output Write Disable. */ 02139 #define PIO_OWDR_P24 (0x1u << 24) /* (PIO_OWDR) Output Write Disable. */ 02140 #define PIO_OWDR_P25 (0x1u << 25) /* (PIO_OWDR) Output Write Disable. */ 02141 #define PIO_OWDR_P26 (0x1u << 26) /* (PIO_OWDR) Output Write Disable. */ 02142 #define PIO_OWDR_P27 (0x1u << 27) /* (PIO_OWDR) Output Write Disable. */ 02143 #define PIO_OWDR_P28 (0x1u << 28) /* (PIO_OWDR) Output Write Disable. */ 02144 #define PIO_OWDR_P29 (0x1u << 29) /* (PIO_OWDR) Output Write Disable. */ 02145 #define PIO_OWDR_P30 (0x1u << 30) /* (PIO_OWDR) Output Write Disable. */ 02146 #define PIO_OWDR_P31 (0x1u << 31) /* (PIO_OWDR) Output Write Disable. */ 02147 /* -------- PIO_OWSR : (PIO Offset: 0x00A8) Output Write Status Register -------- */ 02148 #define PIO_OWSR_P0 (0x1u << 0) /* (PIO_OWSR) Output Write Status. */ 02149 #define PIO_OWSR_P1 (0x1u << 1) /* (PIO_OWSR) Output Write Status. */ 02150 #define PIO_OWSR_P2 (0x1u << 2) /* (PIO_OWSR) Output Write Status. */ 02151 #define PIO_OWSR_P3 (0x1u << 3) /* (PIO_OWSR) Output Write Status. */ 02152 #define PIO_OWSR_P4 (0x1u << 4) /* (PIO_OWSR) Output Write Status. */ 02153 #define PIO_OWSR_P5 (0x1u << 5) /* (PIO_OWSR) Output Write Status. */ 02154 #define PIO_OWSR_P6 (0x1u << 6) /* (PIO_OWSR) Output Write Status. */ 02155 #define PIO_OWSR_P7 (0x1u << 7) /* (PIO_OWSR) Output Write Status. */ 02156 #define PIO_OWSR_P8 (0x1u << 8) /* (PIO_OWSR) Output Write Status. */ 02157 #define PIO_OWSR_P9 (0x1u << 9) /* (PIO_OWSR) Output Write Status. */ 02158 #define PIO_OWSR_P10 (0x1u << 10) /* (PIO_OWSR) Output Write Status. */ 02159 #define PIO_OWSR_P11 (0x1u << 11) /* (PIO_OWSR) Output Write Status. */ 02160 #define PIO_OWSR_P12 (0x1u << 12) /* (PIO_OWSR) Output Write Status. */ 02161 #define PIO_OWSR_P13 (0x1u << 13) /* (PIO_OWSR) Output Write Status. */ 02162 #define PIO_OWSR_P14 (0x1u << 14) /* (PIO_OWSR) Output Write Status. */ 02163 #define PIO_OWSR_P15 (0x1u << 15) /* (PIO_OWSR) Output Write Status. */ 02164 #define PIO_OWSR_P16 (0x1u << 16) /* (PIO_OWSR) Output Write Status. */ 02165 #define PIO_OWSR_P17 (0x1u << 17) /* (PIO_OWSR) Output Write Status. */ 02166 #define PIO_OWSR_P18 (0x1u << 18) /* (PIO_OWSR) Output Write Status. */ 02167 #define PIO_OWSR_P19 (0x1u << 19) /* (PIO_OWSR) Output Write Status. */ 02168 #define PIO_OWSR_P20 (0x1u << 20) /* (PIO_OWSR) Output Write Status. */ 02169 #define PIO_OWSR_P21 (0x1u << 21) /* (PIO_OWSR) Output Write Status. */ 02170 #define PIO_OWSR_P22 (0x1u << 22) /* (PIO_OWSR) Output Write Status. */ 02171 #define PIO_OWSR_P23 (0x1u << 23) /* (PIO_OWSR) Output Write Status. */ 02172 #define PIO_OWSR_P24 (0x1u << 24) /* (PIO_OWSR) Output Write Status. */ 02173 #define PIO_OWSR_P25 (0x1u << 25) /* (PIO_OWSR) Output Write Status. */ 02174 #define PIO_OWSR_P26 (0x1u << 26) /* (PIO_OWSR) Output Write Status. */ 02175 #define PIO_OWSR_P27 (0x1u << 27) /* (PIO_OWSR) Output Write Status. */ 02176 #define PIO_OWSR_P28 (0x1u << 28) /* (PIO_OWSR) Output Write Status. */ 02177 #define PIO_OWSR_P29 (0x1u << 29) /* (PIO_OWSR) Output Write Status. */ 02178 #define PIO_OWSR_P30 (0x1u << 30) /* (PIO_OWSR) Output Write Status. */ 02179 #define PIO_OWSR_P31 (0x1u << 31) /* (PIO_OWSR) Output Write Status. */ 02180 /* -------- PIO_AIMER : (PIO Offset: 0x00B0) Additional Interrupt Modes Enable Register -------- */ 02181 #define PIO_AIMER_P0 (0x1u << 0) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02182 #define PIO_AIMER_P1 (0x1u << 1) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02183 #define PIO_AIMER_P2 (0x1u << 2) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02184 #define PIO_AIMER_P3 (0x1u << 3) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02185 #define PIO_AIMER_P4 (0x1u << 4) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02186 #define PIO_AIMER_P5 (0x1u << 5) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02187 #define PIO_AIMER_P6 (0x1u << 6) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02188 #define PIO_AIMER_P7 (0x1u << 7) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02189 #define PIO_AIMER_P8 (0x1u << 8) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02190 #define PIO_AIMER_P9 (0x1u << 9) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02191 #define PIO_AIMER_P10 (0x1u << 10) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02192 #define PIO_AIMER_P11 (0x1u << 11) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02193 #define PIO_AIMER_P12 (0x1u << 12) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02194 #define PIO_AIMER_P13 (0x1u << 13) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02195 #define PIO_AIMER_P14 (0x1u << 14) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02196 #define PIO_AIMER_P15 (0x1u << 15) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02197 #define PIO_AIMER_P16 (0x1u << 16) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02198 #define PIO_AIMER_P17 (0x1u << 17) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02199 #define PIO_AIMER_P18 (0x1u << 18) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02200 #define PIO_AIMER_P19 (0x1u << 19) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02201 #define PIO_AIMER_P20 (0x1u << 20) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02202 #define PIO_AIMER_P21 (0x1u << 21) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02203 #define PIO_AIMER_P22 (0x1u << 22) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02204 #define PIO_AIMER_P23 (0x1u << 23) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02205 #define PIO_AIMER_P24 (0x1u << 24) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02206 #define PIO_AIMER_P25 (0x1u << 25) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02207 #define PIO_AIMER_P26 (0x1u << 26) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02208 #define PIO_AIMER_P27 (0x1u << 27) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02209 #define PIO_AIMER_P28 (0x1u << 28) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02210 #define PIO_AIMER_P29 (0x1u << 29) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02211 #define PIO_AIMER_P30 (0x1u << 30) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02212 #define PIO_AIMER_P31 (0x1u << 31) /* (PIO_AIMER) Additional Interrupt Modes Enable. */ 02213 /* -------- PIO_AIMDR : (PIO Offset: 0x00B4) Additional Interrupt Modes Disables Register -------- */ 02214 #define PIO_AIMDR_P0 (0x1u << 0) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02215 #define PIO_AIMDR_P1 (0x1u << 1) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02216 #define PIO_AIMDR_P2 (0x1u << 2) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02217 #define PIO_AIMDR_P3 (0x1u << 3) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02218 #define PIO_AIMDR_P4 (0x1u << 4) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02219 #define PIO_AIMDR_P5 (0x1u << 5) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02220 #define PIO_AIMDR_P6 (0x1u << 6) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02221 #define PIO_AIMDR_P7 (0x1u << 7) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02222 #define PIO_AIMDR_P8 (0x1u << 8) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02223 #define PIO_AIMDR_P9 (0x1u << 9) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02224 #define PIO_AIMDR_P10 (0x1u << 10) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02225 #define PIO_AIMDR_P11 (0x1u << 11) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02226 #define PIO_AIMDR_P12 (0x1u << 12) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02227 #define PIO_AIMDR_P13 (0x1u << 13) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02228 #define PIO_AIMDR_P14 (0x1u << 14) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02229 #define PIO_AIMDR_P15 (0x1u << 15) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02230 #define PIO_AIMDR_P16 (0x1u << 16) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02231 #define PIO_AIMDR_P17 (0x1u << 17) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02232 #define PIO_AIMDR_P18 (0x1u << 18) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02233 #define PIO_AIMDR_P19 (0x1u << 19) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02234 #define PIO_AIMDR_P20 (0x1u << 20) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02235 #define PIO_AIMDR_P21 (0x1u << 21) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02236 #define PIO_AIMDR_P22 (0x1u << 22) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02237 #define PIO_AIMDR_P23 (0x1u << 23) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02238 #define PIO_AIMDR_P24 (0x1u << 24) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02239 #define PIO_AIMDR_P25 (0x1u << 25) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02240 #define PIO_AIMDR_P26 (0x1u << 26) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02241 #define PIO_AIMDR_P27 (0x1u << 27) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02242 #define PIO_AIMDR_P28 (0x1u << 28) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02243 #define PIO_AIMDR_P29 (0x1u << 29) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02244 #define PIO_AIMDR_P30 (0x1u << 30) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02245 #define PIO_AIMDR_P31 (0x1u << 31) /* (PIO_AIMDR) Additional Interrupt Modes Disable. */ 02246 /* -------- PIO_AIMMR : (PIO Offset: 0x00B8) Additional Interrupt Modes Mask Register -------- */ 02247 #define PIO_AIMMR_P0 (0x1u << 0) /* (PIO_AIMMR) Peripheral CD Status. */ 02248 #define PIO_AIMMR_P1 (0x1u << 1) /* (PIO_AIMMR) Peripheral CD Status. */ 02249 #define PIO_AIMMR_P2 (0x1u << 2) /* (PIO_AIMMR) Peripheral CD Status. */ 02250 #define PIO_AIMMR_P3 (0x1u << 3) /* (PIO_AIMMR) Peripheral CD Status. */ 02251 #define PIO_AIMMR_P4 (0x1u << 4) /* (PIO_AIMMR) Peripheral CD Status. */ 02252 #define PIO_AIMMR_P5 (0x1u << 5) /* (PIO_AIMMR) Peripheral CD Status. */ 02253 #define PIO_AIMMR_P6 (0x1u << 6) /* (PIO_AIMMR) Peripheral CD Status. */ 02254 #define PIO_AIMMR_P7 (0x1u << 7) /* (PIO_AIMMR) Peripheral CD Status. */ 02255 #define PIO_AIMMR_P8 (0x1u << 8) /* (PIO_AIMMR) Peripheral CD Status. */ 02256 #define PIO_AIMMR_P9 (0x1u << 9) /* (PIO_AIMMR) Peripheral CD Status. */ 02257 #define PIO_AIMMR_P10 (0x1u << 10) /* (PIO_AIMMR) Peripheral CD Status. */ 02258 #define PIO_AIMMR_P11 (0x1u << 11) /* (PIO_AIMMR) Peripheral CD Status. */ 02259 #define PIO_AIMMR_P12 (0x1u << 12) /* (PIO_AIMMR) Peripheral CD Status. */ 02260 #define PIO_AIMMR_P13 (0x1u << 13) /* (PIO_AIMMR) Peripheral CD Status. */ 02261 #define PIO_AIMMR_P14 (0x1u << 14) /* (PIO_AIMMR) Peripheral CD Status. */ 02262 #define PIO_AIMMR_P15 (0x1u << 15) /* (PIO_AIMMR) Peripheral CD Status. */ 02263 #define PIO_AIMMR_P16 (0x1u << 16) /* (PIO_AIMMR) Peripheral CD Status. */ 02264 #define PIO_AIMMR_P17 (0x1u << 17) /* (PIO_AIMMR) Peripheral CD Status. */ 02265 #define PIO_AIMMR_P18 (0x1u << 18) /* (PIO_AIMMR) Peripheral CD Status. */ 02266 #define PIO_AIMMR_P19 (0x1u << 19) /* (PIO_AIMMR) Peripheral CD Status. */ 02267 #define PIO_AIMMR_P20 (0x1u << 20) /* (PIO_AIMMR) Peripheral CD Status. */ 02268 #define PIO_AIMMR_P21 (0x1u << 21) /* (PIO_AIMMR) Peripheral CD Status. */ 02269 #define PIO_AIMMR_P22 (0x1u << 22) /* (PIO_AIMMR) Peripheral CD Status. */ 02270 #define PIO_AIMMR_P23 (0x1u << 23) /* (PIO_AIMMR) Peripheral CD Status. */ 02271 #define PIO_AIMMR_P24 (0x1u << 24) /* (PIO_AIMMR) Peripheral CD Status. */ 02272 #define PIO_AIMMR_P25 (0x1u << 25) /* (PIO_AIMMR) Peripheral CD Status. */ 02273 #define PIO_AIMMR_P26 (0x1u << 26) /* (PIO_AIMMR) Peripheral CD Status. */ 02274 #define PIO_AIMMR_P27 (0x1u << 27) /* (PIO_AIMMR) Peripheral CD Status. */ 02275 #define PIO_AIMMR_P28 (0x1u << 28) /* (PIO_AIMMR) Peripheral CD Status. */ 02276 #define PIO_AIMMR_P29 (0x1u << 29) /* (PIO_AIMMR) Peripheral CD Status. */ 02277 #define PIO_AIMMR_P30 (0x1u << 30) /* (PIO_AIMMR) Peripheral CD Status. */ 02278 #define PIO_AIMMR_P31 (0x1u << 31) /* (PIO_AIMMR) Peripheral CD Status. */ 02279 /* -------- PIO_ESR : (PIO Offset: 0x00C0) Edge Select Register -------- */ 02280 #define PIO_ESR_P0 (0x1u << 0) /* (PIO_ESR) Edge Interrupt Selection. */ 02281 #define PIO_ESR_P1 (0x1u << 1) /* (PIO_ESR) Edge Interrupt Selection. */ 02282 #define PIO_ESR_P2 (0x1u << 2) /* (PIO_ESR) Edge Interrupt Selection. */ 02283 #define PIO_ESR_P3 (0x1u << 3) /* (PIO_ESR) Edge Interrupt Selection. */ 02284 #define PIO_ESR_P4 (0x1u << 4) /* (PIO_ESR) Edge Interrupt Selection. */ 02285 #define PIO_ESR_P5 (0x1u << 5) /* (PIO_ESR) Edge Interrupt Selection. */ 02286 #define PIO_ESR_P6 (0x1u << 6) /* (PIO_ESR) Edge Interrupt Selection. */ 02287 #define PIO_ESR_P7 (0x1u << 7) /* (PIO_ESR) Edge Interrupt Selection. */ 02288 #define PIO_ESR_P8 (0x1u << 8) /* (PIO_ESR) Edge Interrupt Selection. */ 02289 #define PIO_ESR_P9 (0x1u << 9) /* (PIO_ESR) Edge Interrupt Selection. */ 02290 #define PIO_ESR_P10 (0x1u << 10) /* (PIO_ESR) Edge Interrupt Selection. */ 02291 #define PIO_ESR_P11 (0x1u << 11) /* (PIO_ESR) Edge Interrupt Selection. */ 02292 #define PIO_ESR_P12 (0x1u << 12) /* (PIO_ESR) Edge Interrupt Selection. */ 02293 #define PIO_ESR_P13 (0x1u << 13) /* (PIO_ESR) Edge Interrupt Selection. */ 02294 #define PIO_ESR_P14 (0x1u << 14) /* (PIO_ESR) Edge Interrupt Selection. */ 02295 #define PIO_ESR_P15 (0x1u << 15) /* (PIO_ESR) Edge Interrupt Selection. */ 02296 #define PIO_ESR_P16 (0x1u << 16) /* (PIO_ESR) Edge Interrupt Selection. */ 02297 #define PIO_ESR_P17 (0x1u << 17) /* (PIO_ESR) Edge Interrupt Selection. */ 02298 #define PIO_ESR_P18 (0x1u << 18) /* (PIO_ESR) Edge Interrupt Selection. */ 02299 #define PIO_ESR_P19 (0x1u << 19) /* (PIO_ESR) Edge Interrupt Selection. */ 02300 #define PIO_ESR_P20 (0x1u << 20) /* (PIO_ESR) Edge Interrupt Selection. */ 02301 #define PIO_ESR_P21 (0x1u << 21) /* (PIO_ESR) Edge Interrupt Selection. */ 02302 #define PIO_ESR_P22 (0x1u << 22) /* (PIO_ESR) Edge Interrupt Selection. */ 02303 #define PIO_ESR_P23 (0x1u << 23) /* (PIO_ESR) Edge Interrupt Selection. */ 02304 #define PIO_ESR_P24 (0x1u << 24) /* (PIO_ESR) Edge Interrupt Selection. */ 02305 #define PIO_ESR_P25 (0x1u << 25) /* (PIO_ESR) Edge Interrupt Selection. */ 02306 #define PIO_ESR_P26 (0x1u << 26) /* (PIO_ESR) Edge Interrupt Selection. */ 02307 #define PIO_ESR_P27 (0x1u << 27) /* (PIO_ESR) Edge Interrupt Selection. */ 02308 #define PIO_ESR_P28 (0x1u << 28) /* (PIO_ESR) Edge Interrupt Selection. */ 02309 #define PIO_ESR_P29 (0x1u << 29) /* (PIO_ESR) Edge Interrupt Selection. */ 02310 #define PIO_ESR_P30 (0x1u << 30) /* (PIO_ESR) Edge Interrupt Selection. */ 02311 #define PIO_ESR_P31 (0x1u << 31) /* (PIO_ESR) Edge Interrupt Selection. */ 02312 /* -------- PIO_LSR : (PIO Offset: 0x00C4) Level Select Register -------- */ 02313 #define PIO_LSR_P0 (0x1u << 0) /* (PIO_LSR) Level Interrupt Selection. */ 02314 #define PIO_LSR_P1 (0x1u << 1) /* (PIO_LSR) Level Interrupt Selection. */ 02315 #define PIO_LSR_P2 (0x1u << 2) /* (PIO_LSR) Level Interrupt Selection. */ 02316 #define PIO_LSR_P3 (0x1u << 3) /* (PIO_LSR) Level Interrupt Selection. */ 02317 #define PIO_LSR_P4 (0x1u << 4) /* (PIO_LSR) Level Interrupt Selection. */ 02318 #define PIO_LSR_P5 (0x1u << 5) /* (PIO_LSR) Level Interrupt Selection. */ 02319 #define PIO_LSR_P6 (0x1u << 6) /* (PIO_LSR) Level Interrupt Selection. */ 02320 #define PIO_LSR_P7 (0x1u << 7) /* (PIO_LSR) Level Interrupt Selection. */ 02321 #define PIO_LSR_P8 (0x1u << 8) /* (PIO_LSR) Level Interrupt Selection. */ 02322 #define PIO_LSR_P9 (0x1u << 9) /* (PIO_LSR) Level Interrupt Selection. */ 02323 #define PIO_LSR_P10 (0x1u << 10) /* (PIO_LSR) Level Interrupt Selection. */ 02324 #define PIO_LSR_P11 (0x1u << 11) /* (PIO_LSR) Level Interrupt Selection. */ 02325 #define PIO_LSR_P12 (0x1u << 12) /* (PIO_LSR) Level Interrupt Selection. */ 02326 #define PIO_LSR_P13 (0x1u << 13) /* (PIO_LSR) Level Interrupt Selection. */ 02327 #define PIO_LSR_P14 (0x1u << 14) /* (PIO_LSR) Level Interrupt Selection. */ 02328 #define PIO_LSR_P15 (0x1u << 15) /* (PIO_LSR) Level Interrupt Selection. */ 02329 #define PIO_LSR_P16 (0x1u << 16) /* (PIO_LSR) Level Interrupt Selection. */ 02330 #define PIO_LSR_P17 (0x1u << 17) /* (PIO_LSR) Level Interrupt Selection. */ 02331 #define PIO_LSR_P18 (0x1u << 18) /* (PIO_LSR) Level Interrupt Selection. */ 02332 #define PIO_LSR_P19 (0x1u << 19) /* (PIO_LSR) Level Interrupt Selection. */ 02333 #define PIO_LSR_P20 (0x1u << 20) /* (PIO_LSR) Level Interrupt Selection. */ 02334 #define PIO_LSR_P21 (0x1u << 21) /* (PIO_LSR) Level Interrupt Selection. */ 02335 #define PIO_LSR_P22 (0x1u << 22) /* (PIO_LSR) Level Interrupt Selection. */ 02336 #define PIO_LSR_P23 (0x1u << 23) /* (PIO_LSR) Level Interrupt Selection. */ 02337 #define PIO_LSR_P24 (0x1u << 24) /* (PIO_LSR) Level Interrupt Selection. */ 02338 #define PIO_LSR_P25 (0x1u << 25) /* (PIO_LSR) Level Interrupt Selection. */ 02339 #define PIO_LSR_P26 (0x1u << 26) /* (PIO_LSR) Level Interrupt Selection. */ 02340 #define PIO_LSR_P27 (0x1u << 27) /* (PIO_LSR) Level Interrupt Selection. */ 02341 #define PIO_LSR_P28 (0x1u << 28) /* (PIO_LSR) Level Interrupt Selection. */ 02342 #define PIO_LSR_P29 (0x1u << 29) /* (PIO_LSR) Level Interrupt Selection. */ 02343 #define PIO_LSR_P30 (0x1u << 30) /* (PIO_LSR) Level Interrupt Selection. */ 02344 #define PIO_LSR_P31 (0x1u << 31) /* (PIO_LSR) Level Interrupt Selection. */ 02345 /* -------- PIO_ELSR : (PIO Offset: 0x00C8) Edge/Level Status Register -------- */ 02346 #define PIO_ELSR_P0 (0x1u << 0) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02347 #define PIO_ELSR_P1 (0x1u << 1) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02348 #define PIO_ELSR_P2 (0x1u << 2) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02349 #define PIO_ELSR_P3 (0x1u << 3) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02350 #define PIO_ELSR_P4 (0x1u << 4) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02351 #define PIO_ELSR_P5 (0x1u << 5) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02352 #define PIO_ELSR_P6 (0x1u << 6) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02353 #define PIO_ELSR_P7 (0x1u << 7) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02354 #define PIO_ELSR_P8 (0x1u << 8) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02355 #define PIO_ELSR_P9 (0x1u << 9) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02356 #define PIO_ELSR_P10 (0x1u << 10) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02357 #define PIO_ELSR_P11 (0x1u << 11) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02358 #define PIO_ELSR_P12 (0x1u << 12) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02359 #define PIO_ELSR_P13 (0x1u << 13) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02360 #define PIO_ELSR_P14 (0x1u << 14) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02361 #define PIO_ELSR_P15 (0x1u << 15) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02362 #define PIO_ELSR_P16 (0x1u << 16) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02363 #define PIO_ELSR_P17 (0x1u << 17) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02364 #define PIO_ELSR_P18 (0x1u << 18) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02365 #define PIO_ELSR_P19 (0x1u << 19) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02366 #define PIO_ELSR_P20 (0x1u << 20) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02367 #define PIO_ELSR_P21 (0x1u << 21) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02368 #define PIO_ELSR_P22 (0x1u << 22) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02369 #define PIO_ELSR_P23 (0x1u << 23) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02370 #define PIO_ELSR_P24 (0x1u << 24) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02371 #define PIO_ELSR_P25 (0x1u << 25) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02372 #define PIO_ELSR_P26 (0x1u << 26) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02373 #define PIO_ELSR_P27 (0x1u << 27) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02374 #define PIO_ELSR_P28 (0x1u << 28) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02375 #define PIO_ELSR_P29 (0x1u << 29) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02376 #define PIO_ELSR_P30 (0x1u << 30) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02377 #define PIO_ELSR_P31 (0x1u << 31) /* (PIO_ELSR) Edge/Level Interrupt source selection. */ 02378 /* -------- PIO_FELLSR : (PIO Offset: 0x00D0) Falling Edge/Low Level Select Register -------- */ 02379 #define PIO_FELLSR_P0 (0x1u << 0) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02380 #define PIO_FELLSR_P1 (0x1u << 1) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02381 #define PIO_FELLSR_P2 (0x1u << 2) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02382 #define PIO_FELLSR_P3 (0x1u << 3) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02383 #define PIO_FELLSR_P4 (0x1u << 4) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02384 #define PIO_FELLSR_P5 (0x1u << 5) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02385 #define PIO_FELLSR_P6 (0x1u << 6) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02386 #define PIO_FELLSR_P7 (0x1u << 7) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02387 #define PIO_FELLSR_P8 (0x1u << 8) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02388 #define PIO_FELLSR_P9 (0x1u << 9) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02389 #define PIO_FELLSR_P10 (0x1u << 10) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02390 #define PIO_FELLSR_P11 (0x1u << 11) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02391 #define PIO_FELLSR_P12 (0x1u << 12) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02392 #define PIO_FELLSR_P13 (0x1u << 13) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02393 #define PIO_FELLSR_P14 (0x1u << 14) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02394 #define PIO_FELLSR_P15 (0x1u << 15) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02395 #define PIO_FELLSR_P16 (0x1u << 16) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02396 #define PIO_FELLSR_P17 (0x1u << 17) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02397 #define PIO_FELLSR_P18 (0x1u << 18) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02398 #define PIO_FELLSR_P19 (0x1u << 19) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02399 #define PIO_FELLSR_P20 (0x1u << 20) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02400 #define PIO_FELLSR_P21 (0x1u << 21) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02401 #define PIO_FELLSR_P22 (0x1u << 22) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02402 #define PIO_FELLSR_P23 (0x1u << 23) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02403 #define PIO_FELLSR_P24 (0x1u << 24) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02404 #define PIO_FELLSR_P25 (0x1u << 25) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02405 #define PIO_FELLSR_P26 (0x1u << 26) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02406 #define PIO_FELLSR_P27 (0x1u << 27) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02407 #define PIO_FELLSR_P28 (0x1u << 28) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02408 #define PIO_FELLSR_P29 (0x1u << 29) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02409 #define PIO_FELLSR_P30 (0x1u << 30) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02410 #define PIO_FELLSR_P31 (0x1u << 31) /* (PIO_FELLSR) Falling Edge/Low Level Interrupt Selection. */ 02411 /* -------- PIO_REHLSR : (PIO Offset: 0x00D4) Rising Edge/ High Level Select Register -------- */ 02412 #define PIO_REHLSR_P0 (0x1u << 0) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02413 #define PIO_REHLSR_P1 (0x1u << 1) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02414 #define PIO_REHLSR_P2 (0x1u << 2) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02415 #define PIO_REHLSR_P3 (0x1u << 3) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02416 #define PIO_REHLSR_P4 (0x1u << 4) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02417 #define PIO_REHLSR_P5 (0x1u << 5) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02418 #define PIO_REHLSR_P6 (0x1u << 6) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02419 #define PIO_REHLSR_P7 (0x1u << 7) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02420 #define PIO_REHLSR_P8 (0x1u << 8) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02421 #define PIO_REHLSR_P9 (0x1u << 9) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02422 #define PIO_REHLSR_P10 (0x1u << 10) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02423 #define PIO_REHLSR_P11 (0x1u << 11) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02424 #define PIO_REHLSR_P12 (0x1u << 12) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02425 #define PIO_REHLSR_P13 (0x1u << 13) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02426 #define PIO_REHLSR_P14 (0x1u << 14) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02427 #define PIO_REHLSR_P15 (0x1u << 15) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02428 #define PIO_REHLSR_P16 (0x1u << 16) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02429 #define PIO_REHLSR_P17 (0x1u << 17) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02430 #define PIO_REHLSR_P18 (0x1u << 18) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02431 #define PIO_REHLSR_P19 (0x1u << 19) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02432 #define PIO_REHLSR_P20 (0x1u << 20) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02433 #define PIO_REHLSR_P21 (0x1u << 21) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02434 #define PIO_REHLSR_P22 (0x1u << 22) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02435 #define PIO_REHLSR_P23 (0x1u << 23) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02436 #define PIO_REHLSR_P24 (0x1u << 24) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02437 #define PIO_REHLSR_P25 (0x1u << 25) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02438 #define PIO_REHLSR_P26 (0x1u << 26) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02439 #define PIO_REHLSR_P27 (0x1u << 27) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02440 #define PIO_REHLSR_P28 (0x1u << 28) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02441 #define PIO_REHLSR_P29 (0x1u << 29) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02442 #define PIO_REHLSR_P30 (0x1u << 30) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02443 #define PIO_REHLSR_P31 (0x1u << 31) /* (PIO_REHLSR) Rising Edge /High Level Interrupt Selection. */ 02444 /* -------- PIO_FRLHSR : (PIO Offset: 0x00D8) Fall/Rise - Low/High Status Register -------- */ 02445 #define PIO_FRLHSR_P0 (0x1u << 0) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02446 #define PIO_FRLHSR_P1 (0x1u << 1) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02447 #define PIO_FRLHSR_P2 (0x1u << 2) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02448 #define PIO_FRLHSR_P3 (0x1u << 3) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02449 #define PIO_FRLHSR_P4 (0x1u << 4) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02450 #define PIO_FRLHSR_P5 (0x1u << 5) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02451 #define PIO_FRLHSR_P6 (0x1u << 6) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02452 #define PIO_FRLHSR_P7 (0x1u << 7) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02453 #define PIO_FRLHSR_P8 (0x1u << 8) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02454 #define PIO_FRLHSR_P9 (0x1u << 9) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02455 #define PIO_FRLHSR_P10 (0x1u << 10) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02456 #define PIO_FRLHSR_P11 (0x1u << 11) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02457 #define PIO_FRLHSR_P12 (0x1u << 12) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02458 #define PIO_FRLHSR_P13 (0x1u << 13) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02459 #define PIO_FRLHSR_P14 (0x1u << 14) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02460 #define PIO_FRLHSR_P15 (0x1u << 15) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02461 #define PIO_FRLHSR_P16 (0x1u << 16) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02462 #define PIO_FRLHSR_P17 (0x1u << 17) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02463 #define PIO_FRLHSR_P18 (0x1u << 18) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02464 #define PIO_FRLHSR_P19 (0x1u << 19) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02465 #define PIO_FRLHSR_P20 (0x1u << 20) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02466 #define PIO_FRLHSR_P21 (0x1u << 21) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02467 #define PIO_FRLHSR_P22 (0x1u << 22) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02468 #define PIO_FRLHSR_P23 (0x1u << 23) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02469 #define PIO_FRLHSR_P24 (0x1u << 24) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02470 #define PIO_FRLHSR_P25 (0x1u << 25) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02471 #define PIO_FRLHSR_P26 (0x1u << 26) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02472 #define PIO_FRLHSR_P27 (0x1u << 27) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02473 #define PIO_FRLHSR_P28 (0x1u << 28) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02474 #define PIO_FRLHSR_P29 (0x1u << 29) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02475 #define PIO_FRLHSR_P30 (0x1u << 30) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02476 #define PIO_FRLHSR_P31 (0x1u << 31) /* (PIO_FRLHSR) Edge /Level Interrupt Source Selection. */ 02477 /* -------- PIO_LOCKSR : (PIO Offset: 0x00E0) Lock Status -------- */ 02478 #define PIO_LOCKSR_P0 (0x1u << 0) /* (PIO_LOCKSR) Lock Status. */ 02479 #define PIO_LOCKSR_P1 (0x1u << 1) /* (PIO_LOCKSR) Lock Status. */ 02480 #define PIO_LOCKSR_P2 (0x1u << 2) /* (PIO_LOCKSR) Lock Status. */ 02481 #define PIO_LOCKSR_P3 (0x1u << 3) /* (PIO_LOCKSR) Lock Status. */ 02482 #define PIO_LOCKSR_P4 (0x1u << 4) /* (PIO_LOCKSR) Lock Status. */ 02483 #define PIO_LOCKSR_P5 (0x1u << 5) /* (PIO_LOCKSR) Lock Status. */ 02484 #define PIO_LOCKSR_P6 (0x1u << 6) /* (PIO_LOCKSR) Lock Status. */ 02485 #define PIO_LOCKSR_P7 (0x1u << 7) /* (PIO_LOCKSR) Lock Status. */ 02486 #define PIO_LOCKSR_P8 (0x1u << 8) /* (PIO_LOCKSR) Lock Status. */ 02487 #define PIO_LOCKSR_P9 (0x1u << 9) /* (PIO_LOCKSR) Lock Status. */ 02488 #define PIO_LOCKSR_P10 (0x1u << 10) /* (PIO_LOCKSR) Lock Status. */ 02489 #define PIO_LOCKSR_P11 (0x1u << 11) /* (PIO_LOCKSR) Lock Status. */ 02490 #define PIO_LOCKSR_P12 (0x1u << 12) /* (PIO_LOCKSR) Lock Status. */ 02491 #define PIO_LOCKSR_P13 (0x1u << 13) /* (PIO_LOCKSR) Lock Status. */ 02492 #define PIO_LOCKSR_P14 (0x1u << 14) /* (PIO_LOCKSR) Lock Status. */ 02493 #define PIO_LOCKSR_P15 (0x1u << 15) /* (PIO_LOCKSR) Lock Status. */ 02494 #define PIO_LOCKSR_P16 (0x1u << 16) /* (PIO_LOCKSR) Lock Status. */ 02495 #define PIO_LOCKSR_P17 (0x1u << 17) /* (PIO_LOCKSR) Lock Status. */ 02496 #define PIO_LOCKSR_P18 (0x1u << 18) /* (PIO_LOCKSR) Lock Status. */ 02497 #define PIO_LOCKSR_P19 (0x1u << 19) /* (PIO_LOCKSR) Lock Status. */ 02498 #define PIO_LOCKSR_P20 (0x1u << 20) /* (PIO_LOCKSR) Lock Status. */ 02499 #define PIO_LOCKSR_P21 (0x1u << 21) /* (PIO_LOCKSR) Lock Status. */ 02500 #define PIO_LOCKSR_P22 (0x1u << 22) /* (PIO_LOCKSR) Lock Status. */ 02501 #define PIO_LOCKSR_P23 (0x1u << 23) /* (PIO_LOCKSR) Lock Status. */ 02502 #define PIO_LOCKSR_P24 (0x1u << 24) /* (PIO_LOCKSR) Lock Status. */ 02503 #define PIO_LOCKSR_P25 (0x1u << 25) /* (PIO_LOCKSR) Lock Status. */ 02504 #define PIO_LOCKSR_P26 (0x1u << 26) /* (PIO_LOCKSR) Lock Status. */ 02505 #define PIO_LOCKSR_P27 (0x1u << 27) /* (PIO_LOCKSR) Lock Status. */ 02506 #define PIO_LOCKSR_P28 (0x1u << 28) /* (PIO_LOCKSR) Lock Status. */ 02507 #define PIO_LOCKSR_P29 (0x1u << 29) /* (PIO_LOCKSR) Lock Status. */ 02508 #define PIO_LOCKSR_P30 (0x1u << 30) /* (PIO_LOCKSR) Lock Status. */ 02509 #define PIO_LOCKSR_P31 (0x1u << 31) /* (PIO_LOCKSR) Lock Status. */ 02510 /* -------- PIO_WPMR : (PIO Offset: 0x00E4) Write Protect Mode Register -------- */ 02511 #define PIO_WPMR_WPEN (0x1u << 0) /* (PIO_WPMR) Write Protect Enable */ 02512 #define PIO_WPMR_WPKEY_Pos 8 02513 #define PIO_WPMR_WPKEY_Msk (0xffffffu << PIO_WPMR_WPKEY_Pos) /* (PIO_WPMR) Write Protect KEY */ 02514 #define PIO_WPMR_WPKEY(value) ((PIO_WPMR_WPKEY_Msk & ((value) << PIO_WPMR_WPKEY_Pos))) 02515 /* -------- PIO_WPSR : (PIO Offset: 0x00E8) Write Protect Status Register -------- */ 02516 #define PIO_WPSR_WPVS (0x1u << 0) /* (PIO_WPSR) Write Protect Violation Status */ 02517 #define PIO_WPSR_WPVSRC_Pos 8 02518 #define PIO_WPSR_WPVSRC_Msk (0xffffu << PIO_WPSR_WPVSRC_Pos) /* (PIO_WPSR) Write Protect Violation Source */ 02519 /* -------- PIO_SCHMITT : (PIO Offset: 0x0100) Schmitt Trigger Register -------- */ 02520 #define PIO_SCHMITT_SCHMITT0 (0x1u << 0) /* (PIO_SCHMITT) */ 02521 #define PIO_SCHMITT_SCHMITT1 (0x1u << 1) /* (PIO_SCHMITT) */ 02522 #define PIO_SCHMITT_SCHMITT2 (0x1u << 2) /* (PIO_SCHMITT) */ 02523 #define PIO_SCHMITT_SCHMITT3 (0x1u << 3) /* (PIO_SCHMITT) */ 02524 #define PIO_SCHMITT_SCHMITT4 (0x1u << 4) /* (PIO_SCHMITT) */ 02525 #define PIO_SCHMITT_SCHMITT5 (0x1u << 5) /* (PIO_SCHMITT) */ 02526 #define PIO_SCHMITT_SCHMITT6 (0x1u << 6) /* (PIO_SCHMITT) */ 02527 #define PIO_SCHMITT_SCHMITT7 (0x1u << 7) /* (PIO_SCHMITT) */ 02528 #define PIO_SCHMITT_SCHMITT8 (0x1u << 8) /* (PIO_SCHMITT) */ 02529 #define PIO_SCHMITT_SCHMITT9 (0x1u << 9) /* (PIO_SCHMITT) */ 02530 #define PIO_SCHMITT_SCHMITT10 (0x1u << 10) /* (PIO_SCHMITT) */ 02531 #define PIO_SCHMITT_SCHMITT11 (0x1u << 11) /* (PIO_SCHMITT) */ 02532 #define PIO_SCHMITT_SCHMITT12 (0x1u << 12) /* (PIO_SCHMITT) */ 02533 #define PIO_SCHMITT_SCHMITT13 (0x1u << 13) /* (PIO_SCHMITT) */ 02534 #define PIO_SCHMITT_SCHMITT14 (0x1u << 14) /* (PIO_SCHMITT) */ 02535 #define PIO_SCHMITT_SCHMITT15 (0x1u << 15) /* (PIO_SCHMITT) */ 02536 #define PIO_SCHMITT_SCHMITT16 (0x1u << 16) /* (PIO_SCHMITT) */ 02537 #define PIO_SCHMITT_SCHMITT17 (0x1u << 17) /* (PIO_SCHMITT) */ 02538 #define PIO_SCHMITT_SCHMITT18 (0x1u << 18) /* (PIO_SCHMITT) */ 02539 #define PIO_SCHMITT_SCHMITT19 (0x1u << 19) /* (PIO_SCHMITT) */ 02540 #define PIO_SCHMITT_SCHMITT20 (0x1u << 20) /* (PIO_SCHMITT) */ 02541 #define PIO_SCHMITT_SCHMITT21 (0x1u << 21) /* (PIO_SCHMITT) */ 02542 #define PIO_SCHMITT_SCHMITT22 (0x1u << 22) /* (PIO_SCHMITT) */ 02543 #define PIO_SCHMITT_SCHMITT23 (0x1u << 23) /* (PIO_SCHMITT) */ 02544 #define PIO_SCHMITT_SCHMITT24 (0x1u << 24) /* (PIO_SCHMITT) */ 02545 #define PIO_SCHMITT_SCHMITT25 (0x1u << 25) /* (PIO_SCHMITT) */ 02546 #define PIO_SCHMITT_SCHMITT26 (0x1u << 26) /* (PIO_SCHMITT) */ 02547 #define PIO_SCHMITT_SCHMITT27 (0x1u << 27) /* (PIO_SCHMITT) */ 02548 #define PIO_SCHMITT_SCHMITT28 (0x1u << 28) /* (PIO_SCHMITT) */ 02549 #define PIO_SCHMITT_SCHMITT29 (0x1u << 29) /* (PIO_SCHMITT) */ 02550 #define PIO_SCHMITT_SCHMITT30 (0x1u << 30) /* (PIO_SCHMITT) */ 02551 #define PIO_SCHMITT_SCHMITT31 (0x1u << 31) /* (PIO_SCHMITT) */ 02552 02553 02554 02555 /* ============================================================================= */ 02556 /* SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller */ 02557 /* ============================================================================= */ 02558 02559 #ifndef __ASSEMBLY__ 02560 /* PwmCh_num hardware registers */ 02561 typedef struct { 02562 RwReg PWM_CMR; /* (PwmCh_num Offset: 0x0) PWM Channel Mode Register */ 02563 RwReg PWM_CDTY; /* (PwmCh_num Offset: 0x4) PWM Channel Duty Cycle Register */ 02564 RwReg PWM_CPRD; /* (PwmCh_num Offset: 0x8) PWM Channel Period Register */ 02565 RwReg PWM_CCNT; /* (PwmCh_num Offset: 0xC) PWM Channel Counter Register */ 02566 RwReg PWM_CUPD; /* (PwmCh_num Offset: 0x10) PWM Channel Update Register */ 02567 RwReg Reserved1[3]; 02568 } PwmCh_num; 02569 /* Pwm hardware registers */ 02570 typedef struct { 02571 RwReg PWM_MR; /* (Pwm Offset: 0x00) PWM Mode Register */ 02572 WoReg PWM_ENA; /* (Pwm Offset: 0x04) PWM Enable Register */ 02573 WoReg PWM_DIS; /* (Pwm Offset: 0x08) PWM Disable Register */ 02574 RoReg PWM_SR; /* (Pwm Offset: 0x0C) PWM Status Register */ 02575 WoReg PWM_IER; /* (Pwm Offset: 0x10) PWM Interrupt Enable Register */ 02576 WoReg PWM_IDR; /* (Pwm Offset: 0x14) PWM Interrupt Disable Register */ 02577 RoReg PWM_IMR; /* (Pwm Offset: 0x18) PWM Interrupt Mask Register */ 02578 RoReg PWM_ISR; /* (Pwm Offset: 0x1C) PWM Interrupt Status Register */ 02579 RwReg Reserved1[120]; 02580 PwmCh_num PWM_CH_NUM[4]; /* (Pwm Offset: 0x200) ch_num = 0 .. 3 */ 02581 } Pwm; 02582 #endif /* __ASSEMBLY__ */ 02583 /* -------- PWM_MR : (PWM Offset: 0x00) PWM Mode Register -------- */ 02584 #define PWM_MR_DIVA_Pos 0 02585 #define PWM_MR_DIVA_Msk (0xffu << PWM_MR_DIVA_Pos) /* (PWM_MR) CLKA, CLKB Divide Factor */ 02586 #define PWM_MR_DIVA_CLK_OFF (0x0u << 0) /* (PWM_MR) CLKA, CLKB clock is turned off */ 02587 #define PWM_MR_DIVA_CLK_DIV1 (0x1u << 0) /* (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */ 02588 #define PWM_MR_PREA_Pos 8 02589 #define PWM_MR_PREA_Msk (0xfu << PWM_MR_PREA_Pos) /* (PWM_MR) */ 02590 #define PWM_MR_PREA_MCK (0x0u << 8) /* (PWM_MR) Master Clock */ 02591 #define PWM_MR_PREA_MCKDIV2 (0x1u << 8) /* (PWM_MR) Master Clock divided by 2 */ 02592 #define PWM_MR_PREA_MCKDIV4 (0x2u << 8) /* (PWM_MR) Master Clock divided by 4 */ 02593 #define PWM_MR_PREA_MCKDIV8 (0x3u << 8) /* (PWM_MR) Master Clock divided by 8 */ 02594 #define PWM_MR_PREA_MCKDIV16 (0x4u << 8) /* (PWM_MR) Master Clock divided by 16 */ 02595 #define PWM_MR_PREA_MCKDIV32 (0x5u << 8) /* (PWM_MR) Master Clock divided by 32 */ 02596 #define PWM_MR_PREA_MCKDIV64 (0x6u << 8) /* (PWM_MR) Master Clock divided by 64 */ 02597 #define PWM_MR_PREA_MCKDIV128 (0x7u << 8) /* (PWM_MR) Master Clock divided by 128 */ 02598 #define PWM_MR_PREA_MCKDIV256 (0x8u << 8) /* (PWM_MR) Master Clock divided by 256 */ 02599 #define PWM_MR_PREA_MCKDIV512 (0x9u << 8) /* (PWM_MR) Master Clock divided by 512 */ 02600 #define PWM_MR_PREA_MCKDIV1024 (0xAu << 8) /* (PWM_MR) Master Clock divided by 1024 */ 02601 #define PWM_MR_DIVB_Pos 16 02602 #define PWM_MR_DIVB_Msk (0xffu << PWM_MR_DIVB_Pos) /* (PWM_MR) CLKA, CLKB Divide Factor */ 02603 #define PWM_MR_DIVB_CLK_OFF (0x0u << 16) /* (PWM_MR) CLKA, CLKB clock is turned off */ 02604 #define PWM_MR_DIVB_CLK_DIV1 (0x1u << 16) /* (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB */ 02605 #define PWM_MR_PREB_Pos 24 02606 #define PWM_MR_PREB_Msk (0xfu << PWM_MR_PREB_Pos) /* (PWM_MR) */ 02607 #define PWM_MR_PREB_MCK (0x0u << 24) /* (PWM_MR) Master Clock */ 02608 #define PWM_MR_PREB_MCKDIV2 (0x1u << 24) /* (PWM_MR) Master Clock divided by 2 */ 02609 #define PWM_MR_PREB_MCKDIV4 (0x2u << 24) /* (PWM_MR) Master Clock divided by 4 */ 02610 #define PWM_MR_PREB_MCKDIV8 (0x3u << 24) /* (PWM_MR) Master Clock divided by 8 */ 02611 #define PWM_MR_PREB_MCKDIV16 (0x4u << 24) /* (PWM_MR) Master Clock divided by 16 */ 02612 #define PWM_MR_PREB_MCKDIV32 (0x5u << 24) /* (PWM_MR) Master Clock divided by 32 */ 02613 #define PWM_MR_PREB_MCKDIV64 (0x6u << 24) /* (PWM_MR) Master Clock divided by 64 */ 02614 #define PWM_MR_PREB_MCKDIV128 (0x7u << 24) /* (PWM_MR) Master Clock divided by 128 */ 02615 #define PWM_MR_PREB_MCKDIV256 (0x8u << 24) /* (PWM_MR) Master Clock divided by 256 */ 02616 #define PWM_MR_PREB_MCKDIV512 (0x9u << 24) /* (PWM_MR) Master Clock divided by 512 */ 02617 #define PWM_MR_PREB_MCKDIV1024 (0xAu << 24) /* (PWM_MR) Master Clock divided by 1024 */ 02618 /* -------- PWM_ENA : (PWM Offset: 0x04) PWM Enable Register -------- */ 02619 #define PWM_ENA_CHID0 (0x1u << 0) /* (PWM_ENA) Channel ID */ 02620 #define PWM_ENA_CHID1 (0x1u << 1) /* (PWM_ENA) Channel ID */ 02621 #define PWM_ENA_CHID2 (0x1u << 2) /* (PWM_ENA) Channel ID */ 02622 #define PWM_ENA_CHID3 (0x1u << 3) /* (PWM_ENA) Channel ID */ 02623 /* -------- PWM_DIS : (PWM Offset: 0x08) PWM Disable Register -------- */ 02624 #define PWM_DIS_CHID0 (0x1u << 0) /* (PWM_DIS) Channel ID */ 02625 #define PWM_DIS_CHID1 (0x1u << 1) /* (PWM_DIS) Channel ID */ 02626 #define PWM_DIS_CHID2 (0x1u << 2) /* (PWM_DIS) Channel ID */ 02627 #define PWM_DIS_CHID3 (0x1u << 3) /* (PWM_DIS) Channel ID */ 02628 /* -------- PWM_SR : (PWM Offset: 0x0C) PWM Status Register -------- */ 02629 #define PWM_SR_CHID0 (0x1u << 0) /* (PWM_SR) Channel ID */ 02630 #define PWM_SR_CHID1 (0x1u << 1) /* (PWM_SR) Channel ID */ 02631 #define PWM_SR_CHID2 (0x1u << 2) /* (PWM_SR) Channel ID */ 02632 #define PWM_SR_CHID3 (0x1u << 3) /* (PWM_SR) Channel ID */ 02633 /* -------- PWM_IER : (PWM Offset: 0x10) PWM Interrupt Enable Register -------- */ 02634 #define PWM_IER_CHID0 (0x1u << 0) /* (PWM_IER) Channel ID. */ 02635 #define PWM_IER_CHID1 (0x1u << 1) /* (PWM_IER) Channel ID. */ 02636 #define PWM_IER_CHID2 (0x1u << 2) /* (PWM_IER) Channel ID. */ 02637 #define PWM_IER_CHID3 (0x1u << 3) /* (PWM_IER) Channel ID. */ 02638 /* -------- PWM_IDR : (PWM Offset: 0x14) PWM Interrupt Disable Register -------- */ 02639 #define PWM_IDR_CHID0 (0x1u << 0) /* (PWM_IDR) Channel ID. */ 02640 #define PWM_IDR_CHID1 (0x1u << 1) /* (PWM_IDR) Channel ID. */ 02641 #define PWM_IDR_CHID2 (0x1u << 2) /* (PWM_IDR) Channel ID. */ 02642 #define PWM_IDR_CHID3 (0x1u << 3) /* (PWM_IDR) Channel ID. */ 02643 /* -------- PWM_IMR : (PWM Offset: 0x18) PWM Interrupt Mask Register -------- */ 02644 #define PWM_IMR_CHID0 (0x1u << 0) /* (PWM_IMR) Channel ID. */ 02645 #define PWM_IMR_CHID1 (0x1u << 1) /* (PWM_IMR) Channel ID. */ 02646 #define PWM_IMR_CHID2 (0x1u << 2) /* (PWM_IMR) Channel ID. */ 02647 #define PWM_IMR_CHID3 (0x1u << 3) /* (PWM_IMR) Channel ID. */ 02648 /* -------- PWM_ISR : (PWM Offset: 0x1C) PWM Interrupt Status Register -------- */ 02649 #define PWM_ISR_CHID0 (0x1u << 0) /* (PWM_ISR) Channel ID */ 02650 #define PWM_ISR_CHID1 (0x1u << 1) /* (PWM_ISR) Channel ID */ 02651 #define PWM_ISR_CHID2 (0x1u << 2) /* (PWM_ISR) Channel ID */ 02652 #define PWM_ISR_CHID3 (0x1u << 3) /* (PWM_ISR) Channel ID */ 02653 /* -------- PWM_CMR : (PWM Offset: N/A) PWM Channel Mode Register -------- */ 02654 #define PWM_CMR_CPRE_Pos 0 02655 #define PWM_CMR_CPRE_Msk (0xfu << PWM_CMR_CPRE_Pos) /* (PWM_CMR) Channel Pre-scaler */ 02656 #define PWM_CMR_CPRE_MCK (0x0u << 0) /* (PWM_CMR) Master Clock */ 02657 #define PWM_CMR_CPRE_MCKDIV2 (0x1u << 0) /* (PWM_CMR) Master Clock divided by 2 */ 02658 #define PWM_CMR_CPRE_MCKDIV4 (0x2u << 0) /* (PWM_CMR) Master Clock divided by 4 */ 02659 #define PWM_CMR_CPRE_MCKDIV8 (0x3u << 0) /* (PWM_CMR) Master Clock divided by 8 */ 02660 #define PWM_CMR_CPRE_MCKDIV16 (0x4u << 0) /* (PWM_CMR) Master Clock divided by 16 */ 02661 #define PWM_CMR_CPRE_MCKDIV32 (0x5u << 0) /* (PWM_CMR) Master Clock divided by 32 */ 02662 #define PWM_CMR_CPRE_MCKDIV64 (0x6u << 0) /* (PWM_CMR) Master Clock divided by 64 */ 02663 #define PWM_CMR_CPRE_MCKDIV128 (0x7u << 0) /* (PWM_CMR) Master Clock divided by 128 */ 02664 #define PWM_CMR_CPRE_MCKDIV256 (0x8u << 0) /* (PWM_CMR) Master Clock divided by 256 */ 02665 #define PWM_CMR_CPRE_MCKDIV512 (0x9u << 0) /* (PWM_CMR) Master Clock divided by 512 */ 02666 #define PWM_CMR_CPRE_MCKDIV1024 (0xAu << 0) /* (PWM_CMR) Master Clock divided by 1024 */ 02667 #define PWM_CMR_CPRE_CLKA (0xBu << 0) /* (PWM_CMR) Clock A */ 02668 #define PWM_CMR_CPRE_CLKB (0xCu << 0) /* (PWM_CMR) Clock B */ 02669 #define PWM_CMR_CALG (0x1u << 8) /* (PWM_CMR) Channel Alignment */ 02670 #define PWM_CMR_CPOL (0x1u << 9) /* (PWM_CMR) Channel Polarity */ 02671 #define PWM_CMR_CPD (0x1u << 10) /* (PWM_CMR) Channel Update Period */ 02672 /* -------- PWM_CDTY : (PWM Offset: N/A) PWM Channel Duty Cycle Register -------- */ 02673 #define PWM_CDTY_CDTY_Pos 0 02674 #define PWM_CDTY_CDTY_Msk (0xffffffffu << PWM_CDTY_CDTY_Pos) /* (PWM_CDTY) Channel Duty Cycle */ 02675 #define PWM_CDTY_CDTY(value) ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos))) 02676 /* -------- PWM_CPRD : (PWM Offset: N/A) PWM Channel Period Register -------- */ 02677 #define PWM_CPRD_CPRD_Pos 0 02678 #define PWM_CPRD_CPRD_Msk (0xffffffffu << PWM_CPRD_CPRD_Pos) /* (PWM_CPRD) Channel Period */ 02679 #define PWM_CPRD_CPRD(value) ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos))) 02680 /* -------- PWM_CCNT : (PWM Offset: N/A) PWM Channel Counter Register -------- */ 02681 #define PWM_CCNT_CNT_Pos 0 02682 #define PWM_CCNT_CNT_Msk (0xffffffffu << PWM_CCNT_CNT_Pos) /* (PWM_CCNT) Channel Counter Register */ 02683 /* -------- PWM_CUPD : (PWM Offset: N/A) PWM Channel Update Register -------- */ 02684 #define PWM_CUPD_CUPD_Pos 0 02685 #define PWM_CUPD_CUPD_Msk (0xffffffffu << PWM_CUPD_CUPD_Pos) /* (PWM_CUPD) */ 02686 #define PWM_CUPD_CUPD(value) ((PWM_CUPD_CUPD_Msk & ((value) << PWM_CUPD_CUPD_Pos))) 02687 02688 02689 /* ============================================================================= */ 02690 /* SOFTWARE API DEFINITION FOR Reset Controller */ 02691 /* ============================================================================= */ 02692 02693 #ifndef __ASSEMBLY__ 02694 /* Rstc hardware registers */ 02695 typedef struct { 02696 WoReg RSTC_CR; /* (Rstc Offset: 0x00) Control Register */ 02697 RoReg RSTC_SR; /* (Rstc Offset: 0x04) Status Register */ 02698 RwReg RSTC_MR; /* (Rstc Offset: 0x08) Mode Register */ 02699 } Rstc; 02700 #endif /* __ASSEMBLY__ */ 02701 /* -------- RSTC_CR : (RSTC Offset: 0x00) Control Register -------- */ 02702 #define RSTC_CR_PROCRST (0x1u << 0) /* (RSTC_CR) Processor Reset */ 02703 #define RSTC_CR_PERRST (0x1u << 2) /* (RSTC_CR) Peripheral Reset */ 02704 #define RSTC_CR_EXTRST (0x1u << 3) /* (RSTC_CR) External Reset */ 02705 #define RSTC_CR_KEY_Pos 24 02706 #define RSTC_CR_KEY_Msk (0xffu << RSTC_CR_KEY_Pos) /* (RSTC_CR) Password */ 02707 #define RSTC_CR_KEY(value) ((RSTC_CR_KEY_Msk & ((value) << RSTC_CR_KEY_Pos))) 02708 /* -------- RSTC_SR : (RSTC Offset: 0x04) Status Register -------- */ 02709 #define RSTC_SR_URSTS (0x1u << 0) /* (RSTC_SR) User Reset Status */ 02710 #define RSTC_SR_RSTTYP_Pos 8 02711 #define RSTC_SR_RSTTYP_Msk (0x7u << RSTC_SR_RSTTYP_Pos) /* (RSTC_SR) Reset Type */ 02712 #define RSTC_SR_NRSTL (0x1u << 16) /* (RSTC_SR) NRST Pin Level */ 02713 #define RSTC_SR_SRCMP (0x1u << 17) /* (RSTC_SR) Software Reset Command in Progress */ 02714 /* -------- RSTC_MR : (RSTC Offset: 0x08) Mode Register -------- */ 02715 #define RSTC_MR_URSTEN (0x1u << 0) /* (RSTC_MR) User Reset Enable */ 02716 #define RSTC_MR_URSTIEN (0x1u << 4) /* (RSTC_MR) User Reset Interrupt Enable */ 02717 #define RSTC_MR_ERSTL_Pos 8 02718 #define RSTC_MR_ERSTL_Msk (0xfu << RSTC_MR_ERSTL_Pos) /* (RSTC_MR) External Reset Length */ 02719 #define RSTC_MR_ERSTL(value) ((RSTC_MR_ERSTL_Msk & ((value) << RSTC_MR_ERSTL_Pos))) 02720 #define RSTC_MR_KEY_Pos 24 02721 #define RSTC_MR_KEY_Msk (0xffu << RSTC_MR_KEY_Pos) /* (RSTC_MR) Password */ 02722 #define RSTC_MR_KEY(value) ((RSTC_MR_KEY_Msk & ((value) << RSTC_MR_KEY_Pos))) 02723 02724 02725 /* ============================================================================= */ 02726 /* SOFTWARE API DEFINITION FOR Real-time Clock */ 02727 /* ============================================================================= */ 02728 02729 #ifndef __ASSEMBLY__ 02730 /* Rtc hardware registers */ 02731 typedef struct { 02732 RwReg RTC_CR; /* (Rtc Offset: 0x00) Control Register */ 02733 RwReg RTC_MR; /* (Rtc Offset: 0x04) Mode Register */ 02734 RwReg RTC_TIMR; /* (Rtc Offset: 0x08) Time Register */ 02735 RwReg RTC_CALR; /* (Rtc Offset: 0x0C) Calendar Register */ 02736 RwReg RTC_TIMALR; /* (Rtc Offset: 0x10) Time Alarm Register */ 02737 RwReg RTC_CALALR; /* (Rtc Offset: 0x14) Calendar Alarm Register */ 02738 RoReg RTC_SR; /* (Rtc Offset: 0x18) Status Register */ 02739 WoReg RTC_SCCR; /* (Rtc Offset: 0x1C) Status Clear Command Register */ 02740 WoReg RTC_IER; /* (Rtc Offset: 0x20) Interrupt Enable Register */ 02741 WoReg RTC_IDR; /* (Rtc Offset: 0x24) Interrupt Disable Register */ 02742 RoReg RTC_IMR; /* (Rtc Offset: 0x28) Interrupt Mask Register */ 02743 RoReg RTC_VER; /* (Rtc Offset: 0x2C) Valid Entry Register */ 02744 RwReg Reserved1[45]; 02745 RwReg RTC_WPMR; /* (Rtc Offset: 0xE4) Write Protect Mode Register */ 02746 } Rtc; 02747 #endif /* __ASSEMBLY__ */ 02748 /* -------- RTC_CR : (RTC Offset: 0x00) Control Register -------- */ 02749 #define RTC_CR_UPDTIM (0x1u << 0) /* (RTC_CR) Update Request Time Register */ 02750 #define RTC_CR_UPDCAL (0x1u << 1) /* (RTC_CR) Update Request Calendar Register */ 02751 #define RTC_CR_TIMEVSEL_Pos 8 02752 #define RTC_CR_TIMEVSEL_Msk (0x3u << RTC_CR_TIMEVSEL_Pos) /* (RTC_CR) Time Event Selection */ 02753 #define RTC_CR_TIMEVSEL_MINUTE (0x0u << 8) /* (RTC_CR) Minute change */ 02754 #define RTC_CR_TIMEVSEL_HOUR (0x1u << 8) /* (RTC_CR) Hour change */ 02755 #define RTC_CR_TIMEVSEL_MIDNIGHT (0x2u << 8) /* (RTC_CR) Every day at midnight */ 02756 #define RTC_CR_TIMEVSEL_NOON (0x3u << 8) /* (RTC_CR) Every day at noon */ 02757 #define RTC_CR_CALEVSEL_Pos 16 02758 #define RTC_CR_CALEVSEL_Msk (0x3u << RTC_CR_CALEVSEL_Pos) /* (RTC_CR) Calendar Event Selection */ 02759 #define RTC_CR_CALEVSEL_WEEK (0x0u << 16) /* (RTC_CR) Week change (every Monday at time 00:00:00) */ 02760 #define RTC_CR_CALEVSEL_MONTH (0x1u << 16) /* (RTC_CR) Month change (every 01 of each month at time 00:00:00) */ 02761 #define RTC_CR_CALEVSEL_YEAR (0x2u << 16) /* (RTC_CR) Year change (every January 1 at time 00:00:00) */ 02762 /* -------- RTC_MR : (RTC Offset: 0x04) Mode Register -------- */ 02763 #define RTC_MR_HRMOD (0x1u << 0) /* (RTC_MR) 12-/24-hour Mode */ 02764 /* -------- RTC_TIMR : (RTC Offset: 0x08) Time Register -------- */ 02765 #define RTC_TIMR_SEC_Pos 0 02766 #define RTC_TIMR_SEC_Msk (0x7fu << RTC_TIMR_SEC_Pos) /* (RTC_TIMR) Current Second */ 02767 #define RTC_TIMR_SEC(value) ((RTC_TIMR_SEC_Msk & ((value) << RTC_TIMR_SEC_Pos))) 02768 #define RTC_TIMR_MIN_Pos 8 02769 #define RTC_TIMR_MIN_Msk (0x7fu << RTC_TIMR_MIN_Pos) /* (RTC_TIMR) Current Minute */ 02770 #define RTC_TIMR_MIN(value) ((RTC_TIMR_MIN_Msk & ((value) << RTC_TIMR_MIN_Pos))) 02771 #define RTC_TIMR_HOUR_Pos 16 02772 #define RTC_TIMR_HOUR_Msk (0x3fu << RTC_TIMR_HOUR_Pos) /* (RTC_TIMR) Current Hour */ 02773 #define RTC_TIMR_HOUR(value) ((RTC_TIMR_HOUR_Msk & ((value) << RTC_TIMR_HOUR_Pos))) 02774 #define RTC_TIMR_AMPM (0x1u << 22) /* (RTC_TIMR) Ante Meridiem Post Meridiem Indicator */ 02775 /* -------- RTC_CALR : (RTC Offset: 0x0C) Calendar Register -------- */ 02776 #define RTC_CALR_CENT_Pos 0 02777 #define RTC_CALR_CENT_Msk (0x7fu << RTC_CALR_CENT_Pos) /* (RTC_CALR) Current Century */ 02778 #define RTC_CALR_CENT(value) ((RTC_CALR_CENT_Msk & ((value) << RTC_CALR_CENT_Pos))) 02779 #define RTC_CALR_YEAR_Pos 8 02780 #define RTC_CALR_YEAR_Msk (0xffu << RTC_CALR_YEAR_Pos) /* (RTC_CALR) Current Year */ 02781 #define RTC_CALR_YEAR(value) ((RTC_CALR_YEAR_Msk & ((value) << RTC_CALR_YEAR_Pos))) 02782 #define RTC_CALR_MONTH_Pos 16 02783 #define RTC_CALR_MONTH_Msk (0x1fu << RTC_CALR_MONTH_Pos) /* (RTC_CALR) Current Month */ 02784 #define RTC_CALR_MONTH(value) ((RTC_CALR_MONTH_Msk & ((value) << RTC_CALR_MONTH_Pos))) 02785 #define RTC_CALR_DAY_Pos 21 02786 #define RTC_CALR_DAY_Msk (0x7u << RTC_CALR_DAY_Pos) /* (RTC_CALR) Current Day in Current Week */ 02787 #define RTC_CALR_DAY(value) ((RTC_CALR_DAY_Msk & ((value) << RTC_CALR_DAY_Pos))) 02788 #define RTC_CALR_DATE_Pos 24 02789 #define RTC_CALR_DATE_Msk (0x3fu << RTC_CALR_DATE_Pos) /* (RTC_CALR) Current Day in Current Month */ 02790 #define RTC_CALR_DATE(value) ((RTC_CALR_DATE_Msk & ((value) << RTC_CALR_DATE_Pos))) 02791 /* -------- RTC_TIMALR : (RTC Offset: 0x10) Time Alarm Register -------- */ 02792 #define RTC_TIMALR_SEC_Pos 0 02793 #define RTC_TIMALR_SEC_Msk (0x7fu << RTC_TIMALR_SEC_Pos) /* (RTC_TIMALR) Second Alarm */ 02794 #define RTC_TIMALR_SEC(value) ((RTC_TIMALR_SEC_Msk & ((value) << RTC_TIMALR_SEC_Pos))) 02795 #define RTC_TIMALR_SECEN (0x1u << 7) /* (RTC_TIMALR) Second Alarm Enable */ 02796 #define RTC_TIMALR_MIN_Pos 8 02797 #define RTC_TIMALR_MIN_Msk (0x7fu << RTC_TIMALR_MIN_Pos) /* (RTC_TIMALR) Minute Alarm */ 02798 #define RTC_TIMALR_MIN(value) ((RTC_TIMALR_MIN_Msk & ((value) << RTC_TIMALR_MIN_Pos))) 02799 #define RTC_TIMALR_MINEN (0x1u << 15) /* (RTC_TIMALR) Minute Alarm Enable */ 02800 #define RTC_TIMALR_HOUR_Pos 16 02801 #define RTC_TIMALR_HOUR_Msk (0x3fu << RTC_TIMALR_HOUR_Pos) /* (RTC_TIMALR) Hour Alarm */ 02802 #define RTC_TIMALR_HOUR(value) ((RTC_TIMALR_HOUR_Msk & ((value) << RTC_TIMALR_HOUR_Pos))) 02803 #define RTC_TIMALR_AMPM (0x1u << 22) /* (RTC_TIMALR) AM/PM Indicator */ 02804 #define RTC_TIMALR_HOUREN (0x1u << 23) /* (RTC_TIMALR) Hour Alarm Enable */ 02805 /* -------- RTC_CALALR : (RTC Offset: 0x14) Calendar Alarm Register -------- */ 02806 #define RTC_CALALR_MONTH_Pos 16 02807 #define RTC_CALALR_MONTH_Msk (0x1fu << RTC_CALALR_MONTH_Pos) /* (RTC_CALALR) Month Alarm */ 02808 #define RTC_CALALR_MONTH(value) ((RTC_CALALR_MONTH_Msk & ((value) << RTC_CALALR_MONTH_Pos))) 02809 #define RTC_CALALR_MTHEN (0x1u << 23) /* (RTC_CALALR) Month Alarm Enable */ 02810 #define RTC_CALALR_DATE_Pos 24 02811 #define RTC_CALALR_DATE_Msk (0x3fu << RTC_CALALR_DATE_Pos) /* (RTC_CALALR) Date Alarm */ 02812 #define RTC_CALALR_DATE(value) ((RTC_CALALR_DATE_Msk & ((value) << RTC_CALALR_DATE_Pos))) 02813 #define RTC_CALALR_DATEEN (0x1u << 31) /* (RTC_CALALR) Date Alarm Enable */ 02814 /* -------- RTC_SR : (RTC Offset: 0x18) Status Register -------- */ 02815 #define RTC_SR_ACKUPD (0x1u << 0) /* (RTC_SR) Acknowledge for Update */ 02816 #define RTC_SR_ALARM (0x1u << 1) /* (RTC_SR) Alarm Flag */ 02817 #define RTC_SR_SEC (0x1u << 2) /* (RTC_SR) Second Event */ 02818 #define RTC_SR_TIMEV (0x1u << 3) /* (RTC_SR) Time Event */ 02819 #define RTC_SR_CALEV (0x1u << 4) /* (RTC_SR) Calendar Event */ 02820 /* -------- RTC_SCCR : (RTC Offset: 0x1C) Status Clear Command Register -------- */ 02821 #define RTC_SCCR_ACKCLR (0x1u << 0) /* (RTC_SCCR) Acknowledge Clear */ 02822 #define RTC_SCCR_ALRCLR (0x1u << 1) /* (RTC_SCCR) Alarm Clear */ 02823 #define RTC_SCCR_SECCLR (0x1u << 2) /* (RTC_SCCR) Second Clear */ 02824 #define RTC_SCCR_TIMCLR (0x1u << 3) /* (RTC_SCCR) Time Clear */ 02825 #define RTC_SCCR_CALCLR (0x1u << 4) /* (RTC_SCCR) Calendar Clear */ 02826 /* -------- RTC_IER : (RTC Offset: 0x20) Interrupt Enable Register -------- */ 02827 #define RTC_IER_ACKEN (0x1u << 0) /* (RTC_IER) Acknowledge Update Interrupt Enable */ 02828 #define RTC_IER_ALREN (0x1u << 1) /* (RTC_IER) Alarm Interrupt Enable */ 02829 #define RTC_IER_SECEN (0x1u << 2) /* (RTC_IER) Second Event Interrupt Enable */ 02830 #define RTC_IER_TIMEN (0x1u << 3) /* (RTC_IER) Time Event Interrupt Enable */ 02831 #define RTC_IER_CALEN (0x1u << 4) /* (RTC_IER) Calendar Event Interrupt Enable */ 02832 /* -------- RTC_IDR : (RTC Offset: 0x24) Interrupt Disable Register -------- */ 02833 #define RTC_IDR_ACKDIS (0x1u << 0) /* (RTC_IDR) Acknowledge Update Interrupt Disable */ 02834 #define RTC_IDR_ALRDIS (0x1u << 1) /* (RTC_IDR) Alarm Interrupt Disable */ 02835 #define RTC_IDR_SECDIS (0x1u << 2) /* (RTC_IDR) Second Event Interrupt Disable */ 02836 #define RTC_IDR_TIMDIS (0x1u << 3) /* (RTC_IDR) Time Event Interrupt Disable */ 02837 #define RTC_IDR_CALDIS (0x1u << 4) /* (RTC_IDR) Calendar Event Interrupt Disable */ 02838 /* -------- RTC_IMR : (RTC Offset: 0x28) Interrupt Mask Register -------- */ 02839 #define RTC_IMR_ACK (0x1u << 0) /* (RTC_IMR) Acknowledge Update Interrupt Mask */ 02840 #define RTC_IMR_ALR (0x1u << 1) /* (RTC_IMR) Alarm Interrupt Mask */ 02841 #define RTC_IMR_SEC (0x1u << 2) /* (RTC_IMR) Second Event Interrupt Mask */ 02842 #define RTC_IMR_TIM (0x1u << 3) /* (RTC_IMR) Time Event Interrupt Mask */ 02843 #define RTC_IMR_CAL (0x1u << 4) /* (RTC_IMR) Calendar Event Interrupt Mask */ 02844 /* -------- RTC_VER : (RTC Offset: 0x2C) Valid Entry Register -------- */ 02845 #define RTC_VER_NVTIM (0x1u << 0) /* (RTC_VER) Non-valid Time */ 02846 #define RTC_VER_NVCAL (0x1u << 1) /* (RTC_VER) Non-valid Calendar */ 02847 #define RTC_VER_NVTIMALR (0x1u << 2) /* (RTC_VER) Non-valid Time Alarm */ 02848 #define RTC_VER_NVCALALR (0x1u << 3) /* (RTC_VER) Non-valid Calendar Alarm */ 02849 /* -------- RTC_WPMR : (RTC Offset: 0xE4) Write Protect Mode Register -------- */ 02850 #define RTC_WPMR_WPEN (0x1u << 0) /* (RTC_WPMR) Write Protect Enable */ 02851 #define RTC_WPMR_WPKEY_Pos 8 02852 #define RTC_WPMR_WPKEY_Msk (0xffffffu << RTC_WPMR_WPKEY_Pos) /* (RTC_WPMR) */ 02853 #define RTC_WPMR_WPKEY(value) ((RTC_WPMR_WPKEY_Msk & ((value) << RTC_WPMR_WPKEY_Pos))) 02854 02855 02856 /* ============================================================================= */ 02857 /* SOFTWARE API DEFINITION FOR Real-time Timer */ 02858 /* ============================================================================= */ 02859 02860 #ifndef __ASSEMBLY__ 02861 /* Rtt hardware registers */ 02862 typedef struct { 02863 RwReg RTT_MR; /* (Rtt Offset: 0x00) Mode Register */ 02864 RwReg RTT_AR; /* (Rtt Offset: 0x04) Alarm Register */ 02865 RoReg RTT_VR; /* (Rtt Offset: 0x08) Value Register */ 02866 RoReg RTT_SR; /* (Rtt Offset: 0x0C) Status Register */ 02867 } Rtt; 02868 #endif /* __ASSEMBLY__ */ 02869 /* -------- RTT_MR : (RTT Offset: 0x00) Mode Register -------- */ 02870 #define RTT_MR_RTPRES_Pos 0 02871 #define RTT_MR_RTPRES_Msk (0xffffu << RTT_MR_RTPRES_Pos) /* (RTT_MR) Real-time Timer Prescaler Value */ 02872 #define RTT_MR_RTPRES(value) ((RTT_MR_RTPRES_Msk & ((value) << RTT_MR_RTPRES_Pos))) 02873 #define RTT_MR_ALMIEN (0x1u << 16) /* (RTT_MR) Alarm Interrupt Enable */ 02874 #define RTT_MR_RTTINCIEN (0x1u << 17) /* (RTT_MR) Real-time Timer Increment Interrupt Enable */ 02875 #define RTT_MR_RTTRST (0x1u << 18) /* (RTT_MR) Real-time Timer Restart */ 02876 /* -------- RTT_AR : (RTT Offset: 0x04) Alarm Register -------- */ 02877 #define RTT_AR_ALMV_Pos 0 02878 #define RTT_AR_ALMV_Msk (0xffffffffu << RTT_AR_ALMV_Pos) /* (RTT_AR) Alarm Value */ 02879 #define RTT_AR_ALMV(value) ((RTT_AR_ALMV_Msk & ((value) << RTT_AR_ALMV_Pos))) 02880 /* -------- RTT_VR : (RTT Offset: 0x08) Value Register -------- */ 02881 #define RTT_VR_CRTV_Pos 0 02882 #define RTT_VR_CRTV_Msk (0xffffffffu << RTT_VR_CRTV_Pos) /* (RTT_VR) Current Real-time Value */ 02883 /* -------- RTT_SR : (RTT Offset: 0x0C) Status Register -------- */ 02884 #define RTT_SR_ALMS (0x1u << 0) /* (RTT_SR) Real-time Alarm Status */ 02885 #define RTT_SR_RTTINC (0x1u << 1) /* (RTT_SR) Real-time Timer Increment */ 02886 02887 02888 /* ============================================================================= */ 02889 /* SOFTWARE API DEFINITION FOR Serial Peripheral Interface */ 02890 /* ============================================================================= */ 02891 02892 #ifndef __ASSEMBLY__ 02893 /* Spi hardware registers */ 02894 typedef struct { 02895 WoReg SPI_CR; /* (Spi Offset: 0x00) Control Register */ 02896 RwReg SPI_MR; /* (Spi Offset: 0x04) Mode Register */ 02897 RoReg SPI_RDR; /* (Spi Offset: 0x08) Receive Data Register */ 02898 WoReg SPI_TDR; /* (Spi Offset: 0x0C) Transmit Data Register */ 02899 RoReg SPI_SR; /* (Spi Offset: 0x10) Status Register */ 02900 WoReg SPI_IER; /* (Spi Offset: 0x14) Interrupt Enable Register */ 02901 WoReg SPI_IDR; /* (Spi Offset: 0x18) Interrupt Disable Register */ 02902 RoReg SPI_IMR; /* (Spi Offset: 0x1C) Interrupt Mask Register */ 02903 RwReg Reserved1[4]; 02904 RwReg SPI_CSR[4]; /* (Spi Offset: 0x30) Chip Select Register */ 02905 RwReg Reserved2[41]; 02906 RwReg SPI_WPMR; /* (Spi Offset: 0xE4) Write Protection Control Register */ 02907 RoReg SPI_WPSR; /* (Spi Offset: 0xE8) Write Protection Status Register */ 02908 RwReg Reserved3[5]; 02909 RwReg SPI_RPR; /* (Spi Offset: 0x100) Receive Pointer Register */ 02910 RwReg SPI_RCR; /* (Spi Offset: 0x104) Receive Counter Register */ 02911 RwReg SPI_TPR; /* (Spi Offset: 0x108) Transmit Pointer Register */ 02912 RwReg SPI_TCR; /* (Spi Offset: 0x10C) Transmit Counter Register */ 02913 RwReg SPI_RNPR; /* (Spi Offset: 0x110) Receive Next Pointer Register */ 02914 RwReg SPI_RNCR; /* (Spi Offset: 0x114) Receive Next Counter Register */ 02915 RwReg SPI_TNPR; /* (Spi Offset: 0x118) Transmit Next Pointer Register */ 02916 RwReg SPI_TNCR; /* (Spi Offset: 0x11C) Transmit Next Counter Register */ 02917 WoReg SPI_PTCR; /* (Spi Offset: 0x120) Transfer Control Register */ 02918 RoReg SPI_PTSR; /* (Spi Offset: 0x124) Transfer Status Register */ 02919 } Spi; 02920 #endif /* __ASSEMBLY__ */ 02921 /* -------- SPI_CR : (SPI Offset: 0x00) Control Register -------- */ 02922 #define SPI_CR_SPIEN (0x1u << 0) /* (SPI_CR) SPI Enable */ 02923 #define SPI_CR_SPIDIS (0x1u << 1) /* (SPI_CR) SPI Disable */ 02924 #define SPI_CR_SWRST (0x1u << 7) /* (SPI_CR) SPI Software Reset */ 02925 #define SPI_CR_LASTXFER (0x1u << 24) /* (SPI_CR) Last Transfer */ 02926 /* -------- SPI_MR : (SPI Offset: 0x04) Mode Register -------- */ 02927 #define SPI_MR_MSTR (0x1u << 0) /* (SPI_MR) Master/Slave Mode */ 02928 #define SPI_MR_PS (0x1u << 1) /* (SPI_MR) Peripheral Select */ 02929 #define SPI_MR_PCSDEC (0x1u << 2) /* (SPI_MR) Chip Select Decode */ 02930 #define SPI_MR_MODFDIS (0x1u << 4) /* (SPI_MR) Mode Fault Detection */ 02931 #define SPI_MR_WDRBT (0x1u << 5) /* (SPI_MR) Wait Data Read Before Transfer */ 02932 #define SPI_MR_LLB (0x1u << 7) /* (SPI_MR) Local Loopback Enable */ 02933 #define SPI_MR_PCS_Pos 16 02934 #define SPI_MR_PCS_Msk (0xfu << SPI_MR_PCS_Pos) /* (SPI_MR) Peripheral Chip Select */ 02935 #define SPI_MR_PCS(value) ((SPI_MR_PCS_Msk & ((value) << SPI_MR_PCS_Pos))) 02936 #define SPI_MR_DLYBCS_Pos 24 02937 #define SPI_MR_DLYBCS_Msk (0xffu << SPI_MR_DLYBCS_Pos) /* (SPI_MR) Delay Between Chip Selects */ 02938 #define SPI_MR_DLYBCS(value) ((SPI_MR_DLYBCS_Msk & ((value) << SPI_MR_DLYBCS_Pos))) 02939 /* -------- SPI_RDR : (SPI Offset: 0x08) Receive Data Register -------- */ 02940 #define SPI_RDR_RD_Pos 0 02941 #define SPI_RDR_RD_Msk (0xffffu << SPI_RDR_RD_Pos) /* (SPI_RDR) Receive Data */ 02942 #define SPI_RDR_PCS_Pos 16 02943 #define SPI_RDR_PCS_Msk (0xfu << SPI_RDR_PCS_Pos) /* (SPI_RDR) Peripheral Chip Select */ 02944 /* -------- SPI_TDR : (SPI Offset: 0x0C) Transmit Data Register -------- */ 02945 #define SPI_TDR_TD_Pos 0 02946 #define SPI_TDR_TD_Msk (0xffffu << SPI_TDR_TD_Pos) /* (SPI_TDR) Transmit Data */ 02947 #define SPI_TDR_TD(value) ((SPI_TDR_TD_Msk & ((value) << SPI_TDR_TD_Pos))) 02948 #define SPI_TDR_PCS_Pos 16 02949 #define SPI_TDR_PCS_Msk (0xfu << SPI_TDR_PCS_Pos) /* (SPI_TDR) Peripheral Chip Select */ 02950 #define SPI_TDR_PCS(value) ((SPI_TDR_PCS_Msk & ((value) << SPI_TDR_PCS_Pos))) 02951 #define SPI_TDR_LASTXFER (0x1u << 24) /* (SPI_TDR) Last Transfer */ 02952 /* -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- */ 02953 #define SPI_SR_RDRF (0x1u << 0) /* (SPI_SR) Receive Data Register Full */ 02954 #define SPI_SR_TDRE (0x1u << 1) /* (SPI_SR) Transmit Data Register Empty */ 02955 #define SPI_SR_MODF (0x1u << 2) /* (SPI_SR) Mode Fault Error */ 02956 #define SPI_SR_OVRES (0x1u << 3) /* (SPI_SR) Overrun Error Status */ 02957 #define SPI_SR_ENDRX (0x1u << 4) /* (SPI_SR) End of RX buffer */ 02958 #define SPI_SR_ENDTX (0x1u << 5) /* (SPI_SR) End of TX buffer */ 02959 #define SPI_SR_RXBUFF (0x1u << 6) /* (SPI_SR) RX Buffer Full */ 02960 #define SPI_SR_TXBUFE (0x1u << 7) /* (SPI_SR) TX Buffer Empty */ 02961 #define SPI_SR_NSSR (0x1u << 8) /* (SPI_SR) NSS Rising */ 02962 #define SPI_SR_TXEMPTY (0x1u << 9) /* (SPI_SR) Transmission Registers Empty */ 02963 #define SPI_SR_UNDES (0x1u << 10) /* (SPI_SR) Underrun Error Status (Slave Mode Only) */ 02964 #define SPI_SR_SPIENS (0x1u << 16) /* (SPI_SR) SPI Enable Status */ 02965 /* -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- */ 02966 #define SPI_IER_RDRF (0x1u << 0) /* (SPI_IER) Receive Data Register Full Interrupt Enable */ 02967 #define SPI_IER_TDRE (0x1u << 1) /* (SPI_IER) SPI Transmit Data Register Empty Interrupt Enable */ 02968 #define SPI_IER_MODF (0x1u << 2) /* (SPI_IER) Mode Fault Error Interrupt Enable */ 02969 #define SPI_IER_OVRES (0x1u << 3) /* (SPI_IER) Overrun Error Interrupt Enable */ 02970 #define SPI_IER_ENDRX (0x1u << 4) /* (SPI_IER) End of Receive Buffer Interrupt Enable */ 02971 #define SPI_IER_ENDTX (0x1u << 5) /* (SPI_IER) End of Transmit Buffer Interrupt Enable */ 02972 #define SPI_IER_RXBUFF (0x1u << 6) /* (SPI_IER) Receive Buffer Full Interrupt Enable */ 02973 #define SPI_IER_TXBUFE (0x1u << 7) /* (SPI_IER) Transmit Buffer Empty Interrupt Enable */ 02974 #define SPI_IER_NSSR (0x1u << 8) /* (SPI_IER) NSS Rising Interrupt Enable */ 02975 #define SPI_IER_TXEMPTY (0x1u << 9) /* (SPI_IER) Transmission Registers Empty Enable */ 02976 #define SPI_IER_UNDES (0x1u << 10) /* (SPI_IER) Underrun Error Interrupt Enable */ 02977 /* -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- */ 02978 #define SPI_IDR_RDRF (0x1u << 0) /* (SPI_IDR) Receive Data Register Full Interrupt Disable */ 02979 #define SPI_IDR_TDRE (0x1u << 1) /* (SPI_IDR) SPI Transmit Data Register Empty Interrupt Disable */ 02980 #define SPI_IDR_MODF (0x1u << 2) /* (SPI_IDR) Mode Fault Error Interrupt Disable */ 02981 #define SPI_IDR_OVRES (0x1u << 3) /* (SPI_IDR) Overrun Error Interrupt Disable */ 02982 #define SPI_IDR_ENDRX (0x1u << 4) /* (SPI_IDR) End of Receive Buffer Interrupt Disable */ 02983 #define SPI_IDR_ENDTX (0x1u << 5) /* (SPI_IDR) End of Transmit Buffer Interrupt Disable */ 02984 #define SPI_IDR_RXBUFF (0x1u << 6) /* (SPI_IDR) Receive Buffer Full Interrupt Disable */ 02985 #define SPI_IDR_TXBUFE (0x1u << 7) /* (SPI_IDR) Transmit Buffer Empty Interrupt Disable */ 02986 #define SPI_IDR_NSSR (0x1u << 8) /* (SPI_IDR) NSS Rising Interrupt Disable */ 02987 #define SPI_IDR_TXEMPTY (0x1u << 9) /* (SPI_IDR) Transmission Registers Empty Disable */ 02988 #define SPI_IDR_UNDES (0x1u << 10) /* (SPI_IDR) Underrun Error Interrupt Disable */ 02989 /* -------- SPI_IMR : (SPI Offset: 0x1C) Interrupt Mask Register -------- */ 02990 #define SPI_IMR_RDRF (0x1u << 0) /* (SPI_IMR) Receive Data Register Full Interrupt Mask */ 02991 #define SPI_IMR_TDRE (0x1u << 1) /* (SPI_IMR) SPI Transmit Data Register Empty Interrupt Mask */ 02992 #define SPI_IMR_MODF (0x1u << 2) /* (SPI_IMR) Mode Fault Error Interrupt Mask */ 02993 #define SPI_IMR_OVRES (0x1u << 3) /* (SPI_IMR) Overrun Error Interrupt Mask */ 02994 #define SPI_IMR_ENDRX (0x1u << 4) /* (SPI_IMR) End of Receive Buffer Interrupt Mask */ 02995 #define SPI_IMR_ENDTX (0x1u << 5) /* (SPI_IMR) End of Transmit Buffer Interrupt Mask */ 02996 #define SPI_IMR_RXBUFF (0x1u << 6) /* (SPI_IMR) Receive Buffer Full Interrupt Mask */ 02997 #define SPI_IMR_TXBUFE (0x1u << 7) /* (SPI_IMR) Transmit Buffer Empty Interrupt Mask */ 02998 #define SPI_IMR_NSSR (0x1u << 8) /* (SPI_IMR) NSS Rising Interrupt Mask */ 02999 #define SPI_IMR_TXEMPTY (0x1u << 9) /* (SPI_IMR) Transmission Registers Empty Mask */ 03000 #define SPI_IMR_UNDES (0x1u << 10) /* (SPI_IMR) Underrun Error Interrupt Mask */ 03001 /* -------- SPI_CSR[4] : (SPI Offset: 0x30) Chip Select Register -------- */ 03002 #define SPI_CSR_CPOL (0x1u << 0) /* (SPI_CSR[4]) Clock Polarity */ 03003 #define SPI_CSR_NCPHA (0x1u << 1) /* (SPI_CSR[4]) Clock Phase */ 03004 #define SPI_CSR_CSNAAT (0x1u << 2) /* (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ 03005 #define SPI_CSR_CSAAT (0x1u << 3) /* (SPI_CSR[4]) Chip Select Not Active After Transfer (Ignored if CSAAT = 1) */ 03006 #define SPI_CSR_BITS_Pos 4 03007 #define SPI_CSR_BITS_Msk (0xfu << SPI_CSR_BITS_Pos) /* (SPI_CSR[4]) Bits Per Transfer */ 03008 #define SPI_CSR_BITS_8_BIT (0x0u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03009 #define SPI_CSR_BITS_9_BIT (0x1u << 4) /* (SPI_CSR[4]) 9_bits for transfer */ 03010 #define SPI_CSR_BITS_10_BIT (0x2u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03011 #define SPI_CSR_BITS_11_BIT (0x3u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03012 #define SPI_CSR_BITS_12_BIT (0x4u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03013 #define SPI_CSR_BITS_13_BIT (0x5u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03014 #define SPI_CSR_BITS_14_BIT (0x6u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03015 #define SPI_CSR_BITS_15_BIT (0x7u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03016 #define SPI_CSR_BITS_16_BIT (0x8u << 4) /* (SPI_CSR[4]) 8_bits for transfer */ 03017 #define SPI_CSR_SCBR_Pos 8 03018 #define SPI_CSR_SCBR_Msk (0xffu << SPI_CSR_SCBR_Pos) /* (SPI_CSR[4]) Serial Clock Baud Rate */ 03019 #define SPI_CSR_SCBR(value) ((SPI_CSR_SCBR_Msk & ((value) << SPI_CSR_SCBR_Pos))) 03020 #define SPI_CSR_DLYBS_Pos 16 03021 #define SPI_CSR_DLYBS_Msk (0xffu << SPI_CSR_DLYBS_Pos) /* (SPI_CSR[4]) Delay Before SPCK */ 03022 #define SPI_CSR_DLYBS(value) ((SPI_CSR_DLYBS_Msk & ((value) << SPI_CSR_DLYBS_Pos))) 03023 #define SPI_CSR_DLYBCT_Pos 24 03024 #define SPI_CSR_DLYBCT_Msk (0xffu << SPI_CSR_DLYBCT_Pos) /* (SPI_CSR[4]) Delay Between Consecutive Transfers */ 03025 #define SPI_CSR_DLYBCT(value) ((SPI_CSR_DLYBCT_Msk & ((value) << SPI_CSR_DLYBCT_Pos))) 03026 /* -------- SPI_WPMR : (SPI Offset: 0xE4) Write Protection Control Register -------- */ 03027 #define SPI_WPMR_SPIWPEN (0x1u << 0) /* (SPI_WPMR) SPI Write Protection Enable */ 03028 #define SPI_WPMR_SPIWPKEY_Pos 8 03029 #define SPI_WPMR_SPIWPKEY_Msk (0xffffffu << SPI_WPMR_SPIWPKEY_Pos) /* (SPI_WPMR) SPI Write Protection Key Password */ 03030 #define SPI_WPMR_SPIWPKEY(value) ((SPI_WPMR_SPIWPKEY_Msk & ((value) << SPI_WPMR_SPIWPKEY_Pos))) 03031 /* -------- SPI_WPSR : (SPI Offset: 0xE8) Write Protection Status Register -------- */ 03032 #define SPI_WPSR_SPIWPVS_Pos 0 03033 #define SPI_WPSR_SPIWPVS_Msk (0x7u << SPI_WPSR_SPIWPVS_Pos) /* (SPI_WPSR) SPI Write Protection Violation Status */ 03034 #define SPI_WPSR_SPIWPVSRC_Pos 8 03035 #define SPI_WPSR_SPIWPVSRC_Msk (0xffu << SPI_WPSR_SPIWPVSRC_Pos) /* (SPI_WPSR) SPI Write Protection Violation Source */ 03036 /* -------- SPI_RPR : (SPI Offset: 0x100) Receive Pointer Register -------- */ 03037 #define SPI_RPR_RXPTR_Pos 0 03038 #define SPI_RPR_RXPTR_Msk (0xffffffffu << SPI_RPR_RXPTR_Pos) /* (SPI_RPR) Receive Pointer Register */ 03039 #define SPI_RPR_RXPTR(value) ((SPI_RPR_RXPTR_Msk & ((value) << SPI_RPR_RXPTR_Pos))) 03040 /* -------- SPI_RCR : (SPI Offset: 0x104) Receive Counter Register -------- */ 03041 #define SPI_RCR_RXCTR_Pos 0 03042 #define SPI_RCR_RXCTR_Msk (0xffffu << SPI_RCR_RXCTR_Pos) /* (SPI_RCR) Receive Counter Register */ 03043 #define SPI_RCR_RXCTR(value) ((SPI_RCR_RXCTR_Msk & ((value) << SPI_RCR_RXCTR_Pos))) 03044 /* -------- SPI_TPR : (SPI Offset: 0x108) Transmit Pointer Register -------- */ 03045 #define SPI_TPR_TXPTR_Pos 0 03046 #define SPI_TPR_TXPTR_Msk (0xffffffffu << SPI_TPR_TXPTR_Pos) /* (SPI_TPR) Transmit Counter Register */ 03047 #define SPI_TPR_TXPTR(value) ((SPI_TPR_TXPTR_Msk & ((value) << SPI_TPR_TXPTR_Pos))) 03048 /* -------- SPI_TCR : (SPI Offset: 0x10C) Transmit Counter Register -------- */ 03049 #define SPI_TCR_TXCTR_Pos 0 03050 #define SPI_TCR_TXCTR_Msk (0xffffu << SPI_TCR_TXCTR_Pos) /* (SPI_TCR) Transmit Counter Register */ 03051 #define SPI_TCR_TXCTR(value) ((SPI_TCR_TXCTR_Msk & ((value) << SPI_TCR_TXCTR_Pos))) 03052 /* -------- SPI_RNPR : (SPI Offset: 0x110) Receive Next Pointer Register -------- */ 03053 #define SPI_RNPR_RXNPTR_Pos 0 03054 #define SPI_RNPR_RXNPTR_Msk (0xffffffffu << SPI_RNPR_RXNPTR_Pos) /* (SPI_RNPR) Receive Next Pointer */ 03055 #define SPI_RNPR_RXNPTR(value) ((SPI_RNPR_RXNPTR_Msk & ((value) << SPI_RNPR_RXNPTR_Pos))) 03056 /* -------- SPI_RNCR : (SPI Offset: 0x114) Receive Next Counter Register -------- */ 03057 #define SPI_RNCR_RXNCTR_Pos 0 03058 #define SPI_RNCR_RXNCTR_Msk (0xffffu << SPI_RNCR_RXNCTR_Pos) /* (SPI_RNCR) Receive Next Counter */ 03059 #define SPI_RNCR_RXNCTR(value) ((SPI_RNCR_RXNCTR_Msk & ((value) << SPI_RNCR_RXNCTR_Pos))) 03060 /* -------- SPI_TNPR : (SPI Offset: 0x118) Transmit Next Pointer Register -------- */ 03061 #define SPI_TNPR_TXNPTR_Pos 0 03062 #define SPI_TNPR_TXNPTR_Msk (0xffffffffu << SPI_TNPR_TXNPTR_Pos) /* (SPI_TNPR) Transmit Next Pointer */ 03063 #define SPI_TNPR_TXNPTR(value) ((SPI_TNPR_TXNPTR_Msk & ((value) << SPI_TNPR_TXNPTR_Pos))) 03064 /* -------- SPI_TNCR : (SPI Offset: 0x11C) Transmit Next Counter Register -------- */ 03065 #define SPI_TNCR_TXNCTR_Pos 0 03066 #define SPI_TNCR_TXNCTR_Msk (0xffffu << SPI_TNCR_TXNCTR_Pos) /* (SPI_TNCR) Transmit Counter Next */ 03067 #define SPI_TNCR_TXNCTR(value) ((SPI_TNCR_TXNCTR_Msk & ((value) << SPI_TNCR_TXNCTR_Pos))) 03068 /* -------- SPI_PTCR : (SPI Offset: 0x120) Transfer Control Register -------- */ 03069 #define SPI_PTCR_RXTEN (0x1u << 0) /* (SPI_PTCR) Receiver Transfer Enable */ 03070 #define SPI_PTCR_RXTDIS (0x1u << 1) /* (SPI_PTCR) Receiver Transfer Disable */ 03071 #define SPI_PTCR_TXTEN (0x1u << 8) /* (SPI_PTCR) Transmitter Transfer Enable */ 03072 #define SPI_PTCR_TXTDIS (0x1u << 9) /* (SPI_PTCR) Transmitter Transfer Disable */ 03073 /* -------- SPI_PTSR : (SPI Offset: 0x124) Transfer Status Register -------- */ 03074 #define SPI_PTSR_RXTEN (0x1u << 0) /* (SPI_PTSR) Receiver Transfer Enable */ 03075 #define SPI_PTSR_TXTEN (0x1u << 8) /* (SPI_PTSR) Transmitter Transfer Enable */ 03076 03077 03078 03079 /* ============================================================================= */ 03080 /* SOFTWARE API DEFINITION FOR Timer Counter */ 03081 /* ============================================================================= */ 03082 03083 #ifndef __ASSEMBLY__ 03084 /* TcChannel hardware registers */ 03085 typedef struct { 03086 RwReg TC_CCR; /* (TcChannel Offset: 0x0) Channel Control Register */ 03087 RwReg TC_CMR; /* (TcChannel Offset: 0x4) Channel Mode Register */ 03088 RwReg TC_SMMR; /* (TcChannel Offset: 0x8) Stepper Motor Mode Register */ 03089 RwReg Reserved1[1]; 03090 RwReg TC_CV; /* (TcChannel Offset: 0x10) Counter Value */ 03091 RwReg TC_RA; /* (TcChannel Offset: 0x14) Register A */ 03092 RwReg TC_RB; /* (TcChannel Offset: 0x18) Register B */ 03093 RwReg TC_RC; /* (TcChannel Offset: 0x1C) Register C */ 03094 RwReg TC_SR; /* (TcChannel Offset: 0x20) Status Register */ 03095 RwReg TC_IER; /* (TcChannel Offset: 0x24) Interrupt Enable Register */ 03096 RwReg TC_IDR; /* (TcChannel Offset: 0x28) Interrupt Disable Register */ 03097 RwReg TC_IMR; /* (TcChannel Offset: 0x2C) Interrupt Mask Register */ 03098 RwReg Reserved2[4]; 03099 } TcChannel; 03100 /* Tc hardware registers */ 03101 typedef struct { 03102 TcChannel TC_CHANNEL[3]; /* (Tc Offset: 0x0) channel = 0 .. 2 */ 03103 WoReg TC_BCR; /* (Tc Offset: 0xC0) Block Control Register */ 03104 RwReg TC_BMR; /* (Tc Offset: 0xC4) Block Mode Register */ 03105 WoReg TC_QIER; /* (Tc Offset: 0xC8) QDEC Interrupt Enable Register */ 03106 WoReg TC_QIDR; /* (Tc Offset: 0xCC) QDEC Interrupt Disable Register */ 03107 RoReg TC_QIMR; /* (Tc Offset: 0xD0) QDEC Interrupt Mask Register */ 03108 RoReg TC_QISR; /* (Tc Offset: 0xD4) QDEC Interrupt Status Register */ 03109 RwReg Reserved1[3]; 03110 RwReg TC_WPMR; /* (Tc Offset: 0xE4) Write Protect Mode Register */ 03111 } Tc; 03112 #endif /* __ASSEMBLY__ */ 03113 /* -------- TC_CCR : (TC Offset: N/A) Channel Control Register -------- */ 03114 #define TC_CCR_CLKEN (0x1u << 0) /* (TC_CCR) Counter Clock Enable Command */ 03115 #define TC_CCR_CLKDIS (0x1u << 1) /* (TC_CCR) Counter Clock Disable Command */ 03116 #define TC_CCR_SWTRG (0x1u << 2) /* (TC_CCR) Software Trigger Command */ 03117 /* -------- TC_CMR : (TC Offset: N/A) Channel Mode Register -------- */ 03118 #define TC_CMR_TCCLKS_Pos 0 03119 #define TC_CMR_TCCLKS_Msk (0x7u << TC_CMR_TCCLKS_Pos) /* (TC_CMR) Clock Selection */ 03120 #define TC_CMR_TCCLKS_TIMER_CLOCK1 (0x0u << 0) /* (TC_CMR) Clock selected: TCLK1 */ 03121 #define TC_CMR_TCCLKS_TIMER_CLOCK2 (0x1u << 0) /* (TC_CMR) Clock selected: TCLK2 */ 03122 #define TC_CMR_TCCLKS_TIMER_CLOCK3 (0x2u << 0) /* (TC_CMR) Clock selected: TCLK3 */ 03123 #define TC_CMR_TCCLKS_TIMER_CLOCK4 (0x3u << 0) /* (TC_CMR) Clock selected: TCLK4 */ 03124 #define TC_CMR_TCCLKS_TIMER_CLOCK5 (0x4u << 0) /* (TC_CMR) Clock selected: TCLK5 */ 03125 #define TC_CMR_TCCLKS_XC0 (0x5u << 0) /* (TC_CMR) Clock selected: XC0 */ 03126 #define TC_CMR_TCCLKS_XC1 (0x6u << 0) /* (TC_CMR) Clock selected: XC1 */ 03127 #define TC_CMR_TCCLKS_XC2 (0x7u << 0) /* (TC_CMR) Clock selected: XC2 */ 03128 #define TC_CMR_CLKI (0x1u << 3) /* (TC_CMR) Clock Invert */ 03129 #define TC_CMR_BURST_Pos 4 03130 #define TC_CMR_BURST_Msk (0x3u << TC_CMR_BURST_Pos) /* (TC_CMR) Burst Signal Selection */ 03131 #define TC_CMR_BURST_NONE (0x0u << 4) /* (TC_CMR) The clock is not gated by an external signal. */ 03132 #define TC_CMR_BURST_XC0 (0x1u << 4) /* (TC_CMR) XC0 is ANDed with the selected clock. */ 03133 #define TC_CMR_BURST_XC1 (0x2u << 4) /* (TC_CMR) XC1 is ANDed with the selected clock. */ 03134 #define TC_CMR_BURST_XC2 (0x3u << 4) /* (TC_CMR) XC2 is ANDed with the selected clock. */ 03135 #define TC_CMR_LDBSTOP (0x1u << 6) /* (TC_CMR) Counter Clock Stopped with RB Loading */ 03136 #define TC_CMR_LDBDIS (0x1u << 7) /* (TC_CMR) Counter Clock Disable with RB Loading */ 03137 #define TC_CMR_ETRGEDG_Pos 8 03138 #define TC_CMR_ETRGEDG_Msk (0x3u << TC_CMR_ETRGEDG_Pos) /* (TC_CMR) External Trigger Edge Selection */ 03139 #define TC_CMR_ETRGEDG_NONE (0x0u << 8) /* (TC_CMR) The clock is not gated by an external signal. */ 03140 #define TC_CMR_ETRGEDG_RISING (0x1u << 8) /* (TC_CMR) Rising edge */ 03141 #define TC_CMR_ETRGEDG_FALLING (0x2u << 8) /* (TC_CMR) Falling edge */ 03142 #define TC_CMR_ETRGEDG_EDGE (0x3u << 8) /* (TC_CMR) Each edge */ 03143 #define TC_CMR_ABETRG (0x1u << 10) /* (TC_CMR) TIOA or TIOB External Trigger Selection */ 03144 #define TC_CMR_CPCTRG (0x1u << 14) /* (TC_CMR) RC Compare Trigger Enable */ 03145 #define TC_CMR_WAVE (0x1u << 15) /* (TC_CMR) */ 03146 #define TC_CMR_LDRA_Pos 16 03147 #define TC_CMR_LDRA_Msk (0x3u << TC_CMR_LDRA_Pos) /* (TC_CMR) RA Loading Selection */ 03148 #define TC_CMR_LDRA_NONE (0x0u << 16) /* (TC_CMR) None */ 03149 #define TC_CMR_LDRA_RISING (0x1u << 16) /* (TC_CMR) Rising edge of TIOA */ 03150 #define TC_CMR_LDRA_FALLING (0x2u << 16) /* (TC_CMR) Falling edge of TIOA */ 03151 #define TC_CMR_LDRA_EDGE (0x3u << 16) /* (TC_CMR) Each edge of TIOA */ 03152 #define TC_CMR_LDRB_Pos 18 03153 #define TC_CMR_LDRB_Msk (0x3u << TC_CMR_LDRB_Pos) /* (TC_CMR) RB Loading Selection */ 03154 #define TC_CMR_LDRB_NONE (0x0u << 18) /* (TC_CMR) None */ 03155 #define TC_CMR_LDRB_RISING (0x1u << 18) /* (TC_CMR) Rising edge of TIOA */ 03156 #define TC_CMR_LDRB_FALLING (0x2u << 18) /* (TC_CMR) Falling edge of TIOA */ 03157 #define TC_CMR_LDRB_EDGE (0x3u << 18) /* (TC_CMR) Each edge of TIOA */ 03158 #define TC_CMR_CPCSTOP (0x1u << 6) /* (TC_CMR) Counter Clock Stopped with RC Compare */ 03159 #define TC_CMR_CPCDIS (0x1u << 7) /* (TC_CMR) Counter Clock Disable with RC Compare */ 03160 #define TC_CMR_EEVTEDG_Pos 8 03161 #define TC_CMR_EEVTEDG_Msk (0x3u << TC_CMR_EEVTEDG_Pos) /* (TC_CMR) External Event Edge Selection */ 03162 #define TC_CMR_EEVTEDG_NONE (0x0u << 8) /* (TC_CMR) None */ 03163 #define TC_CMR_EEVTEDG_RISING (0x1u << 8) /* (TC_CMR) Rising edge */ 03164 #define TC_CMR_EEVTEDG_FALLING (0x2u << 8) /* (TC_CMR) Falling edge */ 03165 #define TC_CMR_EEVTEDG_EDGE (0x3u << 8) /* (TC_CMR) Each edge */ 03166 #define TC_CMR_EEVT_Pos 10 03167 #define TC_CMR_EEVT_Msk (0x3u << TC_CMR_EEVT_Pos) /* (TC_CMR) External Event Selection */ 03168 #define TC_CMR_EEVT_TIOB (0x0u << 10) /* (TC_CMR) TIOB */ 03169 #define TC_CMR_EEVT_XC0 (0x1u << 10) /* (TC_CMR) XC0 */ 03170 #define TC_CMR_EEVT_XC1 (0x2u << 10) /* (TC_CMR) XC1 */ 03171 #define TC_CMR_EEVT_XC2 (0x3u << 10) /* (TC_CMR) XC2 */ 03172 #define TC_CMR_ENETRG (0x1u << 12) /* (TC_CMR) External Event Trigger Enable */ 03173 #define TC_CMR_WAVSEL_Pos 13 03174 #define TC_CMR_WAVSEL_Msk (0x3u << TC_CMR_WAVSEL_Pos) /* (TC_CMR) Waveform Selection */ 03175 #define TC_CMR_WAVSEL_UP (0x0u << 13) /* (TC_CMR) UP mode without automatic trigger on RC Compare */ 03176 #define TC_CMR_WAVSEL_UPDOWN (0x1u << 13) /* (TC_CMR) UPDOWN mode without automatic trigger on RC Compare */ 03177 #define TC_CMR_WAVSEL_UP_RC (0x2u << 13) /* (TC_CMR) UP mode with automatic trigger on RC Compare */ 03178 #define TC_CMR_WAVSEL_UPDOWN_RC (0x3u << 13) /* (TC_CMR) UPDOWN mode with automatic trigger on RC Compare */ 03179 #define TC_CMR_ACPA_Pos 16 03180 #define TC_CMR_ACPA_Msk (0x3u << TC_CMR_ACPA_Pos) /* (TC_CMR) RA Compare Effect on TIOA */ 03181 #define TC_CMR_ACPA_NONE (0x0u << 16) /* (TC_CMR) None */ 03182 #define TC_CMR_ACPA_SET (0x1u << 16) /* (TC_CMR) Set */ 03183 #define TC_CMR_ACPA_CLEAR (0x2u << 16) /* (TC_CMR) Clear */ 03184 #define TC_CMR_ACPA_TOGGLE (0x3u << 16) /* (TC_CMR) Toggle */ 03185 #define TC_CMR_ACPC_Pos 18 03186 #define TC_CMR_ACPC_Msk (0x3u << TC_CMR_ACPC_Pos) /* (TC_CMR) RC Compare Effect on TIOA */ 03187 #define TC_CMR_ACPC_NONE (0x0u << 18) /* (TC_CMR) None */ 03188 #define TC_CMR_ACPC_SET (0x1u << 18) /* (TC_CMR) Set */ 03189 #define TC_CMR_ACPC_CLEAR (0x2u << 18) /* (TC_CMR) Clear */ 03190 #define TC_CMR_ACPC_TOGGLE (0x3u << 18) /* (TC_CMR) Toggle */ 03191 #define TC_CMR_AEEVT_Pos 20 03192 #define TC_CMR_AEEVT_Msk (0x3u << TC_CMR_AEEVT_Pos) /* (TC_CMR) External Event Effect on TIOA */ 03193 #define TC_CMR_AEEVT_NONE (0x0u << 20) /* (TC_CMR) None */ 03194 #define TC_CMR_AEEVT_SET (0x1u << 20) /* (TC_CMR) Set */ 03195 #define TC_CMR_AEEVT_CLEAR (0x2u << 20) /* (TC_CMR) Clear */ 03196 #define TC_CMR_AEEVT_TOGGLE (0x3u << 20) /* (TC_CMR) Toggle */ 03197 #define TC_CMR_ASWTRG_Pos 22 03198 #define TC_CMR_ASWTRG_Msk (0x3u << TC_CMR_ASWTRG_Pos) /* (TC_CMR) Software Trigger Effect on TIOA */ 03199 #define TC_CMR_ASWTRG_NONE (0x0u << 22) /* (TC_CMR) None */ 03200 #define TC_CMR_ASWTRG_SET (0x1u << 22) /* (TC_CMR) Set */ 03201 #define TC_CMR_ASWTRG_CLEAR (0x2u << 22) /* (TC_CMR) Clear */ 03202 #define TC_CMR_ASWTRG_TOGGLE (0x3u << 22) /* (TC_CMR) Toggle */ 03203 #define TC_CMR_BCPB_Pos 24 03204 #define TC_CMR_BCPB_Msk (0x3u << TC_CMR_BCPB_Pos) /* (TC_CMR) RB Compare Effect on TIOB */ 03205 #define TC_CMR_BCPB_NONE (0x0u << 24) /* (TC_CMR) None */ 03206 #define TC_CMR_BCPB_SET (0x1u << 24) /* (TC_CMR) Set */ 03207 #define TC_CMR_BCPB_CLEAR (0x2u << 24) /* (TC_CMR) Clear */ 03208 #define TC_CMR_BCPB_TOGGLE (0x3u << 24) /* (TC_CMR) Toggle */ 03209 #define TC_CMR_BCPC_Pos 26 03210 #define TC_CMR_BCPC_Msk (0x3u << TC_CMR_BCPC_Pos) /* (TC_CMR) RC Compare Effect on TIOB */ 03211 #define TC_CMR_BCPC_NONE (0x0u << 26) /* (TC_CMR) None */ 03212 #define TC_CMR_BCPC_SET (0x1u << 26) /* (TC_CMR) Set */ 03213 #define TC_CMR_BCPC_CLEAR (0x2u << 26) /* (TC_CMR) Clear */ 03214 #define TC_CMR_BCPC_TOGGLE (0x3u << 26) /* (TC_CMR) Toggle */ 03215 #define TC_CMR_BEEVT_Pos 28 03216 #define TC_CMR_BEEVT_Msk (0x3u << TC_CMR_BEEVT_Pos) /* (TC_CMR) External Event Effect on TIOB */ 03217 #define TC_CMR_BEEVT_NONE (0x0u << 28) /* (TC_CMR) None */ 03218 #define TC_CMR_BEEVT_SET (0x1u << 28) /* (TC_CMR) Set */ 03219 #define TC_CMR_BEEVT_CLEAR (0x2u << 28) /* (TC_CMR) Clear */ 03220 #define TC_CMR_BEEVT_TOGGLE (0x3u << 28) /* (TC_CMR) Toggle */ 03221 #define TC_CMR_BSWTRG_Pos 30 03222 #define TC_CMR_BSWTRG_Msk (0x3u << TC_CMR_BSWTRG_Pos) /* (TC_CMR) Software Trigger Effect on TIOB */ 03223 #define TC_CMR_BSWTRG_NONE (0x0u << 30) /* (TC_CMR) None */ 03224 #define TC_CMR_BSWTRG_SET (0x1u << 30) /* (TC_CMR) Set */ 03225 #define TC_CMR_BSWTRG_CLEAR (0x2u << 30) /* (TC_CMR) Clear */ 03226 #define TC_CMR_BSWTRG_TOGGLE (0x3u << 30) /* (TC_CMR) Toggle */ 03227 /* -------- TC_SMMR : (TC Offset: N/A) Stepper Motor Mode Register -------- */ 03228 #define TC_SMMR_GCEN (0x1u << 0) /* (TC_SMMR) Gray Count Enable */ 03229 #define TC_SMMR_DOWN (0x1u << 1) /* (TC_SMMR) DOWN Count */ 03230 /* -------- TC_CV : (TC Offset: N/A) Counter Value -------- */ 03231 #define TC_CV_CV_Pos 0 03232 #define TC_CV_CV_Msk (0xffffffffu << TC_CV_CV_Pos) /* (TC_CV) Counter Value */ 03233 /* -------- TC_RA : (TC Offset: N/A) Register A -------- */ 03234 #define TC_RA_RA_Pos 0 03235 #define TC_RA_RA_Msk (0xffffffffu << TC_RA_RA_Pos) /* (TC_RA) Register A */ 03236 #define TC_RA_RA(value) ((TC_RA_RA_Msk & ((value) << TC_RA_RA_Pos))) 03237 /* -------- TC_RB : (TC Offset: N/A) Register B -------- */ 03238 #define TC_RB_RB_Pos 0 03239 #define TC_RB_RB_Msk (0xffffffffu << TC_RB_RB_Pos) /* (TC_RB) Register B */ 03240 #define TC_RB_RB(value) ((TC_RB_RB_Msk & ((value) << TC_RB_RB_Pos))) 03241 /* -------- TC_RC : (TC Offset: N/A) Register C -------- */ 03242 #define TC_RC_RC_Pos 0 03243 #define TC_RC_RC_Msk (0xffffffffu << TC_RC_RC_Pos) /* (TC_RC) Register C */ 03244 #define TC_RC_RC(value) ((TC_RC_RC_Msk & ((value) << TC_RC_RC_Pos))) 03245 /* -------- TC_SR : (TC Offset: N/A) Status Register -------- */ 03246 #define TC_SR_COVFS (0x1u << 0) /* (TC_SR) Counter Overflow Status */ 03247 #define TC_SR_LOVRS (0x1u << 1) /* (TC_SR) Load Overrun Status */ 03248 #define TC_SR_CPAS (0x1u << 2) /* (TC_SR) RA Compare Status */ 03249 #define TC_SR_CPBS (0x1u << 3) /* (TC_SR) RB Compare Status */ 03250 #define TC_SR_CPCS (0x1u << 4) /* (TC_SR) RC Compare Status */ 03251 #define TC_SR_LDRAS (0x1u << 5) /* (TC_SR) RA Loading Status */ 03252 #define TC_SR_LDRBS (0x1u << 6) /* (TC_SR) RB Loading Status */ 03253 #define TC_SR_ETRGS (0x1u << 7) /* (TC_SR) External Trigger Status */ 03254 #define TC_SR_CLKSTA (0x1u << 16) /* (TC_SR) Clock Enabling Status */ 03255 #define TC_SR_MTIOA (0x1u << 17) /* (TC_SR) TIOA Mirror */ 03256 #define TC_SR_MTIOB (0x1u << 18) /* (TC_SR) TIOB Mirror */ 03257 /* -------- TC_IER : (TC Offset: N/A) Interrupt Enable Register -------- */ 03258 #define TC_IER_COVFS (0x1u << 0) /* (TC_IER) Counter Overflow */ 03259 #define TC_IER_LOVRS (0x1u << 1) /* (TC_IER) Load Overrun */ 03260 #define TC_IER_CPAS (0x1u << 2) /* (TC_IER) RA Compare */ 03261 #define TC_IER_CPBS (0x1u << 3) /* (TC_IER) RB Compare */ 03262 #define TC_IER_CPCS (0x1u << 4) /* (TC_IER) RC Compare */ 03263 #define TC_IER_LDRAS (0x1u << 5) /* (TC_IER) RA Loading */ 03264 #define TC_IER_LDRBS (0x1u << 6) /* (TC_IER) RB Loading */ 03265 #define TC_IER_ETRGS (0x1u << 7) /* (TC_IER) External Trigger */ 03266 /* -------- TC_IDR : (TC Offset: N/A) Interrupt Disable Register -------- */ 03267 #define TC_IDR_COVFS (0x1u << 0) /* (TC_IDR) Counter Overflow */ 03268 #define TC_IDR_LOVRS (0x1u << 1) /* (TC_IDR) Load Overrun */ 03269 #define TC_IDR_CPAS (0x1u << 2) /* (TC_IDR) RA Compare */ 03270 #define TC_IDR_CPBS (0x1u << 3) /* (TC_IDR) RB Compare */ 03271 #define TC_IDR_CPCS (0x1u << 4) /* (TC_IDR) RC Compare */ 03272 #define TC_IDR_LDRAS (0x1u << 5) /* (TC_IDR) RA Loading */ 03273 #define TC_IDR_LDRBS (0x1u << 6) /* (TC_IDR) RB Loading */ 03274 #define TC_IDR_ETRGS (0x1u << 7) /* (TC_IDR) External Trigger */ 03275 /* -------- TC_IMR : (TC Offset: N/A) Interrupt Mask Register -------- */ 03276 #define TC_IMR_COVFS (0x1u << 0) /* (TC_IMR) Counter Overflow */ 03277 #define TC_IMR_LOVRS (0x1u << 1) /* (TC_IMR) Load Overrun */ 03278 #define TC_IMR_CPAS (0x1u << 2) /* (TC_IMR) RA Compare */ 03279 #define TC_IMR_CPBS (0x1u << 3) /* (TC_IMR) RB Compare */ 03280 #define TC_IMR_CPCS (0x1u << 4) /* (TC_IMR) RC Compare */ 03281 #define TC_IMR_LDRAS (0x1u << 5) /* (TC_IMR) RA Loading */ 03282 #define TC_IMR_LDRBS (0x1u << 6) /* (TC_IMR) RB Loading */ 03283 #define TC_IMR_ETRGS (0x1u << 7) /* (TC_IMR) External Trigger */ 03284 /* -------- TC_BCR : (TC Offset: 0xC0) Block Control Register -------- */ 03285 #define TC_BCR_SYNC (0x1u << 0) /* (TC_BCR) Synchro Command */ 03286 /* -------- TC_BMR : (TC Offset: 0xC4) Block Mode Register -------- */ 03287 #define TC_BMR_TC0XC0S_Pos 0 03288 #define TC_BMR_TC0XC0S_Msk (0x3u << TC_BMR_TC0XC0S_Pos) /* (TC_BMR) External Clock Signal 0 Selection */ 03289 #define TC_BMR_TC0XC0S_TCLK0 (0x0u << 0) /* (TC_BMR) Signal connected to XC0: TCLK0 */ 03290 #define TC_BMR_TC0XC0S_TIOA1 (0x2u << 0) /* (TC_BMR) Signal connected to XC0: TIOA1 */ 03291 #define TC_BMR_TC0XC0S_TIOA2 (0x3u << 0) /* (TC_BMR) Signal connected to XC0: TIOA2 */ 03292 #define TC_BMR_TC1XC1S_Pos 2 03293 #define TC_BMR_TC1XC1S_Msk (0x3u << TC_BMR_TC1XC1S_Pos) /* (TC_BMR) External Clock Signal 1 Selection */ 03294 #define TC_BMR_TC1XC1S_TCLK1 (0x0u << 2) /* (TC_BMR) Signal connected to XC1: TCLK1 */ 03295 #define TC_BMR_TC1XC1S_TIOA0 (0x2u << 2) /* (TC_BMR) Signal connected to XC1: TIOA0 */ 03296 #define TC_BMR_TC1XC1S_TIOA2 (0x3u << 2) /* (TC_BMR) Signal connected to XC1: TIOA2 */ 03297 #define TC_BMR_TC2XC2S_Pos 4 03298 #define TC_BMR_TC2XC2S_Msk (0x3u << TC_BMR_TC2XC2S_Pos) /* (TC_BMR) External Clock Signal 2 Selection */ 03299 #define TC_BMR_TC2XC2S_TCLK2 (0x0u << 4) /* (TC_BMR) Signal connected to XC2: TCLK2 */ 03300 #define TC_BMR_TC2XC2S_TIOA1 (0x2u << 4) /* (TC_BMR) Signal connected to XC2: TIOA1 */ 03301 #define TC_BMR_TC2XC2S_TIOA2 (0x3u << 4) /* (TC_BMR) Signal connected to XC2: TIOA2 */ 03302 #define TC_BMR_QDEN (0x1u << 8) /* (TC_BMR) Quadrature Decoder ENabled */ 03303 #define TC_BMR_POSEN (0x1u << 9) /* (TC_BMR) POSition ENabled */ 03304 #define TC_BMR_SPEEDEN (0x1u << 10) /* (TC_BMR) SPEED ENabled */ 03305 #define TC_BMR_QDTRANS (0x1u << 11) /* (TC_BMR) Quadrature Decoding TRANSparent */ 03306 #define TC_BMR_EDGPHA (0x1u << 12) /* (TC_BMR) EDGe on PHA count mode */ 03307 #define TC_BMR_INVA (0x1u << 13) /* (TC_BMR) INVerted phA */ 03308 #define TC_BMR_INVB (0x1u << 14) /* (TC_BMR) INVerted phB */ 03309 #define TC_BMR_INVIDX (0x1u << 15) /* (TC_BMR) INVerted InDeX */ 03310 #define TC_BMR_SWAP (0x1u << 16) /* (TC_BMR) SWAP PHA and PHB */ 03311 #define TC_BMR_IDXPHB (0x1u << 17) /* (TC_BMR) InDeX pin is PHB pin */ 03312 #define TC_BMR_FILTER (0x1u << 19) /* (TC_BMR) */ 03313 #define TC_BMR_MAXFILT_Pos 20 03314 #define TC_BMR_MAXFILT_Msk (0x3fu << TC_BMR_MAXFILT_Pos) /* (TC_BMR) MAXimum FILTer */ 03315 #define TC_BMR_MAXFILT(value) ((TC_BMR_MAXFILT_Msk & ((value) << TC_BMR_MAXFILT_Pos))) 03316 /* -------- TC_QIER : (TC Offset: 0xC8) QDEC Interrupt Enable Register -------- */ 03317 #define TC_QIER_IDX (0x1u << 0) /* (TC_QIER) InDeX */ 03318 #define TC_QIER_DIRCHG (0x1u << 1) /* (TC_QIER) DIRection CHanGe */ 03319 #define TC_QIER_QERR (0x1u << 2) /* (TC_QIER) Quadrature ERRor */ 03320 /* -------- TC_QIDR : (TC Offset: 0xCC) QDEC Interrupt Disable Register -------- */ 03321 #define TC_QIDR_IDX (0x1u << 0) /* (TC_QIDR) InDeX */ 03322 #define TC_QIDR_DIRCHG (0x1u << 1) /* (TC_QIDR) DIRection CHanGe */ 03323 #define TC_QIDR_QERR (0x1u << 2) /* (TC_QIDR) Quadrature ERRor */ 03324 /* -------- TC_QIMR : (TC Offset: 0xD0) QDEC Interrupt Mask Register -------- */ 03325 #define TC_QIMR_IDX (0x1u << 0) /* (TC_QIMR) InDeX */ 03326 #define TC_QIMR_DIRCHG (0x1u << 1) /* (TC_QIMR) DIRection CHanGe */ 03327 #define TC_QIMR_QERR (0x1u << 2) /* (TC_QIMR) Quadrature ERRor */ 03328 /* -------- TC_QISR : (TC Offset: 0xD4) QDEC Interrupt Status Register -------- */ 03329 #define TC_QISR_IDX (0x1u << 0) /* (TC_QISR) InDeX */ 03330 #define TC_QISR_DIRCHG (0x1u << 1) /* (TC_QISR) DIRection CHanGe */ 03331 #define TC_QISR_QERR (0x1u << 2) /* (TC_QISR) Quadrature ERRor */ 03332 #define TC_QISR_DIR (0x1u << 8) /* (TC_QISR) Direction */ 03333 /* -------- TC_WPMR : (TC Offset: 0xE4) Write Protect Mode Register -------- */ 03334 #define TC_WPMR_WPEN (0x1u << 0) /* (TC_WPMR) Write Protect Enable */ 03335 #define TC_WPMR_WPKEY_Pos 8 03336 #define TC_WPMR_WPKEY_Msk (0xffffffu << TC_WPMR_WPKEY_Pos) /* (TC_WPMR) Write Protect KEY */ 03337 #define TC_WPMR_WPKEY(value) ((TC_WPMR_WPKEY_Msk & ((value) << TC_WPMR_WPKEY_Pos))) 03338 03339 03340 /* ============================================================================= */ 03341 /* SOFTWARE API DEFINITION FOR Two-wire Interface */ 03342 /* ============================================================================= */ 03343 03344 #ifndef __ASSEMBLY__ 03345 /* Twi hardware registers */ 03346 typedef struct { 03347 WoReg TWI_CR; /* (Twi Offset: 0x00) Control Register */ 03348 RwReg TWI_MMR; /* (Twi Offset: 0x04) Master Mode Register */ 03349 RwReg TWI_SMR; /* (Twi Offset: 0x08) Slave Mode Register */ 03350 RwReg TWI_IADR; /* (Twi Offset: 0x0C) Internal Address Register */ 03351 RwReg TWI_CWGR; /* (Twi Offset: 0x10) Clock Waveform Generator Register */ 03352 RwReg Reserved1[3]; 03353 RoReg TWI_SR; /* (Twi Offset: 0x20) Status Register */ 03354 WoReg TWI_IER; /* (Twi Offset: 0x24) Interrupt Enable Register */ 03355 WoReg TWI_IDR; /* (Twi Offset: 0x28) Interrupt Disable Register */ 03356 RoReg TWI_IMR; /* (Twi Offset: 0x2C) Interrupt Mask Register */ 03357 RoReg TWI_RHR; /* (Twi Offset: 0x30) Receive Holding Register */ 03358 WoReg TWI_THR; /* (Twi Offset: 0x34) Transmit Holding Register */ 03359 RwReg Reserved2[50]; 03360 RwReg TWI_RPR; /* (Twi Offset: 0x100) Receive Pointer Register */ 03361 RwReg TWI_RCR; /* (Twi Offset: 0x104) Receive Counter Register */ 03362 RwReg TWI_TPR; /* (Twi Offset: 0x108) Transmit Pointer Register */ 03363 RwReg TWI_TCR; /* (Twi Offset: 0x10C) Transmit Counter Register */ 03364 RwReg TWI_RNPR; /* (Twi Offset: 0x110) Receive Next Pointer Register */ 03365 RwReg TWI_RNCR; /* (Twi Offset: 0x114) Receive Next Counter Register */ 03366 RwReg TWI_TNPR; /* (Twi Offset: 0x118) Transmit Next Pointer Register */ 03367 RwReg TWI_TNCR; /* (Twi Offset: 0x11C) Transmit Next Counter Register */ 03368 WoReg TWI_PTCR; /* (Twi Offset: 0x120) Transfer Control Register */ 03369 RoReg TWI_PTSR; /* (Twi Offset: 0x124) Transfer Status Register */ 03370 } Twi; 03371 #endif /* __ASSEMBLY__ */ 03372 /* -------- TWI_CR : (TWI Offset: 0x00) Control Register -------- */ 03373 #define TWI_CR_START (0x1u << 0) /* (TWI_CR) Send a START Condition */ 03374 #define TWI_CR_STOP (0x1u << 1) /* (TWI_CR) Send a STOP Condition */ 03375 #define TWI_CR_MSEN (0x1u << 2) /* (TWI_CR) TWI Master Mode Enabled */ 03376 #define TWI_CR_MSDIS (0x1u << 3) /* (TWI_CR) TWI Master Mode Disabled */ 03377 #define TWI_CR_SVEN (0x1u << 4) /* (TWI_CR) TWI Slave Mode Enabled */ 03378 #define TWI_CR_SVDIS (0x1u << 5) /* (TWI_CR) TWI Slave Mode Disabled */ 03379 #define TWI_CR_QUICK (0x1u << 6) /* (TWI_CR) SMBUS Quick Command */ 03380 #define TWI_CR_SWRST (0x1u << 7) /* (TWI_CR) Software Reset */ 03381 /* -------- TWI_MMR : (TWI Offset: 0x04) Master Mode Register -------- */ 03382 #define TWI_MMR_IADRSZ_Pos 8 03383 #define TWI_MMR_IADRSZ_Msk (0x3u << TWI_MMR_IADRSZ_Pos) /* (TWI_MMR) Internal Device Address Size */ 03384 #define TWI_MMR_IADRSZ_NONE (0x0u << 8) /* (TWI_MMR) No internal device address */ 03385 #define TWI_MMR_IADRSZ_1_BYTE (0x1u << 8) /* (TWI_MMR) One-byte internal device address */ 03386 #define TWI_MMR_IADRSZ_2_BYTE (0x2u << 8) /* (TWI_MMR) Two-byte internal device address */ 03387 #define TWI_MMR_IADRSZ_3_BYTE (0x3u << 8) /* (TWI_MMR) Three-byte internal device address */ 03388 #define TWI_MMR_MREAD (0x1u << 12) /* (TWI_MMR) Master Read Direction */ 03389 #define TWI_MMR_DADR_Pos 16 03390 #define TWI_MMR_DADR_Msk (0x7fu << TWI_MMR_DADR_Pos) /* (TWI_MMR) Device Address */ 03391 #define TWI_MMR_DADR(value) ((TWI_MMR_DADR_Msk & ((value) << TWI_MMR_DADR_Pos))) 03392 /* -------- TWI_SMR : (TWI Offset: 0x08) Slave Mode Register -------- */ 03393 #define TWI_SMR_SADR_Pos 16 03394 #define TWI_SMR_SADR_Msk (0x7fu << TWI_SMR_SADR_Pos) /* (TWI_SMR) Slave Address */ 03395 #define TWI_SMR_SADR(value) ((TWI_SMR_SADR_Msk & ((value) << TWI_SMR_SADR_Pos))) 03396 /* -------- TWI_IADR : (TWI Offset: 0x0C) Internal Address Register -------- */ 03397 #define TWI_IADR_IADR_Pos 0 03398 #define TWI_IADR_IADR_Msk (0xffffffu << TWI_IADR_IADR_Pos) /* (TWI_IADR) Internal Address */ 03399 #define TWI_IADR_IADR(value) ((TWI_IADR_IADR_Msk & ((value) << TWI_IADR_IADR_Pos))) 03400 /* -------- TWI_CWGR : (TWI Offset: 0x10) Clock Waveform Generator Register -------- */ 03401 #define TWI_CWGR_CLDIV_Pos 0 03402 #define TWI_CWGR_CLDIV_Msk (0xffu << TWI_CWGR_CLDIV_Pos) /* (TWI_CWGR) Clock Low Divider */ 03403 #define TWI_CWGR_CLDIV(value) ((TWI_CWGR_CLDIV_Msk & ((value) << TWI_CWGR_CLDIV_Pos))) 03404 #define TWI_CWGR_CHDIV_Pos 8 03405 #define TWI_CWGR_CHDIV_Msk (0xffu << TWI_CWGR_CHDIV_Pos) /* (TWI_CWGR) Clock High Divider */ 03406 #define TWI_CWGR_CHDIV(value) ((TWI_CWGR_CHDIV_Msk & ((value) << TWI_CWGR_CHDIV_Pos))) 03407 #define TWI_CWGR_CKDIV_Pos 16 03408 #define TWI_CWGR_CKDIV_Msk (0x7u << TWI_CWGR_CKDIV_Pos) /* (TWI_CWGR) Clock Divider */ 03409 #define TWI_CWGR_CKDIV(value) ((TWI_CWGR_CKDIV_Msk & ((value) << TWI_CWGR_CKDIV_Pos))) 03410 /* -------- TWI_SR : (TWI Offset: 0x20) Status Register -------- */ 03411 #define TWI_SR_TXCOMP (0x1u << 0) /* (TWI_SR) Transmission Completed (automatically set / reset) */ 03412 #define TWI_SR_RXRDY (0x1u << 1) /* (TWI_SR) Receive Holding Register Ready (automatically set / reset) */ 03413 #define TWI_SR_TXRDY (0x1u << 2) /* (TWI_SR) Transmit Holding Register Ready (automatically set / reset) */ 03414 #define TWI_SR_SVREAD (0x1u << 3) /* (TWI_SR) Slave Read (automatically set / reset) */ 03415 #define TWI_SR_SVACC (0x1u << 4) /* (TWI_SR) Slave Access (automatically set / reset) */ 03416 #define TWI_SR_GACC (0x1u << 5) /* (TWI_SR) General Call Access (clear on read) */ 03417 #define TWI_SR_OVRE (0x1u << 6) /* (TWI_SR) Overrun Error (clear on read) */ 03418 #define TWI_SR_NACK (0x1u << 8) /* (TWI_SR) Not Acknowledged (clear on read) */ 03419 #define TWI_SR_ARBLST (0x1u << 9) /* (TWI_SR) Arbitration Lost (clear on read) */ 03420 #define TWI_SR_SCLWS (0x1u << 10) /* (TWI_SR) Clock Wait State (automatically set / reset) */ 03421 #define TWI_SR_EOSACC (0x1u << 11) /* (TWI_SR) End Of Slave Access (clear on read) */ 03422 #define TWI_SR_ENDRX (0x1u << 12) /* (TWI_SR) End of RX buffer */ 03423 #define TWI_SR_ENDTX (0x1u << 13) /* (TWI_SR) End of TX buffer */ 03424 #define TWI_SR_RXBUFF (0x1u << 14) /* (TWI_SR) RX Buffer Full */ 03425 #define TWI_SR_TXBUFE (0x1u << 15) /* (TWI_SR) TX Buffer Empty */ 03426 /* -------- TWI_IER : (TWI Offset: 0x24) Interrupt Enable Register -------- */ 03427 #define TWI_IER_TXCOMP (0x1u << 0) /* (TWI_IER) Transmission Completed Interrupt Enable */ 03428 #define TWI_IER_RXRDY (0x1u << 1) /* (TWI_IER) Receive Holding Register Ready Interrupt Enable */ 03429 #define TWI_IER_TXRDY (0x1u << 2) /* (TWI_IER) Transmit Holding Register Ready Interrupt Enable */ 03430 #define TWI_IER_SVACC (0x1u << 4) /* (TWI_IER) Slave Access Interrupt Enable */ 03431 #define TWI_IER_GACC (0x1u << 5) /* (TWI_IER) General Call Access Interrupt Enable */ 03432 #define TWI_IER_OVRE (0x1u << 6) /* (TWI_IER) Overrun Error Interrupt Enable */ 03433 #define TWI_IER_NACK (0x1u << 8) /* (TWI_IER) Not Acknowledge Interrupt Enable */ 03434 #define TWI_IER_ARBLST (0x1u << 9) /* (TWI_IER) Arbitration Lost Interrupt Enable */ 03435 #define TWI_IER_SCL_WS (0x1u << 10) /* (TWI_IER) Clock Wait State Interrupt Enable */ 03436 #define TWI_IER_EOSACC (0x1u << 11) /* (TWI_IER) End Of Slave Access Interrupt Enable */ 03437 #define TWI_IER_ENDRX (0x1u << 12) /* (TWI_IER) End of Receive Buffer Interrupt Enable */ 03438 #define TWI_IER_ENDTX (0x1u << 13) /* (TWI_IER) End of Transmit Buffer Interrupt Enable */ 03439 #define TWI_IER_RXBUFF (0x1u << 14) /* (TWI_IER) Receive Buffer Full Interrupt Enable */ 03440 #define TWI_IER_TXBUFE (0x1u << 15) /* (TWI_IER) Transmit Buffer Empty Interrupt Enable */ 03441 /* -------- TWI_IDR : (TWI Offset: 0x28) Interrupt Disable Register -------- */ 03442 #define TWI_IDR_TXCOMP (0x1u << 0) /* (TWI_IDR) Transmission Completed Interrupt Disable */ 03443 #define TWI_IDR_RXRDY (0x1u << 1) /* (TWI_IDR) Receive Holding Register Ready Interrupt Disable */ 03444 #define TWI_IDR_TXRDY (0x1u << 2) /* (TWI_IDR) Transmit Holding Register Ready Interrupt Disable */ 03445 #define TWI_IDR_SVACC (0x1u << 4) /* (TWI_IDR) Slave Access Interrupt Disable */ 03446 #define TWI_IDR_GACC (0x1u << 5) /* (TWI_IDR) General Call Access Interrupt Disable */ 03447 #define TWI_IDR_OVRE (0x1u << 6) /* (TWI_IDR) Overrun Error Interrupt Disable */ 03448 #define TWI_IDR_NACK (0x1u << 8) /* (TWI_IDR) Not Acknowledge Interrupt Disable */ 03449 #define TWI_IDR_ARBLST (0x1u << 9) /* (TWI_IDR) Arbitration Lost Interrupt Disable */ 03450 #define TWI_IDR_SCL_WS (0x1u << 10) /* (TWI_IDR) Clock Wait State Interrupt Disable */ 03451 #define TWI_IDR_EOSACC (0x1u << 11) /* (TWI_IDR) End Of Slave Access Interrupt Disable */ 03452 #define TWI_IDR_ENDRX (0x1u << 12) /* (TWI_IDR) End of Receive Buffer Interrupt Disable */ 03453 #define TWI_IDR_ENDTX (0x1u << 13) /* (TWI_IDR) End of Transmit Buffer Interrupt Disable */ 03454 #define TWI_IDR_RXBUFF (0x1u << 14) /* (TWI_IDR) Receive Buffer Full Interrupt Disable */ 03455 #define TWI_IDR_TXBUFE (0x1u << 15) /* (TWI_IDR) Transmit Buffer Empty Interrupt Disable */ 03456 /* -------- TWI_IMR : (TWI Offset: 0x2C) Interrupt Mask Register -------- */ 03457 #define TWI_IMR_TXCOMP (0x1u << 0) /* (TWI_IMR) Transmission Completed Interrupt Mask */ 03458 #define TWI_IMR_RXRDY (0x1u << 1) /* (TWI_IMR) Receive Holding Register Ready Interrupt Mask */ 03459 #define TWI_IMR_TXRDY (0x1u << 2) /* (TWI_IMR) Transmit Holding Register Ready Interrupt Mask */ 03460 #define TWI_IMR_SVACC (0x1u << 4) /* (TWI_IMR) Slave Access Interrupt Mask */ 03461 #define TWI_IMR_GACC (0x1u << 5) /* (TWI_IMR) General Call Access Interrupt Mask */ 03462 #define TWI_IMR_OVRE (0x1u << 6) /* (TWI_IMR) Overrun Error Interrupt Mask */ 03463 #define TWI_IMR_NACK (0x1u << 8) /* (TWI_IMR) Not Acknowledge Interrupt Mask */ 03464 #define TWI_IMR_ARBLST (0x1u << 9) /* (TWI_IMR) Arbitration Lost Interrupt Mask */ 03465 #define TWI_IMR_SCL_WS (0x1u << 10) /* (TWI_IMR) Clock Wait State Interrupt Mask */ 03466 #define TWI_IMR_EOSACC (0x1u << 11) /* (TWI_IMR) End Of Slave Access Interrupt Mask */ 03467 #define TWI_IMR_ENDRX (0x1u << 12) /* (TWI_IMR) End of Receive Buffer Interrupt Mask */ 03468 #define TWI_IMR_ENDTX (0x1u << 13) /* (TWI_IMR) End of Transmit Buffer Interrupt Mask */ 03469 #define TWI_IMR_RXBUFF (0x1u << 14) /* (TWI_IMR) Receive Buffer Full Interrupt Mask */ 03470 #define TWI_IMR_TXBUFE (0x1u << 15) /* (TWI_IMR) Transmit Buffer Empty Interrupt Mask */ 03471 /* -------- TWI_RHR : (TWI Offset: 0x30) Receive Holding Register -------- */ 03472 #define TWI_RHR_RXDATA_Pos 0 03473 #define TWI_RHR_RXDATA_Msk (0xffu << TWI_RHR_RXDATA_Pos) /* (TWI_RHR) Master or Slave Receive Holding Data */ 03474 /* -------- TWI_THR : (TWI Offset: 0x34) Transmit Holding Register -------- */ 03475 #define TWI_THR_TXDATA_Pos 0 03476 #define TWI_THR_TXDATA_Msk (0xffu << TWI_THR_TXDATA_Pos) /* (TWI_THR) Master or Slave Transmit Holding Data */ 03477 #define TWI_THR_TXDATA(value) ((TWI_THR_TXDATA_Msk & ((value) << TWI_THR_TXDATA_Pos))) 03478 /* -------- TWI_RPR : (TWI Offset: 0x100) Receive Pointer Register -------- */ 03479 #define TWI_RPR_RXPTR_Pos 0 03480 #define TWI_RPR_RXPTR_Msk (0xffffffffu << TWI_RPR_RXPTR_Pos) /* (TWI_RPR) Receive Pointer Register */ 03481 #define TWI_RPR_RXPTR(value) ((TWI_RPR_RXPTR_Msk & ((value) << TWI_RPR_RXPTR_Pos))) 03482 /* -------- TWI_RCR : (TWI Offset: 0x104) Receive Counter Register -------- */ 03483 #define TWI_RCR_RXCTR_Pos 0 03484 #define TWI_RCR_RXCTR_Msk (0xffffu << TWI_RCR_RXCTR_Pos) /* (TWI_RCR) Receive Counter Register */ 03485 #define TWI_RCR_RXCTR(value) ((TWI_RCR_RXCTR_Msk & ((value) << TWI_RCR_RXCTR_Pos))) 03486 /* -------- TWI_TPR : (TWI Offset: 0x108) Transmit Pointer Register -------- */ 03487 #define TWI_TPR_TXPTR_Pos 0 03488 #define TWI_TPR_TXPTR_Msk (0xffffffffu << TWI_TPR_TXPTR_Pos) /* (TWI_TPR) Transmit Counter Register */ 03489 #define TWI_TPR_TXPTR(value) ((TWI_TPR_TXPTR_Msk & ((value) << TWI_TPR_TXPTR_Pos))) 03490 /* -------- TWI_TCR : (TWI Offset: 0x10C) Transmit Counter Register -------- */ 03491 #define TWI_TCR_TXCTR_Pos 0 03492 #define TWI_TCR_TXCTR_Msk (0xffffu << TWI_TCR_TXCTR_Pos) /* (TWI_TCR) Transmit Counter Register */ 03493 #define TWI_TCR_TXCTR(value) ((TWI_TCR_TXCTR_Msk & ((value) << TWI_TCR_TXCTR_Pos))) 03494 /* -------- TWI_RNPR : (TWI Offset: 0x110) Receive Next Pointer Register -------- */ 03495 #define TWI_RNPR_RXNPTR_Pos 0 03496 #define TWI_RNPR_RXNPTR_Msk (0xffffffffu << TWI_RNPR_RXNPTR_Pos) /* (TWI_RNPR) Receive Next Pointer */ 03497 #define TWI_RNPR_RXNPTR(value) ((TWI_RNPR_RXNPTR_Msk & ((value) << TWI_RNPR_RXNPTR_Pos))) 03498 /* -------- TWI_RNCR : (TWI Offset: 0x114) Receive Next Counter Register -------- */ 03499 #define TWI_RNCR_RXNCTR_Pos 0 03500 #define TWI_RNCR_RXNCTR_Msk (0xffffu << TWI_RNCR_RXNCTR_Pos) /* (TWI_RNCR) Receive Next Counter */ 03501 #define TWI_RNCR_RXNCTR(value) ((TWI_RNCR_RXNCTR_Msk & ((value) << TWI_RNCR_RXNCTR_Pos))) 03502 /* -------- TWI_TNPR : (TWI Offset: 0x118) Transmit Next Pointer Register -------- */ 03503 #define TWI_TNPR_TXNPTR_Pos 0 03504 #define TWI_TNPR_TXNPTR_Msk (0xffffffffu << TWI_TNPR_TXNPTR_Pos) /* (TWI_TNPR) Transmit Next Pointer */ 03505 #define TWI_TNPR_TXNPTR(value) ((TWI_TNPR_TXNPTR_Msk & ((value) << TWI_TNPR_TXNPTR_Pos))) 03506 /* -------- TWI_TNCR : (TWI Offset: 0x11C) Transmit Next Counter Register -------- */ 03507 #define TWI_TNCR_TXNCTR_Pos 0 03508 #define TWI_TNCR_TXNCTR_Msk (0xffffu << TWI_TNCR_TXNCTR_Pos) /* (TWI_TNCR) Transmit Counter Next */ 03509 #define TWI_TNCR_TXNCTR(value) ((TWI_TNCR_TXNCTR_Msk & ((value) << TWI_TNCR_TXNCTR_Pos))) 03510 /* -------- TWI_PTCR : (TWI Offset: 0x120) Transfer Control Register -------- */ 03511 #define TWI_PTCR_RXTEN (0x1u << 0) /* (TWI_PTCR) Receiver Transfer Enable */ 03512 #define TWI_PTCR_RXTDIS (0x1u << 1) /* (TWI_PTCR) Receiver Transfer Disable */ 03513 #define TWI_PTCR_TXTEN (0x1u << 8) /* (TWI_PTCR) Transmitter Transfer Enable */ 03514 #define TWI_PTCR_TXTDIS (0x1u << 9) /* (TWI_PTCR) Transmitter Transfer Disable */ 03515 /* -------- TWI_PTSR : (TWI Offset: 0x124) Transfer Status Register -------- */ 03516 #define TWI_PTSR_RXTEN (0x1u << 0) /* (TWI_PTSR) Receiver Transfer Enable */ 03517 #define TWI_PTSR_TXTEN (0x1u << 8) /* (TWI_PTSR) Transmitter Transfer Enable */ 03518 03519 03520 03521 03522 /* ************************************************************************** */ 03523 /* REGISTER ACCESS DEFINITIONS FOR SAM3N */ 03524 /* ************************************************************************** */ 03525 03526 /* ========== Register definition for SPI peripheral ========== */ 03527 #define REG_SPI_CR REG_ACCESS(WoReg, 0x40008000U) /* (SPI) Control Register */ 03528 #define REG_SPI_MR REG_ACCESS(RwReg, 0x40008004U) /* (SPI) Mode Register */ 03529 #define REG_SPI_RDR REG_ACCESS(RoReg, 0x40008008U) /* (SPI) Receive Data Register */ 03530 #define REG_SPI_TDR REG_ACCESS(WoReg, 0x4000800CU) /* (SPI) Transmit Data Register */ 03531 #define REG_SPI_SR REG_ACCESS(RoReg, 0x40008010U) /* (SPI) Status Register */ 03532 #define REG_SPI_IER REG_ACCESS(WoReg, 0x40008014U) /* (SPI) Interrupt Enable Register */ 03533 #define REG_SPI_IDR REG_ACCESS(WoReg, 0x40008018U) /* (SPI) Interrupt Disable Register */ 03534 #define REG_SPI_IMR REG_ACCESS(RoReg, 0x4000801CU) /* (SPI) Interrupt Mask Register */ 03535 #define REG_SPI_CSR REG_ACCESS(RwReg, 0x40008030U) /* (SPI) Chip Select Register */ 03536 #define REG_SPI_WPMR REG_ACCESS(RwReg, 0x400080E4U) /* (SPI) Write Protection Control Register */ 03537 #define REG_SPI_WPSR REG_ACCESS(RoReg, 0x400080E8U) /* (SPI) Write Protection Status Register */ 03538 #define REG_SPI_RPR REG_ACCESS(RwReg, 0x40008100U) /* (SPI) Receive Pointer Register */ 03539 #define REG_SPI_RCR REG_ACCESS(RwReg, 0x40008104U) /* (SPI) Receive Counter Register */ 03540 #define REG_SPI_TPR REG_ACCESS(RwReg, 0x40008108U) /* (SPI) Transmit Pointer Register */ 03541 #define REG_SPI_TCR REG_ACCESS(RwReg, 0x4000810CU) /* (SPI) Transmit Counter Register */ 03542 #define REG_SPI_RNPR REG_ACCESS(RwReg, 0x40008110U) /* (SPI) Receive Next Pointer Register */ 03543 #define REG_SPI_RNCR REG_ACCESS(RwReg, 0x40008114U) /* (SPI) Receive Next Counter Register */ 03544 #define REG_SPI_TNPR REG_ACCESS(RwReg, 0x40008118U) /* (SPI) Transmit Next Pointer Register */ 03545 #define REG_SPI_TNCR REG_ACCESS(RwReg, 0x4000811CU) /* (SPI) Transmit Next Counter Register */ 03546 #define REG_SPI_PTCR REG_ACCESS(WoReg, 0x40008120U) /* (SPI) Transfer Control Register */ 03547 #define REG_SPI_PTSR REG_ACCESS(RoReg, 0x40008124U) /* (SPI) Transfer Status Register */ 03548 /* ========== Register definition for TC0 peripheral ========== */ 03549 #define REG_TC0_CCR0 REG_ACCESS(WoReg, 0x40010000U) /* (TC0) Channel Control Register (channel = 0) */ 03550 #define REG_TC0_CMR0 REG_ACCESS(RwReg, 0x40010004U) /* (TC0) Channel Mode Register (channel = 0) */ 03551 #define REG_TC0_SMMR0 REG_ACCESS(RwReg, 0x40010008U) /* (TC0) Stepper Motor Mode Register (channel = 0) */ 03552 #define REG_TC0_CV0 REG_ACCESS(RoReg, 0x40010010U) /* (TC0) Counter Value (channel = 0) */ 03553 #define REG_TC0_RA0 REG_ACCESS(RwReg, 0x40010014U) /* (TC0) Register A (channel = 0) */ 03554 #define REG_TC0_RB0 REG_ACCESS(RwReg, 0x40010018U) /* (TC0) Register B (channel = 0) */ 03555 #define REG_TC0_RC0 REG_ACCESS(RwReg, 0x4001001CU) /* (TC0) Register C (channel = 0) */ 03556 #define REG_TC0_SR0 REG_ACCESS(RoReg, 0x40010020U) /* (TC0) Status Register (channel = 0) */ 03557 #define REG_TC0_IER0 REG_ACCESS(WoReg, 0x40010024U) /* (TC0) Interrupt Enable Register (channel = 0) */ 03558 #define REG_TC0_IDR0 REG_ACCESS(WoReg, 0x40010028U) /* (TC0) Interrupt Disable Register (channel = 0) */ 03559 #define REG_TC0_IMR0 REG_ACCESS(RoReg, 0x4001002CU) /* (TC0) Interrupt Mask Register (channel = 0) */ 03560 #define REG_TC0_CCR1 REG_ACCESS(WoReg, 0x40010040U) /* (TC0) Channel Control Register (channel = 1) */ 03561 #define REG_TC0_CMR1 REG_ACCESS(RwReg, 0x40010044U) /* (TC0) Channel Mode Register (channel = 1) */ 03562 #define REG_TC0_SMMR1 REG_ACCESS(RwReg, 0x40010048U) /* (TC0) Stepper Motor Mode Register (channel = 1) */ 03563 #define REG_TC0_CV1 REG_ACCESS(RoReg, 0x40010050U) /* (TC0) Counter Value (channel = 1) */ 03564 #define REG_TC0_RA1 REG_ACCESS(RwReg, 0x40010054U) /* (TC0) Register A (channel = 1) */ 03565 #define REG_TC0_RB1 REG_ACCESS(RwReg, 0x40010058U) /* (TC0) Register B (channel = 1) */ 03566 #define REG_TC0_RC1 REG_ACCESS(RwReg, 0x4001005CU) /* (TC0) Register C (channel = 1) */ 03567 #define REG_TC0_SR1 REG_ACCESS(RoReg, 0x40010060U) /* (TC0) Status Register (channel = 1) */ 03568 #define REG_TC0_IER1 REG_ACCESS(WoReg, 0x40010064U) /* (TC0) Interrupt Enable Register (channel = 1) */ 03569 #define REG_TC0_IDR1 REG_ACCESS(WoReg, 0x40010068U) /* (TC0) Interrupt Disable Register (channel = 1) */ 03570 #define REG_TC0_IMR1 REG_ACCESS(RoReg, 0x4001006CU) /* (TC0) Interrupt Mask Register (channel = 1) */ 03571 #define REG_TC0_CCR2 REG_ACCESS(WoReg, 0x40010080U) /* (TC0) Channel Control Register (channel = 2) */ 03572 #define REG_TC0_CMR2 REG_ACCESS(RwReg, 0x40010084U) /* (TC0) Channel Mode Register (channel = 2) */ 03573 #define REG_TC0_SMMR2 REG_ACCESS(RwReg, 0x40010088U) /* (TC0) Stepper Motor Mode Register (channel = 2) */ 03574 #define REG_TC0_CV2 REG_ACCESS(RoReg, 0x40010090U) /* (TC0) Counter Value (channel = 2) */ 03575 #define REG_TC0_RA2 REG_ACCESS(RwReg, 0x40010094U) /* (TC0) Register A (channel = 2) */ 03576 #define REG_TC0_RB2 REG_ACCESS(RwReg, 0x40010098U) /* (TC0) Register B (channel = 2) */ 03577 #define REG_TC0_RC2 REG_ACCESS(RwReg, 0x4001009CU) /* (TC0) Register C (channel = 2) */ 03578 #define REG_TC0_SR2 REG_ACCESS(RoReg, 0x400100A0U) /* (TC0) Status Register (channel = 2) */ 03579 #define REG_TC0_IER2 REG_ACCESS(WoReg, 0x400100A4U) /* (TC0) Interrupt Enable Register (channel = 2) */ 03580 #define REG_TC0_IDR2 REG_ACCESS(WoReg, 0x400100A8U) /* (TC0) Interrupt Disable Register (channel = 2) */ 03581 #define REG_TC0_IMR2 REG_ACCESS(RoReg, 0x400100ACU) /* (TC0) Interrupt Mask Register (channel = 2) */ 03582 #define REG_TC0_BCR REG_ACCESS(WoReg, 0x400100C0U) /* (TC0) Block Control Register */ 03583 #define REG_TC0_BMR REG_ACCESS(RwReg, 0x400100C4U) /* (TC0) Block Mode Register */ 03584 #define REG_TC0_QIER REG_ACCESS(WoReg, 0x400100C8U) /* (TC0) QDEC Interrupt Enable Register */ 03585 #define REG_TC0_QIDR REG_ACCESS(WoReg, 0x400100CCU) /* (TC0) QDEC Interrupt Disable Register */ 03586 #define REG_TC0_QIMR REG_ACCESS(RoReg, 0x400100D0U) /* (TC0) QDEC Interrupt Mask Register */ 03587 #define REG_TC0_QISR REG_ACCESS(RoReg, 0x400100D4U) /* (TC0) QDEC Interrupt Status Register */ 03588 #define REG_TC0_WPMR REG_ACCESS(RwReg, 0x400100E4U) /* (TC0) Write Protect Mode Register */ 03589 /* ========== Register definition for TC1 peripheral ========== */ 03590 #define REG_TC1_CCR0 REG_ACCESS(WoReg, 0x40014000U) /* (TC1) Channel Control Register (channel = 0) */ 03591 #define REG_TC1_CMR0 REG_ACCESS(RwReg, 0x40014004U) /* (TC1) Channel Mode Register (channel = 0) */ 03592 #define REG_TC1_SMMR0 REG_ACCESS(RwReg, 0x40014008U) /* (TC1) Stepper Motor Mode Register (channel = 0) */ 03593 #define REG_TC1_CV0 REG_ACCESS(RoReg, 0x40014010U) /* (TC1) Counter Value (channel = 0) */ 03594 #define REG_TC1_RA0 REG_ACCESS(RwReg, 0x40014014U) /* (TC1) Register A (channel = 0) */ 03595 #define REG_TC1_RB0 REG_ACCESS(RwReg, 0x40014018U) /* (TC1) Register B (channel = 0) */ 03596 #define REG_TC1_RC0 REG_ACCESS(RwReg, 0x4001401CU) /* (TC1) Register C (channel = 0) */ 03597 #define REG_TC1_SR0 REG_ACCESS(RoReg, 0x40014020U) /* (TC1) Status Register (channel = 0) */ 03598 #define REG_TC1_IER0 REG_ACCESS(WoReg, 0x40014024U) /* (TC1) Interrupt Enable Register (channel = 0) */ 03599 #define REG_TC1_IDR0 REG_ACCESS(WoReg, 0x40014028U) /* (TC1) Interrupt Disable Register (channel = 0) */ 03600 #define REG_TC1_IMR0 REG_ACCESS(RoReg, 0x4001402CU) /* (TC1) Interrupt Mask Register (channel = 0) */ 03601 #define REG_TC1_CCR1 REG_ACCESS(WoReg, 0x40014040U) /* (TC1) Channel Control Register (channel = 1) */ 03602 #define REG_TC1_CMR1 REG_ACCESS(RwReg, 0x40014044U) /* (TC1) Channel Mode Register (channel = 1) */ 03603 #define REG_TC1_SMMR1 REG_ACCESS(RwReg, 0x40014048U) /* (TC1) Stepper Motor Mode Register (channel = 1) */ 03604 #define REG_TC1_CV1 REG_ACCESS(RoReg, 0x40014050U) /* (TC1) Counter Value (channel = 1) */ 03605 #define REG_TC1_RA1 REG_ACCESS(RwReg, 0x40014054U) /* (TC1) Register A (channel = 1) */ 03606 #define REG_TC1_RB1 REG_ACCESS(RwReg, 0x40014058U) /* (TC1) Register B (channel = 1) */ 03607 #define REG_TC1_RC1 REG_ACCESS(RwReg, 0x4001405CU) /* (TC1) Register C (channel = 1) */ 03608 #define REG_TC1_SR1 REG_ACCESS(RoReg, 0x40014060U) /* (TC1) Status Register (channel = 1) */ 03609 #define REG_TC1_IER1 REG_ACCESS(WoReg, 0x40014064U) /* (TC1) Interrupt Enable Register (channel = 1) */ 03610 #define REG_TC1_IDR1 REG_ACCESS(WoReg, 0x40014068U) /* (TC1) Interrupt Disable Register (channel = 1) */ 03611 #define REG_TC1_IMR1 REG_ACCESS(RoReg, 0x4001406CU) /* (TC1) Interrupt Mask Register (channel = 1) */ 03612 #define REG_TC1_CCR2 REG_ACCESS(WoReg, 0x40014080U) /* (TC1) Channel Control Register (channel = 2) */ 03613 #define REG_TC1_CMR2 REG_ACCESS(RwReg, 0x40014084U) /* (TC1) Channel Mode Register (channel = 2) */ 03614 #define REG_TC1_SMMR2 REG_ACCESS(RwReg, 0x40014088U) /* (TC1) Stepper Motor Mode Register (channel = 2) */ 03615 #define REG_TC1_CV2 REG_ACCESS(RoReg, 0x40014090U) /* (TC1) Counter Value (channel = 2) */ 03616 #define REG_TC1_RA2 REG_ACCESS(RwReg, 0x40014094U) /* (TC1) Register A (channel = 2) */ 03617 #define REG_TC1_RB2 REG_ACCESS(RwReg, 0x40014098U) /* (TC1) Register B (channel = 2) */ 03618 #define REG_TC1_RC2 REG_ACCESS(RwReg, 0x4001409CU) /* (TC1) Register C (channel = 2) */ 03619 #define REG_TC1_SR2 REG_ACCESS(RoReg, 0x400140A0U) /* (TC1) Status Register (channel = 2) */ 03620 #define REG_TC1_IER2 REG_ACCESS(WoReg, 0x400140A4U) /* (TC1) Interrupt Enable Register (channel = 2) */ 03621 #define REG_TC1_IDR2 REG_ACCESS(WoReg, 0x400140A8U) /* (TC1) Interrupt Disable Register (channel = 2) */ 03622 #define REG_TC1_IMR2 REG_ACCESS(RoReg, 0x400140ACU) /* (TC1) Interrupt Mask Register (channel = 2) */ 03623 #define REG_TC1_BCR REG_ACCESS(WoReg, 0x400140C0U) /* (TC1) Block Control Register */ 03624 #define REG_TC1_BMR REG_ACCESS(RwReg, 0x400140C4U) /* (TC1) Block Mode Register */ 03625 #define REG_TC1_QIER REG_ACCESS(WoReg, 0x400140C8U) /* (TC1) QDEC Interrupt Enable Register */ 03626 #define REG_TC1_QIDR REG_ACCESS(WoReg, 0x400140CCU) /* (TC1) QDEC Interrupt Disable Register */ 03627 #define REG_TC1_QIMR REG_ACCESS(RoReg, 0x400140D0U) /* (TC1) QDEC Interrupt Mask Register */ 03628 #define REG_TC1_QISR REG_ACCESS(RoReg, 0x400140D4U) /* (TC1) QDEC Interrupt Status Register */ 03629 #define REG_TC1_WPMR REG_ACCESS(RwReg, 0x400140E4U) /* (TC1) Write Protect Mode Register */ 03630 /* ========== Register definition for TWI0 peripheral ========== */ 03631 #define REG_TWI0_CR REG_ACCESS(WoReg, 0x40018000U) /* (TWI0) Control Register */ 03632 #define REG_TWI0_MMR REG_ACCESS(RwReg, 0x40018004U) /* (TWI0) Master Mode Register */ 03633 #define REG_TWI0_SMR REG_ACCESS(RwReg, 0x40018008U) /* (TWI0) Slave Mode Register */ 03634 #define REG_TWI0_IADR REG_ACCESS(RwReg, 0x4001800CU) /* (TWI0) Internal Address Register */ 03635 #define REG_TWI0_CWGR REG_ACCESS(RwReg, 0x40018010U) /* (TWI0) Clock Waveform Generator Register */ 03636 #define REG_TWI0_SR REG_ACCESS(RoReg, 0x40018020U) /* (TWI0) Status Register */ 03637 #define REG_TWI0_IER REG_ACCESS(WoReg, 0x40018024U) /* (TWI0) Interrupt Enable Register */ 03638 #define REG_TWI0_IDR REG_ACCESS(WoReg, 0x40018028U) /* (TWI0) Interrupt Disable Register */ 03639 #define REG_TWI0_IMR REG_ACCESS(RoReg, 0x4001802CU) /* (TWI0) Interrupt Mask Register */ 03640 #define REG_TWI0_RHR REG_ACCESS(RoReg, 0x40018030U) /* (TWI0) Receive Holding Register */ 03641 #define REG_TWI0_THR REG_ACCESS(WoReg, 0x40018034U) /* (TWI0) Transmit Holding Register */ 03642 #define REG_TWI0_RPR REG_ACCESS(RwReg, 0x40018100U) /* (TWI0) Receive Pointer Register */ 03643 #define REG_TWI0_RCR REG_ACCESS(RwReg, 0x40018104U) /* (TWI0) Receive Counter Register */ 03644 #define REG_TWI0_TPR REG_ACCESS(RwReg, 0x40018108U) /* (TWI0) Transmit Pointer Register */ 03645 #define REG_TWI0_TCR REG_ACCESS(RwReg, 0x4001810CU) /* (TWI0) Transmit Counter Register */ 03646 #define REG_TWI0_RNPR REG_ACCESS(RwReg, 0x40018110U) /* (TWI0) Receive Next Pointer Register */ 03647 #define REG_TWI0_RNCR REG_ACCESS(RwReg, 0x40018114U) /* (TWI0) Receive Next Counter Register */ 03648 #define REG_TWI0_TNPR REG_ACCESS(RwReg, 0x40018118U) /* (TWI0) Transmit Next Pointer Register */ 03649 #define REG_TWI0_TNCR REG_ACCESS(RwReg, 0x4001811CU) /* (TWI0) Transmit Next Counter Register */ 03650 #define REG_TWI0_PTCR REG_ACCESS(WoReg, 0x40018120U) /* (TWI0) Transfer Control Register */ 03651 #define REG_TWI0_PTSR REG_ACCESS(RoReg, 0x40018124U) /* (TWI0) Transfer Status Register */ 03652 /* ========== Register definition for TWI1 peripheral ========== */ 03653 #define REG_TWI1_CR REG_ACCESS(WoReg, 0x4001C000U) /* (TWI1) Control Register */ 03654 #define REG_TWI1_MMR REG_ACCESS(RwReg, 0x4001C004U) /* (TWI1) Master Mode Register */ 03655 #define REG_TWI1_SMR REG_ACCESS(RwReg, 0x4001C008U) /* (TWI1) Slave Mode Register */ 03656 #define REG_TWI1_IADR REG_ACCESS(RwReg, 0x4001C00CU) /* (TWI1) Internal Address Register */ 03657 #define REG_TWI1_CWGR REG_ACCESS(RwReg, 0x4001C010U) /* (TWI1) Clock Waveform Generator Register */ 03658 #define REG_TWI1_SR REG_ACCESS(RoReg, 0x4001C020U) /* (TWI1) Status Register */ 03659 #define REG_TWI1_IER REG_ACCESS(WoReg, 0x4001C024U) /* (TWI1) Interrupt Enable Register */ 03660 #define REG_TWI1_IDR REG_ACCESS(WoReg, 0x4001C028U) /* (TWI1) Interrupt Disable Register */ 03661 #define REG_TWI1_IMR REG_ACCESS(RoReg, 0x4001C02CU) /* (TWI1) Interrupt Mask Register */ 03662 #define REG_TWI1_RHR REG_ACCESS(RoReg, 0x4001C030U) /* (TWI1) Receive Holding Register */ 03663 #define REG_TWI1_THR REG_ACCESS(WoReg, 0x4001C034U) /* (TWI1) Transmit Holding Register */ 03664 /* ========== Register definition for PWM peripheral ========== */ 03665 #define REG_PWM_MR REG_ACCESS(RwReg, 0x40020000U) /* (PWM) PWM Mode Register */ 03666 #define REG_PWM_ENA REG_ACCESS(WoReg, 0x40020004U) /* (PWM) PWM Enable Register */ 03667 #define REG_PWM_DIS REG_ACCESS(WoReg, 0x40020008U) /* (PWM) PWM Disable Register */ 03668 #define REG_PWM_SR REG_ACCESS(RoReg, 0x4002000CU) /* (PWM) PWM Status Register */ 03669 #define REG_PWM_IER REG_ACCESS(WoReg, 0x40020010U) /* (PWM) PWM Interrupt Enable Register */ 03670 #define REG_PWM_IDR REG_ACCESS(WoReg, 0x40020014U) /* (PWM) PWM Interrupt Disable Register */ 03671 #define REG_PWM_IMR REG_ACCESS(RoReg, 0x40020018U) /* (PWM) PWM Interrupt Mask Register */ 03672 #define REG_PWM_ISR REG_ACCESS(RoReg, 0x4002001CU) /* (PWM) PWM Interrupt Status Register */ 03673 #define REG_PWM_CMR0 REG_ACCESS(RwReg, 0x40020200U) /* (PWM) PWM Channel Mode Register (ch_num = 0) */ 03674 #define REG_PWM_CDTY0 REG_ACCESS(RwReg, 0x40020204U) /* (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */ 03675 #define REG_PWM_CPRD0 REG_ACCESS(RwReg, 0x40020208U) /* (PWM) PWM Channel Period Register (ch_num = 0) */ 03676 #define REG_PWM_CCNT0 REG_ACCESS(RoReg, 0x4002020CU) /* (PWM) PWM Channel Counter Register (ch_num = 0) */ 03677 #define REG_PWM_CUPD0 REG_ACCESS(WoReg, 0x40020210U) /* (PWM) PWM Channel Update Register (ch_num = 0) */ 03678 #define REG_PWM_CMR1 REG_ACCESS(RwReg, 0x40020220U) /* (PWM) PWM Channel Mode Register (ch_num = 1) */ 03679 #define REG_PWM_CDTY1 REG_ACCESS(RwReg, 0x40020224U) /* (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */ 03680 #define REG_PWM_CPRD1 REG_ACCESS(RwReg, 0x40020228U) /* (PWM) PWM Channel Period Register (ch_num = 1) */ 03681 #define REG_PWM_CCNT1 REG_ACCESS(RoReg, 0x4002022CU) /* (PWM) PWM Channel Counter Register (ch_num = 1) */ 03682 #define REG_PWM_CUPD1 REG_ACCESS(WoReg, 0x40020230U) /* (PWM) PWM Channel Update Register (ch_num = 1) */ 03683 #define REG_PWM_CMR2 REG_ACCESS(RwReg, 0x40020240U) /* (PWM) PWM Channel Mode Register (ch_num = 2) */ 03684 #define REG_PWM_CDTY2 REG_ACCESS(RwReg, 0x40020244U) /* (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */ 03685 #define REG_PWM_CPRD2 REG_ACCESS(RwReg, 0x40020248U) /* (PWM) PWM Channel Period Register (ch_num = 2) */ 03686 #define REG_PWM_CCNT2 REG_ACCESS(RoReg, 0x4002024CU) /* (PWM) PWM Channel Counter Register (ch_num = 2) */ 03687 #define REG_PWM_CUPD2 REG_ACCESS(WoReg, 0x40020250U) /* (PWM) PWM Channel Update Register (ch_num = 2) */ 03688 #define REG_PWM_CMR3 REG_ACCESS(RwReg, 0x40020260U) /* (PWM) PWM Channel Mode Register (ch_num = 3) */ 03689 #define REG_PWM_CDTY3 REG_ACCESS(RwReg, 0x40020264U) /* (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */ 03690 #define REG_PWM_CPRD3 REG_ACCESS(RwReg, 0x40020268U) /* (PWM) PWM Channel Period Register (ch_num = 3) */ 03691 #define REG_PWM_CCNT3 REG_ACCESS(RoReg, 0x4002026CU) /* (PWM) PWM Channel Counter Register (ch_num = 3) */ 03692 #define REG_PWM_CUPD3 REG_ACCESS(WoReg, 0x40020270U) /* (PWM) PWM Channel Update Register (ch_num = 3) */ 03693 /* ========== Register definition for USART0 peripheral ========== */ 03694 #define REG_USART0_CR REG_ACCESS(WoReg, 0x40024000U) /* (USART0) Control Register */ 03695 #define REG_USART0_MR REG_ACCESS(RwReg, 0x40024004U) /* (USART0) Mode Register */ 03696 #define REG_USART0_IER REG_ACCESS(WoReg, 0x40024008U) /* (USART0) Interrupt Enable Register */ 03697 #define REG_USART0_IDR REG_ACCESS(WoReg, 0x4002400CU) /* (USART0) Interrupt Disable Register */ 03698 #define REG_USART0_IMR REG_ACCESS(RoReg, 0x40024010U) /* (USART0) Interrupt Mask Register */ 03699 #define REG_USART0_CSR REG_ACCESS(RoReg, 0x40024014U) /* (USART0) Channel Status Register */ 03700 #define REG_USART0_RHR REG_ACCESS(RoReg, 0x40024018U) /* (USART0) Receiver Holding Register */ 03701 #define REG_USART0_THR REG_ACCESS(WoReg, 0x4002401CU) /* (USART0) Transmitter Holding Register */ 03702 #define REG_USART0_BRGR REG_ACCESS(RwReg, 0x40024020U) /* (USART0) Baud Rate Generator Register */ 03703 #define REG_USART0_RTOR REG_ACCESS(RwReg, 0x40024024U) /* (USART0) Receiver Time-out Register */ 03704 #define REG_USART0_TTGR REG_ACCESS(RwReg, 0x40024028U) /* (USART0) Transmitter Timeguard Register */ 03705 #define REG_USART0_FIDI REG_ACCESS(RwReg, 0x40024040U) /* (USART0) FI DI Ratio Register */ 03706 #define REG_USART0_NER REG_ACCESS(RoReg, 0x40024044U) /* (USART0) Number of Errors Register */ 03707 #define REG_USART0_IF REG_ACCESS(RwReg, 0x4002404CU) /* (USART0) IrDA Filter Register */ 03708 #define REG_USART0_WPMR REG_ACCESS(RwReg, 0x400240E4U) /* (USART0) Write Protect Mode Register */ 03709 #define REG_USART0_WPSR REG_ACCESS(RoReg, 0x400240E8U) /* (USART0) Write Protect Status Register */ 03710 #define REG_USART0_RPR REG_ACCESS(RwReg, 0x40024100U) /* (USART0) Receive Pointer Register */ 03711 #define REG_USART0_RCR REG_ACCESS(RwReg, 0x40024104U) /* (USART0) Receive Counter Register */ 03712 #define REG_USART0_TPR REG_ACCESS(RwReg, 0x40024108U) /* (USART0) Transmit Pointer Register */ 03713 #define REG_USART0_TCR REG_ACCESS(RwReg, 0x4002410CU) /* (USART0) Transmit Counter Register */ 03714 #define REG_USART0_RNPR REG_ACCESS(RwReg, 0x40024110U) /* (USART0) Receive Next Pointer Register */ 03715 #define REG_USART0_RNCR REG_ACCESS(RwReg, 0x40024114U) /* (USART0) Receive Next Counter Register */ 03716 #define REG_USART0_TNPR REG_ACCESS(RwReg, 0x40024118U) /* (USART0) Transmit Next Pointer Register */ 03717 #define REG_USART0_TNCR REG_ACCESS(RwReg, 0x4002411CU) /* (USART0) Transmit Next Counter Register */ 03718 #define REG_USART0_PTCR REG_ACCESS(WoReg, 0x40024120U) /* (USART0) Transfer Control Register */ 03719 #define REG_USART0_PTSR REG_ACCESS(RoReg, 0x40024124U) /* (USART0) Transfer Status Register */ 03720 /* ========== Register definition for USART1 peripheral ========== */ 03721 #define REG_USART1_CR REG_ACCESS(WoReg, 0x40028000U) /* (USART1) Control Register */ 03722 #define REG_USART1_MR REG_ACCESS(RwReg, 0x40028004U) /* (USART1) Mode Register */ 03723 #define REG_USART1_IER REG_ACCESS(WoReg, 0x40028008U) /* (USART1) Interrupt Enable Register */ 03724 #define REG_USART1_IDR REG_ACCESS(WoReg, 0x4002800CU) /* (USART1) Interrupt Disable Register */ 03725 #define REG_USART1_IMR REG_ACCESS(RoReg, 0x40028010U) /* (USART1) Interrupt Mask Register */ 03726 #define REG_USART1_CSR REG_ACCESS(RoReg, 0x40028014U) /* (USART1) Channel Status Register */ 03727 #define REG_USART1_RHR REG_ACCESS(RoReg, 0x40028018U) /* (USART1) Receiver Holding Register */ 03728 #define REG_USART1_THR REG_ACCESS(WoReg, 0x4002801CU) /* (USART1) Transmitter Holding Register */ 03729 #define REG_USART1_BRGR REG_ACCESS(RwReg, 0x40028020U) /* (USART1) Baud Rate Generator Register */ 03730 #define REG_USART1_RTOR REG_ACCESS(RwReg, 0x40028024U) /* (USART1) Receiver Time-out Register */ 03731 #define REG_USART1_TTGR REG_ACCESS(RwReg, 0x40028028U) /* (USART1) Transmitter Timeguard Register */ 03732 #define REG_USART1_FIDI REG_ACCESS(RwReg, 0x40028040U) /* (USART1) FI DI Ratio Register */ 03733 #define REG_USART1_NER REG_ACCESS(RoReg, 0x40028044U) /* (USART1) Number of Errors Register */ 03734 #define REG_USART1_IF REG_ACCESS(RwReg, 0x4002804CU) /* (USART1) IrDA Filter Register */ 03735 #define REG_USART1_WPMR REG_ACCESS(RwReg, 0x400280E4U) /* (USART1) Write Protect Mode Register */ 03736 #define REG_USART1_WPSR REG_ACCESS(RoReg, 0x400280E8U) /* (USART1) Write Protect Status Register */ 03737 /* ========== Register definition for ADC peripheral ========== */ 03738 #define REG_ADC_CR REG_ACCESS(WoReg, 0x40038000U) /* (ADC) Control Register */ 03739 #define REG_ADC_MR REG_ACCESS(RwReg, 0x40038004U) /* (ADC) Mode Register */ 03740 #define REG_ADC_SEQR1 REG_ACCESS(RwReg, 0x40038008U) /* (ADC) Channel Sequence Register 1 */ 03741 #define REG_ADC_SEQR2 REG_ACCESS(RwReg, 0x4003800CU) /* (ADC) Channel Sequence Register 2 */ 03742 #define REG_ADC_CHER REG_ACCESS(WoReg, 0x40038010U) /* (ADC) Channel Enable Register */ 03743 #define REG_ADC_CHDR REG_ACCESS(WoReg, 0x40038014U) /* (ADC) Channel Disable Register */ 03744 #define REG_ADC_CHSR REG_ACCESS(RoReg, 0x40038018U) /* (ADC) Channel Status Register */ 03745 #define REG_ADC_LCDR REG_ACCESS(RoReg, 0x40038020U) /* (ADC) Last Converted Data Register */ 03746 #define REG_ADC_IER REG_ACCESS(WoReg, 0x40038024U) /* (ADC) Interrupt Enable Register */ 03747 #define REG_ADC_IDR REG_ACCESS(WoReg, 0x40038028U) /* (ADC) Interrupt Disable Register */ 03748 #define REG_ADC_IMR REG_ACCESS(RoReg, 0x4003802CU) /* (ADC) Interrupt Mask Register */ 03749 #define REG_ADC_ISR REG_ACCESS(RoReg, 0x40038030U) /* (ADC) Interrupt Status Register */ 03750 #define REG_ADC_OVER REG_ACCESS(RoReg, 0x4003803CU) /* (ADC) Overrun Status Register */ 03751 #define REG_ADC_EMR REG_ACCESS(RwReg, 0x40038040U) /* (ADC) Extended Mode Register */ 03752 #define REG_ADC_CWR REG_ACCESS(RwReg, 0x40038044U) /* (ADC) Compare Window Register */ 03753 #define REG_ADC_CDR REG_ACCESS(RoReg, 0x40038050U) /* (ADC) Channel Data Register */ 03754 #define REG_ADC_WPMR REG_ACCESS(RwReg, 0x400380E4U) /* (ADC) Write Protect Mode Register */ 03755 #define REG_ADC_WPSR REG_ACCESS(RoReg, 0x400380E8U) /* (ADC) Write Protect Status Register */ 03756 #define REG_ADC_RPR REG_ACCESS(RwReg, 0x40038100U) /* (ADC) Receive Pointer Register */ 03757 #define REG_ADC_RCR REG_ACCESS(RwReg, 0x40038104U) /* (ADC) Receive Counter Register */ 03758 #define REG_ADC_TPR REG_ACCESS(RwReg, 0x40038108U) /* (ADC) Transmit Pointer Register */ 03759 #define REG_ADC_TCR REG_ACCESS(RwReg, 0x4003810CU) /* (ADC) Transmit Counter Register */ 03760 #define REG_ADC_RNPR REG_ACCESS(RwReg, 0x40038110U) /* (ADC) Receive Next Pointer Register */ 03761 #define REG_ADC_RNCR REG_ACCESS(RwReg, 0x40038114U) /* (ADC) Receive Next Counter Register */ 03762 #define REG_ADC_TNPR REG_ACCESS(RwReg, 0x40038118U) /* (ADC) Transmit Next Pointer Register */ 03763 #define REG_ADC_TNCR REG_ACCESS(RwReg, 0x4003811CU) /* (ADC) Transmit Next Counter Register */ 03764 #define REG_ADC_PTCR REG_ACCESS(WoReg, 0x40038120U) /* (ADC) Transfer Control Register */ 03765 #define REG_ADC_PTSR REG_ACCESS(RoReg, 0x40038124U) /* (ADC) Transfer Status Register */ 03766 /* ========== Register definition for DACC peripheral ========== */ 03767 #define REG_DACC_CR REG_ACCESS(WoReg, 0x4003C000U) /* (DACC) Control Register */ 03768 #define REG_DACC_MR REG_ACCESS(RwReg, 0x4003C004U) /* (DACC) Mode Register */ 03769 #define REG_DACC_CDR REG_ACCESS(WoReg, 0x4003C008U) /* (DACC) Conversion Data Register */ 03770 #define REG_DACC_IER REG_ACCESS(WoReg, 0x4003C00CU) /* (DACC) Interrupt Enable Register */ 03771 #define REG_DACC_IDR REG_ACCESS(WoReg, 0x4003C010U) /* (DACC) Interrupt Disable Register */ 03772 #define REG_DACC_IMR REG_ACCESS(RoReg, 0x4003C014U) /* (DACC) Interrupt Mask Register */ 03773 #define REG_DACC_ISR REG_ACCESS(RoReg, 0x4003C018U) /* (DACC) Interrupt Status Register */ 03774 #define REG_DACC_WPMR REG_ACCESS(RwReg, 0x4003C0E4U) /* (DACC) Write Protect Mode Register */ 03775 #define REG_DACC_WPSR REG_ACCESS(RoReg, 0x4003C0E8U) /* (DACC) Write Protect Status Register */ 03776 #define REG_DACC_RPR REG_ACCESS(RwReg, 0x4003C100U) /* (DACC) Receive Pointer Register */ 03777 #define REG_DACC_RCR REG_ACCESS(RwReg, 0x4003C104U) /* (DACC) Receive Counter Register */ 03778 #define REG_DACC_TPR REG_ACCESS(RwReg, 0x4003C108U) /* (DACC) Transmit Pointer Register */ 03779 #define REG_DACC_TCR REG_ACCESS(RwReg, 0x4003C10CU) /* (DACC) Transmit Counter Register */ 03780 #define REG_DACC_RNPR REG_ACCESS(RwReg, 0x4003C110U) /* (DACC) Receive Next Pointer Register */ 03781 #define REG_DACC_RNCR REG_ACCESS(RwReg, 0x4003C114U) /* (DACC) Receive Next Counter Register */ 03782 #define REG_DACC_TNPR REG_ACCESS(RwReg, 0x4003C118U) /* (DACC) Transmit Next Pointer Register */ 03783 #define REG_DACC_TNCR REG_ACCESS(RwReg, 0x4003C11CU) /* (DACC) Transmit Next Counter Register */ 03784 #define REG_DACC_PTCR REG_ACCESS(WoReg, 0x4003C120U) /* (DACC) Transfer Control Register */ 03785 #define REG_DACC_PTSR REG_ACCESS(RoReg, 0x4003C124U) /* (DACC) Transfer Status Register */ 03786 /* ========== Register definition for MATRIX peripheral ========== */ 03787 #define REG_MATRIX_MCFG REG_ACCESS(RwReg, 0x400E0200U) /* (MATRIX) Master Configuration Register */ 03788 #define REG_MATRIX_SCFG REG_ACCESS(RwReg, 0x400E0240U) /* (MATRIX) Slave Configuration Register */ 03789 #define REG_MATRIX_PRAS0 REG_ACCESS(RwReg, 0x400E0280U) /* (MATRIX) Priority Register A for Slave 0 */ 03790 #define REG_MATRIX_PRAS1 REG_ACCESS(RwReg, 0x400E0288U) /* (MATRIX) Priority Register A for Slave 1 */ 03791 #define REG_MATRIX_PRAS2 REG_ACCESS(RwReg, 0x400E0290U) /* (MATRIX) Priority Register A for Slave 2 */ 03792 #define REG_MATRIX_PRAS3 REG_ACCESS(RwReg, 0x400E0298U) /* (MATRIX) Priority Register A for Slave 3 */ 03793 #define REG_MATRIX_SYSIO REG_ACCESS(RwReg, 0x400E0314U) /* (MATRIX) System I/O Configuration register */ 03794 #define REG_MATRIX_WPMR REG_ACCESS(RwReg, 0x400E03E4U) /* (MATRIX) Write Protect Mode Register */ 03795 #define REG_MATRIX_WPSR REG_ACCESS(RoReg, 0x400E03E8U) /* (MATRIX) Write Protect Status Register */ 03796 /* ========== Register definition for PMC peripheral ========== */ 03797 #define REG_PMC_SCER REG_ACCESS(WoReg, 0x400E0400U) /* (PMC) System Clock Enable Register */ 03798 #define REG_PMC_SCDR REG_ACCESS(WoReg, 0x400E0404U) /* (PMC) System Clock Disable Register */ 03799 #define REG_PMC_SCSR REG_ACCESS(RoReg, 0x400E0408U) /* (PMC) System Clock Status Register */ 03800 #define REG_PMC_PCER REG_ACCESS(WoReg, 0x400E0410U) /* (PMC) Peripheral Clock Enable Register */ 03801 #define REG_PMC_PCDR REG_ACCESS(WoReg, 0x400E0414U) /* (PMC) Peripheral Clock Disable Register */ 03802 #define REG_PMC_PCSR REG_ACCESS(RoReg, 0x400E0418U) /* (PMC) Peripheral Clock Status Register */ 03803 #define REG_PMC_MOR REG_ACCESS(RwReg, 0x400E0420U) /* (PMC) Main Oscillator Register */ 03804 #define REG_PMC_MCFR REG_ACCESS(RoReg, 0x400E0424U) /* (PMC) Main Clock Frequency Register */ 03805 #define REG_PMC_PLLR REG_ACCESS(RwReg, 0x400E0428U) /* (PMC) PLL Register */ 03806 #define REG_PMC_MCKR REG_ACCESS(RwReg, 0x400E0430U) /* (PMC) Master Clock Register */ 03807 #define REG_PMC_PCK REG_ACCESS(RwReg, 0x400E0440U) /* (PMC) Programmable Clock 0 Register */ 03808 #define REG_PMC_IER REG_ACCESS(WoReg, 0x400E0460U) /* (PMC) Interrupt Enable Register */ 03809 #define REG_PMC_IDR REG_ACCESS(WoReg, 0x400E0464U) /* (PMC) Interrupt Disable Register */ 03810 #define REG_PMC_SR REG_ACCESS(RoReg, 0x400E0468U) /* (PMC) Status Register */ 03811 #define REG_PMC_IMR REG_ACCESS(RoReg, 0x400E046CU) /* (PMC) Interrupt Mask Register */ 03812 #define REG_PMC_FSMR REG_ACCESS(RwReg, 0x400E0470U) /* (PMC) Fast Startup Mode Register */ 03813 #define REG_PMC_FSPR REG_ACCESS(RwReg, 0x400E0474U) /* (PMC) Fast Startup Polarity Register */ 03814 #define REG_PMC_FOCR REG_ACCESS(WoReg, 0x400E0478U) /* (PMC) Fault Output Clear Register */ 03815 #define REG_PMC_WPMR REG_ACCESS(RwReg, 0x400E04E4U) /* (PMC) Write Protect Mode Register */ 03816 #define REG_PMC_WPSR REG_ACCESS(RoReg, 0x400E04E8U) /* (PMC) Write Protect Status Register */ 03817 #define REG_PMC_OCR REG_ACCESS(RwReg, 0x400E0510U) /* (PMC) Oscillator Calibration Register */ 03818 /* ========== Register definition for UART0 peripheral ========== */ 03819 #define REG_UART0_CR REG_ACCESS(WoReg, 0x400E0600U) /* (UART0) Control Register */ 03820 #define REG_UART0_MR REG_ACCESS(RwReg, 0x400E0604U) /* (UART0) Mode Register */ 03821 #define REG_UART0_IER REG_ACCESS(WoReg, 0x400E0608U) /* (UART0) Interrupt Enable Register */ 03822 #define REG_UART0_IDR REG_ACCESS(WoReg, 0x400E060CU) /* (UART0) Interrupt Disable Register */ 03823 #define REG_UART0_IMR REG_ACCESS(RoReg, 0x400E0610U) /* (UART0) Interrupt Mask Register */ 03824 #define REG_UART0_SR REG_ACCESS(RoReg, 0x400E0614U) /* (UART0) Status Register */ 03825 #define REG_UART0_RHR REG_ACCESS(RoReg, 0x400E0618U) /* (UART0) Receive Holding Register */ 03826 #define REG_UART0_THR REG_ACCESS(WoReg, 0x400E061CU) /* (UART0) Transmit Holding Register */ 03827 #define REG_UART0_BRGR REG_ACCESS(RwReg, 0x400E0620U) /* (UART0) Baud Rate Generator Register */ 03828 #define REG_UART0_RPR REG_ACCESS(RwReg, 0x400E0700U) /* (UART0) Receive Pointer Register */ 03829 #define REG_UART0_RCR REG_ACCESS(RwReg, 0x400E0704U) /* (UART0) Receive Counter Register */ 03830 #define REG_UART0_TPR REG_ACCESS(RwReg, 0x400E0708U) /* (UART0) Transmit Pointer Register */ 03831 #define REG_UART0_TCR REG_ACCESS(RwReg, 0x400E070CU) /* (UART0) Transmit Counter Register */ 03832 #define REG_UART0_RNPR REG_ACCESS(RwReg, 0x400E0710U) /* (UART0) Receive Next Pointer Register */ 03833 #define REG_UART0_RNCR REG_ACCESS(RwReg, 0x400E0714U) /* (UART0) Receive Next Counter Register */ 03834 #define REG_UART0_TNPR REG_ACCESS(RwReg, 0x400E0718U) /* (UART0) Transmit Next Pointer Register */ 03835 #define REG_UART0_TNCR REG_ACCESS(RwReg, 0x400E071CU) /* (UART0) Transmit Next Counter Register */ 03836 #define REG_UART0_PTCR REG_ACCESS(WoReg, 0x400E0720U) /* (UART0) Transfer Control Register */ 03837 #define REG_UART0_PTSR REG_ACCESS(RoReg, 0x400E0724U) /* (UART0) Transfer Status Register */ 03838 /* ========== Register definition for CHIPID peripheral ========== */ 03839 #define REG_CHIPID_CIDR REG_ACCESS(RoReg, 0x400E0740U) /* (CHIPID) Chip ID Register */ 03840 #define REG_CHIPID_EXID REG_ACCESS(RoReg, 0x400E0744U) /* (CHIPID) Chip ID Extension Register */ 03841 /* ========== Register definition for UART1 peripheral ========== */ 03842 #define REG_UART1_CR REG_ACCESS(WoReg, 0x400E0800U) /* (UART1) Control Register */ 03843 #define REG_UART1_MR REG_ACCESS(RwReg, 0x400E0804U) /* (UART1) Mode Register */ 03844 #define REG_UART1_IER REG_ACCESS(WoReg, 0x400E0808U) /* (UART1) Interrupt Enable Register */ 03845 #define REG_UART1_IDR REG_ACCESS(WoReg, 0x400E080CU) /* (UART1) Interrupt Disable Register */ 03846 #define REG_UART1_IMR REG_ACCESS(RoReg, 0x400E0810U) /* (UART1) Interrupt Mask Register */ 03847 #define REG_UART1_SR REG_ACCESS(RoReg, 0x400E0814U) /* (UART1) Status Register */ 03848 #define REG_UART1_RHR REG_ACCESS(RoReg, 0x400E0818U) /* (UART1) Receive Holding Register */ 03849 #define REG_UART1_THR REG_ACCESS(WoReg, 0x400E081CU) /* (UART1) Transmit Holding Register */ 03850 #define REG_UART1_BRGR REG_ACCESS(RwReg, 0x400E0820U) /* (UART1) Baud Rate Generator Register */ 03851 /* ========== Register definition for EFC peripheral ========== */ 03852 #define REG_EFC_FMR REG_ACCESS(RwReg, 0x400E0A00U) /* (EFC) EEFC Flash Mode Register */ 03853 #define REG_EFC_FCR REG_ACCESS(WoReg, 0x400E0A04U) /* (EFC) EEFC Flash Command Register */ 03854 #define REG_EFC_FSR REG_ACCESS(RoReg, 0x400E0A08U) /* (EFC) EEFC Flash Status Register */ 03855 #define REG_EFC_FRR REG_ACCESS(RoReg, 0x400E0A0CU) /* (EFC) EEFC Flash Result Register */ 03856 /* ========== Register definition for PIOA peripheral ========== */ 03857 #define REG_PIOA_PER REG_ACCESS(WoReg, 0x400E0E00U) /* (PIOA) PIO Enable Register */ 03858 #define REG_PIOA_PDR REG_ACCESS(WoReg, 0x400E0E04U) /* (PIOA) PIO Disable Register */ 03859 #define REG_PIOA_PSR REG_ACCESS(RoReg, 0x400E0E08U) /* (PIOA) PIO Status Register */ 03860 #define REG_PIOA_OER REG_ACCESS(WoReg, 0x400E0E10U) /* (PIOA) Output Enable Register */ 03861 #define REG_PIOA_ODR REG_ACCESS(WoReg, 0x400E0E14U) /* (PIOA) Output Disable Register */ 03862 #define REG_PIOA_OSR REG_ACCESS(RoReg, 0x400E0E18U) /* (PIOA) Output Status Register */ 03863 #define REG_PIOA_IFER REG_ACCESS(WoReg, 0x400E0E20U) /* (PIOA) Glitch Input Filter Enable Register */ 03864 #define REG_PIOA_IFDR REG_ACCESS(WoReg, 0x400E0E24U) /* (PIOA) Glitch Input Filter Disable Register */ 03865 #define REG_PIOA_IFSR REG_ACCESS(RoReg, 0x400E0E28U) /* (PIOA) Glitch Input Filter Status Register */ 03866 #define REG_PIOA_SODR REG_ACCESS(WoReg, 0x400E0E30U) /* (PIOA) Set Output Data Register */ 03867 #define REG_PIOA_CODR REG_ACCESS(WoReg, 0x400E0E34U) /* (PIOA) Clear Output Data Register */ 03868 #define REG_PIOA_ODSR REG_ACCESS(RwReg, 0x400E0E38U) /* (PIOA) Output Data Status Register */ 03869 #define REG_PIOA_PDSR REG_ACCESS(RoReg, 0x400E0E3CU) /* (PIOA) Pin Data Status Register */ 03870 #define REG_PIOA_IER REG_ACCESS(WoReg, 0x400E0E40U) /* (PIOA) Interrupt Enable Register */ 03871 #define REG_PIOA_IDR REG_ACCESS(WoReg, 0x400E0E44U) /* (PIOA) Interrupt Disable Register */ 03872 #define REG_PIOA_IMR REG_ACCESS(RoReg, 0x400E0E48U) /* (PIOA) Interrupt Mask Register */ 03873 #define REG_PIOA_ISR REG_ACCESS(RoReg, 0x400E0E4CU) /* (PIOA) Interrupt Status Register */ 03874 #define REG_PIOA_MDER REG_ACCESS(WoReg, 0x400E0E50U) /* (PIOA) Multi-driver Enable Register */ 03875 #define REG_PIOA_MDDR REG_ACCESS(WoReg, 0x400E0E54U) /* (PIOA) Multi-driver Disable Register */ 03876 #define REG_PIOA_MDSR REG_ACCESS(RoReg, 0x400E0E58U) /* (PIOA) Multi-driver Status Register */ 03877 #define REG_PIOA_PUDR REG_ACCESS(WoReg, 0x400E0E60U) /* (PIOA) Pull-up Disable Register */ 03878 #define REG_PIOA_PUER REG_ACCESS(WoReg, 0x400E0E64U) /* (PIOA) Pull-up Enable Register */ 03879 #define REG_PIOA_PUSR REG_ACCESS(RoReg, 0x400E0E68U) /* (PIOA) Pad Pull-up Status Register */ 03880 #define REG_PIOA_ABCDSR REG_ACCESS(RwReg, 0x400E0E70U) /* (PIOA) Peripheral Select Register */ 03881 #define REG_PIOA_IFSCDR REG_ACCESS(WoReg, 0x400E0E80U) /* (PIOA) Input Filter Slow Clock Disable Register */ 03882 #define REG_PIOA_IFSCER REG_ACCESS(WoReg, 0x400E0E84U) /* (PIOA) Input Filter Slow Clock Enable Register */ 03883 #define REG_PIOA_IFSCSR REG_ACCESS(RoReg, 0x400E0E88U) /* (PIOA) Input Filter Slow Clock Status Register */ 03884 #define REG_PIOA_SCDR REG_ACCESS(RwReg, 0x400E0E8CU) /* (PIOA) Slow Clock Divider Debouncing Register */ 03885 #define REG_PIOA_PPDDR REG_ACCESS(WoReg, 0x400E0E90U) /* (PIOA) Pad Pull-down Disable Register */ 03886 #define REG_PIOA_PPDER REG_ACCESS(WoReg, 0x400E0E94U) /* (PIOA) Pad Pull-down Enable Register */ 03887 #define REG_PIOA_PPDSR REG_ACCESS(RoReg, 0x400E0E98U) /* (PIOA) Pad Pull-down Status Register */ 03888 #define REG_PIOA_OWER REG_ACCESS(WoReg, 0x400E0EA0U) /* (PIOA) Output Write Enable */ 03889 #define REG_PIOA_OWDR REG_ACCESS(WoReg, 0x400E0EA4U) /* (PIOA) Output Write Disable */ 03890 #define REG_PIOA_OWSR REG_ACCESS(RoReg, 0x400E0EA8U) /* (PIOA) Output Write Status Register */ 03891 #define REG_PIOA_AIMER REG_ACCESS(WoReg, 0x400E0EB0U) /* (PIOA) Additional Interrupt Modes Enable Register */ 03892 #define REG_PIOA_AIMDR REG_ACCESS(WoReg, 0x400E0EB4U) /* (PIOA) Additional Interrupt Modes Disables Register */ 03893 #define REG_PIOA_AIMMR REG_ACCESS(RoReg, 0x400E0EB8U) /* (PIOA) Additional Interrupt Modes Mask Register */ 03894 #define REG_PIOA_ESR REG_ACCESS(WoReg, 0x400E0EC0U) /* (PIOA) Edge Select Register */ 03895 #define REG_PIOA_LSR REG_ACCESS(WoReg, 0x400E0EC4U) /* (PIOA) Level Select Register */ 03896 #define REG_PIOA_ELSR REG_ACCESS(RoReg, 0x400E0EC8U) /* (PIOA) Edge/Level Status Register */ 03897 #define REG_PIOA_FELLSR REG_ACCESS(WoReg, 0x400E0ED0U) /* (PIOA) Falling Edge/Low Level Select Register */ 03898 #define REG_PIOA_REHLSR REG_ACCESS(WoReg, 0x400E0ED4U) /* (PIOA) Rising Edge/ High Level Select Register */ 03899 #define REG_PIOA_FRLHSR REG_ACCESS(RoReg, 0x400E0ED8U) /* (PIOA) Fall/Rise - Low/High Status Register */ 03900 #define REG_PIOA_LOCKSR REG_ACCESS(RoReg, 0x400E0EE0U) /* (PIOA) Lock Status */ 03901 #define REG_PIOA_WPMR REG_ACCESS(RwReg, 0x400E0EE4U) /* (PIOA) Write Protect Mode Register */ 03902 #define REG_PIOA_WPSR REG_ACCESS(RoReg, 0x400E0EE8U) /* (PIOA) Write Protect Status Register */ 03903 #define REG_PIOA_SCHMITT REG_ACCESS(RwReg, 0x400E0F00U) /* (PIOA) Schmitt Trigger Register */ 03904 /* ========== Register definition for PIOB peripheral ========== */ 03905 #define REG_PIOB_PER REG_ACCESS(WoReg, 0x400E1000U) /* (PIOB) PIO Enable Register */ 03906 #define REG_PIOB_PDR REG_ACCESS(WoReg, 0x400E1004U) /* (PIOB) PIO Disable Register */ 03907 #define REG_PIOB_PSR REG_ACCESS(RoReg, 0x400E1008U) /* (PIOB) PIO Status Register */ 03908 #define REG_PIOB_OER REG_ACCESS(WoReg, 0x400E1010U) /* (PIOB) Output Enable Register */ 03909 #define REG_PIOB_ODR REG_ACCESS(WoReg, 0x400E1014U) /* (PIOB) Output Disable Register */ 03910 #define REG_PIOB_OSR REG_ACCESS(RoReg, 0x400E1018U) /* (PIOB) Output Status Register */ 03911 #define REG_PIOB_IFER REG_ACCESS(WoReg, 0x400E1020U) /* (PIOB) Glitch Input Filter Enable Register */ 03912 #define REG_PIOB_IFDR REG_ACCESS(WoReg, 0x400E1024U) /* (PIOB) Glitch Input Filter Disable Register */ 03913 #define REG_PIOB_IFSR REG_ACCESS(RoReg, 0x400E1028U) /* (PIOB) Glitch Input Filter Status Register */ 03914 #define REG_PIOB_SODR REG_ACCESS(WoReg, 0x400E1030U) /* (PIOB) Set Output Data Register */ 03915 #define REG_PIOB_CODR REG_ACCESS(WoReg, 0x400E1034U) /* (PIOB) Clear Output Data Register */ 03916 #define REG_PIOB_ODSR REG_ACCESS(RwReg, 0x400E1038U) /* (PIOB) Output Data Status Register */ 03917 #define REG_PIOB_PDSR REG_ACCESS(RoReg, 0x400E103CU) /* (PIOB) Pin Data Status Register */ 03918 #define REG_PIOB_IER REG_ACCESS(WoReg, 0x400E1040U) /* (PIOB) Interrupt Enable Register */ 03919 #define REG_PIOB_IDR REG_ACCESS(WoReg, 0x400E1044U) /* (PIOB) Interrupt Disable Register */ 03920 #define REG_PIOB_IMR REG_ACCESS(RoReg, 0x400E1048U) /* (PIOB) Interrupt Mask Register */ 03921 #define REG_PIOB_ISR REG_ACCESS(RoReg, 0x400E104CU) /* (PIOB) Interrupt Status Register */ 03922 #define REG_PIOB_MDER REG_ACCESS(WoReg, 0x400E1050U) /* (PIOB) Multi-driver Enable Register */ 03923 #define REG_PIOB_MDDR REG_ACCESS(WoReg, 0x400E1054U) /* (PIOB) Multi-driver Disable Register */ 03924 #define REG_PIOB_MDSR REG_ACCESS(RoReg, 0x400E1058U) /* (PIOB) Multi-driver Status Register */ 03925 #define REG_PIOB_PUDR REG_ACCESS(WoReg, 0x400E1060U) /* (PIOB) Pull-up Disable Register */ 03926 #define REG_PIOB_PUER REG_ACCESS(WoReg, 0x400E1064U) /* (PIOB) Pull-up Enable Register */ 03927 #define REG_PIOB_PUSR REG_ACCESS(RoReg, 0x400E1068U) /* (PIOB) Pad Pull-up Status Register */ 03928 #define REG_PIOB_ABCDSR REG_ACCESS(RwReg, 0x400E1070U) /* (PIOB) Peripheral Select Register */ 03929 #define REG_PIOB_IFSCDR REG_ACCESS(WoReg, 0x400E1080U) /* (PIOB) Input Filter Slow Clock Disable Register */ 03930 #define REG_PIOB_IFSCER REG_ACCESS(WoReg, 0x400E1084U) /* (PIOB) Input Filter Slow Clock Enable Register */ 03931 #define REG_PIOB_IFSCSR REG_ACCESS(RoReg, 0x400E1088U) /* (PIOB) Input Filter Slow Clock Status Register */ 03932 #define REG_PIOB_SCDR REG_ACCESS(RwReg, 0x400E108CU) /* (PIOB) Slow Clock Divider Debouncing Register */ 03933 #define REG_PIOB_PPDDR REG_ACCESS(WoReg, 0x400E1090U) /* (PIOB) Pad Pull-down Disable Register */ 03934 #define REG_PIOB_PPDER REG_ACCESS(WoReg, 0x400E1094U) /* (PIOB) Pad Pull-down Enable Register */ 03935 #define REG_PIOB_PPDSR REG_ACCESS(RoReg, 0x400E1098U) /* (PIOB) Pad Pull-down Status Register */ 03936 #define REG_PIOB_OWER REG_ACCESS(WoReg, 0x400E10A0U) /* (PIOB) Output Write Enable */ 03937 #define REG_PIOB_OWDR REG_ACCESS(WoReg, 0x400E10A4U) /* (PIOB) Output Write Disable */ 03938 #define REG_PIOB_OWSR REG_ACCESS(RoReg, 0x400E10A8U) /* (PIOB) Output Write Status Register */ 03939 #define REG_PIOB_AIMER REG_ACCESS(WoReg, 0x400E10B0U) /* (PIOB) Additional Interrupt Modes Enable Register */ 03940 #define REG_PIOB_AIMDR REG_ACCESS(WoReg, 0x400E10B4U) /* (PIOB) Additional Interrupt Modes Disables Register */ 03941 #define REG_PIOB_AIMMR REG_ACCESS(RoReg, 0x400E10B8U) /* (PIOB) Additional Interrupt Modes Mask Register */ 03942 #define REG_PIOB_ESR REG_ACCESS(WoReg, 0x400E10C0U) /* (PIOB) Edge Select Register */ 03943 #define REG_PIOB_LSR REG_ACCESS(WoReg, 0x400E10C4U) /* (PIOB) Level Select Register */ 03944 #define REG_PIOB_ELSR REG_ACCESS(RoReg, 0x400E10C8U) /* (PIOB) Edge/Level Status Register */ 03945 #define REG_PIOB_FELLSR REG_ACCESS(WoReg, 0x400E10D0U) /* (PIOB) Falling Edge/Low Level Select Register */ 03946 #define REG_PIOB_REHLSR REG_ACCESS(WoReg, 0x400E10D4U) /* (PIOB) Rising Edge/ High Level Select Register */ 03947 #define REG_PIOB_FRLHSR REG_ACCESS(RoReg, 0x400E10D8U) /* (PIOB) Fall/Rise - Low/High Status Register */ 03948 #define REG_PIOB_LOCKSR REG_ACCESS(RoReg, 0x400E10E0U) /* (PIOB) Lock Status */ 03949 #define REG_PIOB_WPMR REG_ACCESS(RwReg, 0x400E10E4U) /* (PIOB) Write Protect Mode Register */ 03950 #define REG_PIOB_WPSR REG_ACCESS(RoReg, 0x400E10E8U) /* (PIOB) Write Protect Status Register */ 03951 #define REG_PIOB_SCHMITT REG_ACCESS(RwReg, 0x400E1100U) /* (PIOB) Schmitt Trigger Register */ 03952 /* ========== Register definition for PIOC peripheral ========== */ 03953 #define REG_PIOC_PER REG_ACCESS(WoReg, 0x400E1200U) /* (PIOC) PIO Enable Register */ 03954 #define REG_PIOC_PDR REG_ACCESS(WoReg, 0x400E1204U) /* (PIOC) PIO Disable Register */ 03955 #define REG_PIOC_PSR REG_ACCESS(RoReg, 0x400E1208U) /* (PIOC) PIO Status Register */ 03956 #define REG_PIOC_OER REG_ACCESS(WoReg, 0x400E1210U) /* (PIOC) Output Enable Register */ 03957 #define REG_PIOC_ODR REG_ACCESS(WoReg, 0x400E1214U) /* (PIOC) Output Disable Register */ 03958 #define REG_PIOC_OSR REG_ACCESS(RoReg, 0x400E1218U) /* (PIOC) Output Status Register */ 03959 #define REG_PIOC_IFER REG_ACCESS(WoReg, 0x400E1220U) /* (PIOC) Glitch Input Filter Enable Register */ 03960 #define REG_PIOC_IFDR REG_ACCESS(WoReg, 0x400E1224U) /* (PIOC) Glitch Input Filter Disable Register */ 03961 #define REG_PIOC_IFSR REG_ACCESS(RoReg, 0x400E1228U) /* (PIOC) Glitch Input Filter Status Register */ 03962 #define REG_PIOC_SODR REG_ACCESS(WoReg, 0x400E1230U) /* (PIOC) Set Output Data Register */ 03963 #define REG_PIOC_CODR REG_ACCESS(WoReg, 0x400E1234U) /* (PIOC) Clear Output Data Register */ 03964 #define REG_PIOC_ODSR REG_ACCESS(RwReg, 0x400E1238U) /* (PIOC) Output Data Status Register */ 03965 #define REG_PIOC_PDSR REG_ACCESS(RoReg, 0x400E123CU) /* (PIOC) Pin Data Status Register */ 03966 #define REG_PIOC_IER REG_ACCESS(WoReg, 0x400E1240U) /* (PIOC) Interrupt Enable Register */ 03967 #define REG_PIOC_IDR REG_ACCESS(WoReg, 0x400E1244U) /* (PIOC) Interrupt Disable Register */ 03968 #define REG_PIOC_IMR REG_ACCESS(RoReg, 0x400E1248U) /* (PIOC) Interrupt Mask Register */ 03969 #define REG_PIOC_ISR REG_ACCESS(RoReg, 0x400E124CU) /* (PIOC) Interrupt Status Register */ 03970 #define REG_PIOC_MDER REG_ACCESS(WoReg, 0x400E1250U) /* (PIOC) Multi-driver Enable Register */ 03971 #define REG_PIOC_MDDR REG_ACCESS(WoReg, 0x400E1254U) /* (PIOC) Multi-driver Disable Register */ 03972 #define REG_PIOC_MDSR REG_ACCESS(RoReg, 0x400E1258U) /* (PIOC) Multi-driver Status Register */ 03973 #define REG_PIOC_PUDR REG_ACCESS(WoReg, 0x400E1260U) /* (PIOC) Pull-up Disable Register */ 03974 #define REG_PIOC_PUER REG_ACCESS(WoReg, 0x400E1264U) /* (PIOC) Pull-up Enable Register */ 03975 #define REG_PIOC_PUSR REG_ACCESS(RoReg, 0x400E1268U) /* (PIOC) Pad Pull-up Status Register */ 03976 #define REG_PIOC_ABCDSR REG_ACCESS(RwReg, 0x400E1270U) /* (PIOC) Peripheral Select Register */ 03977 #define REG_PIOC_IFSCDR REG_ACCESS(WoReg, 0x400E1280U) /* (PIOC) Input Filter Slow Clock Disable Register */ 03978 #define REG_PIOC_IFSCER REG_ACCESS(WoReg, 0x400E1284U) /* (PIOC) Input Filter Slow Clock Enable Register */ 03979 #define REG_PIOC_IFSCSR REG_ACCESS(RoReg, 0x400E1288U) /* (PIOC) Input Filter Slow Clock Status Register */ 03980 #define REG_PIOC_SCDR REG_ACCESS(RwReg, 0x400E128CU) /* (PIOC) Slow Clock Divider Debouncing Register */ 03981 #define REG_PIOC_PPDDR REG_ACCESS(WoReg, 0x400E1290U) /* (PIOC) Pad Pull-down Disable Register */ 03982 #define REG_PIOC_PPDER REG_ACCESS(WoReg, 0x400E1294U) /* (PIOC) Pad Pull-down Enable Register */ 03983 #define REG_PIOC_PPDSR REG_ACCESS(RoReg, 0x400E1298U) /* (PIOC) Pad Pull-down Status Register */ 03984 #define REG_PIOC_OWER REG_ACCESS(WoReg, 0x400E12A0U) /* (PIOC) Output Write Enable */ 03985 #define REG_PIOC_OWDR REG_ACCESS(WoReg, 0x400E12A4U) /* (PIOC) Output Write Disable */ 03986 #define REG_PIOC_OWSR REG_ACCESS(RoReg, 0x400E12A8U) /* (PIOC) Output Write Status Register */ 03987 #define REG_PIOC_AIMER REG_ACCESS(WoReg, 0x400E12B0U) /* (PIOC) Additional Interrupt Modes Enable Register */ 03988 #define REG_PIOC_AIMDR REG_ACCESS(WoReg, 0x400E12B4U) /* (PIOC) Additional Interrupt Modes Disables Register */ 03989 #define REG_PIOC_AIMMR REG_ACCESS(RoReg, 0x400E12B8U) /* (PIOC) Additional Interrupt Modes Mask Register */ 03990 #define REG_PIOC_ESR REG_ACCESS(WoReg, 0x400E12C0U) /* (PIOC) Edge Select Register */ 03991 #define REG_PIOC_LSR REG_ACCESS(WoReg, 0x400E12C4U) /* (PIOC) Level Select Register */ 03992 #define REG_PIOC_ELSR REG_ACCESS(RoReg, 0x400E12C8U) /* (PIOC) Edge/Level Status Register */ 03993 #define REG_PIOC_FELLSR REG_ACCESS(WoReg, 0x400E12D0U) /* (PIOC) Falling Edge/Low Level Select Register */ 03994 #define REG_PIOC_REHLSR REG_ACCESS(WoReg, 0x400E12D4U) /* (PIOC) Rising Edge/ High Level Select Register */ 03995 #define REG_PIOC_FRLHSR REG_ACCESS(RoReg, 0x400E12D8U) /* (PIOC) Fall/Rise - Low/High Status Register */ 03996 #define REG_PIOC_LOCKSR REG_ACCESS(RoReg, 0x400E12E0U) /* (PIOC) Lock Status */ 03997 #define REG_PIOC_WPMR REG_ACCESS(RwReg, 0x400E12E4U) /* (PIOC) Write Protect Mode Register */ 03998 #define REG_PIOC_WPSR REG_ACCESS(RoReg, 0x400E12E8U) /* (PIOC) Write Protect Status Register */ 03999 #define REG_PIOC_SCHMITT REG_ACCESS(RwReg, 0x400E1300U) /* (PIOC) Schmitt Trigger Register */ 04000 /* ========== Register definition for RSTC peripheral ========== */ 04001 #define REG_RSTC_CR REG_ACCESS(WoReg, 0x400E1400U) /* (RSTC) Control Register */ 04002 #define REG_RSTC_SR REG_ACCESS(RoReg, 0x400E1404U) /* (RSTC) Status Register */ 04003 #define REG_RSTC_MR REG_ACCESS(RwReg, 0x400E1408U) /* (RSTC) Mode Register */ 04004 /* ========== Register definition for SUPC peripheral ========== */ 04005 #define REG_SUPC_CR REG_ACCESS(WoReg, 0x400E1410U) /* (SUPC) Supply Controller Control Register */ 04006 #define REG_SUPC_SMMR REG_ACCESS(RwReg, 0x400E1414U) /* (SUPC) Supply Controller Supply Monitor Mode Register */ 04007 #define REG_SUPC_MR REG_ACCESS(RwReg, 0x400E1418U) /* (SUPC) Supply Controller Mode Register */ 04008 #define REG_SUPC_WUMR REG_ACCESS(RwReg, 0x400E141CU) /* (SUPC) Supply Controller Wake Up Mode Register */ 04009 #define REG_SUPC_WUIR REG_ACCESS(RwReg, 0x400E1420U) /* (SUPC) Supply Controller Wake Up Inputs Register */ 04010 #define REG_SUPC_SR REG_ACCESS(RoReg, 0x400E1424U) /* (SUPC) Supply Controller Status Register */ 04011 /* ========== Register definition for RTT peripheral ========== */ 04012 #define REG_RTT_MR REG_ACCESS(RwReg, 0x400E1430U) /* (RTT) Mode Register */ 04013 #define REG_RTT_AR REG_ACCESS(RwReg, 0x400E1434U) /* (RTT) Alarm Register */ 04014 #define REG_RTT_VR REG_ACCESS(RoReg, 0x400E1438U) /* (RTT) Value Register */ 04015 #define REG_RTT_SR REG_ACCESS(RoReg, 0x400E143CU) /* (RTT) Status Register */ 04016 /* ========== Register definition for WDT peripheral ========== */ 04017 #define REG_WDT_CR REG_ACCESS(WoReg, 0x400E1450U) /* (WDT) Control Register */ 04018 #define REG_WDT_MR REG_ACCESS(RwReg, 0x400E1454U) /* (WDT) Mode Register */ 04019 #define REG_WDT_SR REG_ACCESS(RoReg, 0x400E1458U) /* (WDT) Status Register */ 04020 /* ========== Register definition for RTC peripheral ========== */ 04021 #define REG_RTC_CR REG_ACCESS(RwReg, 0x400E1460U) /* (RTC) Control Register */ 04022 #define REG_RTC_MR REG_ACCESS(RwReg, 0x400E1464U) /* (RTC) Mode Register */ 04023 #define REG_RTC_TIMR REG_ACCESS(RwReg, 0x400E1468U) /* (RTC) Time Register */ 04024 #define REG_RTC_CALR REG_ACCESS(RwReg, 0x400E146CU) /* (RTC) Calendar Register */ 04025 #define REG_RTC_TIMALR REG_ACCESS(RwReg, 0x400E1470U) /* (RTC) Time Alarm Register */ 04026 #define REG_RTC_CALALR REG_ACCESS(RwReg, 0x400E1474U) /* (RTC) Calendar Alarm Register */ 04027 #define REG_RTC_SR REG_ACCESS(RoReg, 0x400E1478U) /* (RTC) Status Register */ 04028 #define REG_RTC_SCCR REG_ACCESS(WoReg, 0x400E147CU) /* (RTC) Status Clear Command Register */ 04029 #define REG_RTC_IER REG_ACCESS(WoReg, 0x400E1480U) /* (RTC) Interrupt Enable Register */ 04030 #define REG_RTC_IDR REG_ACCESS(WoReg, 0x400E1484U) /* (RTC) Interrupt Disable Register */ 04031 #define REG_RTC_IMR REG_ACCESS(RoReg, 0x400E1488U) /* (RTC) Interrupt Mask Register */ 04032 #define REG_RTC_VER REG_ACCESS(RoReg, 0x400E148CU) /* (RTC) Valid Entry Register */ 04033 #define REG_RTC_WPMR REG_ACCESS(RwReg, 0x400E1544U) /* (RTC) Write Protect Mode Register */ 04034 /* ========== Register definition for GPBR peripheral ========== */ 04035 #define REG_GPBR_GPBR0 REG_ACCESS(RwReg, 0x400E1490U) /* (GPBR) General Purpose Backup Register 0 */ 04036 #define REG_GPBR_GPBR1 REG_ACCESS(RwReg, 0x400E1494U) /* (GPBR) General Purpose Backup Register 1 */ 04037 #define REG_GPBR_GPBR2 REG_ACCESS(RwReg, 0x400E1498U) /* (GPBR) General Purpose Backup Register 2 */ 04038 #define REG_GPBR_GPBR3 REG_ACCESS(RwReg, 0x400E149CU) /* (GPBR) General Purpose Backup Register 3 */ 04039 #define REG_GPBR_GPBR4 REG_ACCESS(RwReg, 0x400E14A0U) /* (GPBR) General Purpose Backup Register 4 */ 04040 #define REG_GPBR_GPBR5 REG_ACCESS(RwReg, 0x400E14A4U) /* (GPBR) General Purpose Backup Register 5 */ 04041 #define REG_GPBR_GPBR6 REG_ACCESS(RwReg, 0x400E14A8U) /* (GPBR) General Purpose Backup Register 6 */ 04042 #define REG_GPBR_GPBR7 REG_ACCESS(RwReg, 0x400E14ACU) /* (GPBR) General Purpose Backup Register 7 */ 04043 04044 /* ************************************************************************** */ 04045 /* PERIPHERAL ID DEFINITIONS FOR SAM3N */ 04046 /* ************************************************************************** */ 04047 04048 #define ID_SUPC ( 0) /* Supply Controller (SUPC) */ 04049 #define ID_RSTC ( 1) /* Reset Controller (RSTC) */ 04050 #define ID_RTC ( 2) /* Real Time Clock (RTC) */ 04051 #define ID_RTT ( 3) /* Real Time Timer (RTT) */ 04052 #define ID_WDT ( 4) /* Watchdog Timer (WDT) */ 04053 #define ID_PMC ( 5) /* Power Management Controller (PMC) */ 04054 #define ID_EFC ( 6) /* Enhanced Flash Controller (EFC) */ 04055 #define ID_UART0 ( 8) /* UART 0 (UART0) */ 04056 #define ID_UART1 ( 9) /* UART 1 (UART1) */ 04057 #define ID_PIOA (11) /* Parallel I/O Controller A (PIOA) */ 04058 #define ID_PIOB (12) /* Parallel I/O Controller B (PIOB) */ 04059 #define ID_PIOC (13) /* Parallel I/O Controller C (PIOC) */ 04060 #define ID_USART0 (14) /* USART 0 (USART0) */ 04061 #define ID_USART1 (15) /* USART 1 (USART1) */ 04062 #define ID_TWI0 (19) /* Two Wire Interface 0 (TWI0) */ 04063 #define ID_TWI1 (20) /* Two Wire Interface 1 (TWI1) */ 04064 #define ID_SPI (21) /* Serial Peripheral Interface (SPI) */ 04065 #define ID_TC0 (23) /* Timer/Counter 0 (TC0) */ 04066 #define ID_TC1 (24) /* Timer/Counter 1 (TC1) */ 04067 #define ID_TC2 (25) /* Timer/Counter 2 (TC2) */ 04068 #define ID_TC3 (26) /* Timer/Counter 3 (TC3) */ 04069 #define ID_TC4 (27) /* Timer/Counter 4 (TC4) */ 04070 #define ID_TC5 (28) /* Timer/Counter 5 (TC5) */ 04071 #define ID_ADC (29) /* Analog To Digital Converter (ADC) */ 04072 #define ID_DACC (30) /* Digital To Analog Converter (DACC) */ 04073 #define ID_PWM (31) /* Pulse Width Modulation (PWM) */ 04074 04075 /* ************************************************************************** */ 04076 /* BASE ADDRESS DEFINITIONS FOR SAM3N */ 04077 /* ************************************************************************** */ 04078 04079 #define SPI CAST(Spi , 0x40008000U) /* (SPI ) Base Address */ 04080 #define PDC_SPI CAST(Pdc , 0x40008100U) /* (PDC_SPI ) Base Address */ 04081 #define TC0 CAST(Tc , 0x40010000U) /* (TC0 ) Base Address */ 04082 #define TC1 CAST(Tc , 0x40014000U) /* (TC1 ) Base Address */ 04083 #define TWI0 CAST(Twi , 0x40018000U) /* (TWI0 ) Base Address */ 04084 #define PDC_TWI0 CAST(Pdc , 0x40018100U) /* (PDC_TWI0 ) Base Address */ 04085 #define TWI1 CAST(Twi , 0x4001C000U) /* (TWI1 ) Base Address */ 04086 #define PWM CAST(Pwm , 0x40020000U) /* (PWM ) Base Address */ 04087 #define USART0 CAST(Usart , 0x40024000U) /* (USART0 ) Base Address */ 04088 #define PDC_USART0 CAST(Pdc , 0x40024100U) /* (PDC_USART0) Base Address */ 04089 #define USART1 CAST(Usart , 0x40028000U) /* (USART1 ) Base Address */ 04090 #define ADC CAST(Adc , 0x40038000U) /* (ADC ) Base Address */ 04091 #define PDC_ADC CAST(Pdc , 0x40038100U) /* (PDC_ADC ) Base Address */ 04092 #define DACC CAST(Dacc , 0x4003C000U) /* (DACC ) Base Address */ 04093 #define PDC_DACC CAST(Pdc , 0x4003C100U) /* (PDC_DACC ) Base Address */ 04094 #define MATRIX CAST(Matrix , 0x400E0200U) /* (MATRIX ) Base Address */ 04095 #define PMC CAST(Pmc , 0x400E0400U) /* (PMC ) Base Address */ 04096 #define UART0 CAST(Uart , 0x400E0600U) /* (UART0 ) Base Address */ 04097 #define PDC_UART0 CAST(Pdc , 0x400E0700U) /* (PDC_UART0 ) Base Address */ 04098 #define CHIPID CAST(Chipid , 0x400E0740U) /* (CHIPID ) Base Address */ 04099 #define UART1 CAST(Uart , 0x400E0800U) /* (UART1 ) Base Address */ 04100 #define EFC CAST(Efc , 0x400E0A00U) /* (EFC ) Base Address */ 04101 #define PIOA CAST(Pio , 0x400E0E00U) /* (PIOA ) Base Address */ 04102 #define PIOB CAST(Pio , 0x400E1000U) /* (PIOB ) Base Address */ 04103 #define PIOC CAST(Pio , 0x400E1200U) /* (PIOC ) Base Address */ 04104 #define RSTC CAST(Rstc , 0x400E1400U) /* (RSTC ) Base Address */ 04105 #define SUPC CAST(Supc , 0x400E1410U) /* (SUPC ) Base Address */ 04106 #define RTT CAST(Rtt , 0x400E1430U) /* (RTT ) Base Address */ 04107 #define WDT CAST(Wdt , 0x400E1450U) /* (WDT ) Base Address */ 04108 #define RTC CAST(Rtc , 0x400E1460U) /* (RTC ) Base Address */ 04109 #define GPBR CAST(Gpbr , 0x400E1490U) /* (GPBR ) Base Address */ 04110 04111 /* ************************************************************************** */ 04112 /* PIO DEFINITIONS FOR SAM3N */ 04113 /* ************************************************************************** */ 04114 04115 #define PIO_PA0 (1u << 0) /* Pin Controlled by PA0 */ 04116 #define PIO_PA1 (1u << 1) /* Pin Controlled by PA1 */ 04117 #define PIO_PA2 (1u << 2) /* Pin Controlled by PA2 */ 04118 #define PIO_PA3 (1u << 3) /* Pin Controlled by PA3 */ 04119 #define PIO_PA4 (1u << 4) /* Pin Controlled by PA4 */ 04120 #define PIO_PA5 (1u << 5) /* Pin Controlled by PA5 */ 04121 #define PIO_PA6 (1u << 6) /* Pin Controlled by PA6 */ 04122 #define PIO_PA7 (1u << 7) /* Pin Controlled by PA7 */ 04123 #define PIO_PA8 (1u << 8) /* Pin Controlled by PA8 */ 04124 #define PIO_PA9 (1u << 9) /* Pin Controlled by PA9 */ 04125 #define PIO_PA10 (1u << 10) /* Pin Controlled by PA10 */ 04126 #define PIO_PA11 (1u << 11) /* Pin Controlled by PA11 */ 04127 #define PIO_PA12 (1u << 12) /* Pin Controlled by PA12 */ 04128 #define PIO_PA13 (1u << 13) /* Pin Controlled by PA13 */ 04129 #define PIO_PA14 (1u << 14) /* Pin Controlled by PA14 */ 04130 #define PIO_PA15 (1u << 15) /* Pin Controlled by PA15 */ 04131 #define PIO_PA16 (1u << 16) /* Pin Controlled by PA16 */ 04132 #define PIO_PA17 (1u << 17) /* Pin Controlled by PA17 */ 04133 #define PIO_PA18 (1u << 18) /* Pin Controlled by PA18 */ 04134 #define PIO_PA19 (1u << 19) /* Pin Controlled by PA19 */ 04135 #define PIO_PA20 (1u << 20) /* Pin Controlled by PA20 */ 04136 #define PIO_PA21 (1u << 21) /* Pin Controlled by PA21 */ 04137 #define PIO_PA22 (1u << 22) /* Pin Controlled by PA22 */ 04138 #define PIO_PA23 (1u << 23) /* Pin Controlled by PA23 */ 04139 #define PIO_PA24 (1u << 24) /* Pin Controlled by PA24 */ 04140 #define PIO_PA25 (1u << 25) /* Pin Controlled by PA25 */ 04141 #define PIO_PA26 (1u << 26) /* Pin Controlled by PA26 */ 04142 #define PIO_PA27 (1u << 27) /* Pin Controlled by PA27 */ 04143 #define PIO_PA28 (1u << 28) /* Pin Controlled by PA28 */ 04144 #define PIO_PA29 (1u << 29) /* Pin Controlled by PA29 */ 04145 #define PIO_PA30 (1u << 30) /* Pin Controlled by PA30 */ 04146 #define PIO_PA31 (1u << 31) /* Pin Controlled by PA31 */ 04147 #define PIO_PB0 (1u << 0) /* Pin Controlled by PB0 */ 04148 #define PIO_PB1 (1u << 1) /* Pin Controlled by PB1 */ 04149 #define PIO_PB2 (1u << 2) /* Pin Controlled by PB2 */ 04150 #define PIO_PB3 (1u << 3) /* Pin Controlled by PB3 */ 04151 #define PIO_PB4 (1u << 4) /* Pin Controlled by PB4 */ 04152 #define PIO_PB5 (1u << 5) /* Pin Controlled by PB5 */ 04153 #define PIO_PB6 (1u << 6) /* Pin Controlled by PB6 */ 04154 #define PIO_PB7 (1u << 7) /* Pin Controlled by PB7 */ 04155 #define PIO_PB8 (1u << 8) /* Pin Controlled by PB8 */ 04156 #define PIO_PB9 (1u << 9) /* Pin Controlled by PB9 */ 04157 #define PIO_PB10 (1u << 10) /* Pin Controlled by PB10 */ 04158 #define PIO_PB11 (1u << 11) /* Pin Controlled by PB11 */ 04159 #define PIO_PB12 (1u << 12) /* Pin Controlled by PB12 */ 04160 #define PIO_PB13 (1u << 13) /* Pin Controlled by PB13 */ 04161 #define PIO_PB14 (1u << 14) /* Pin Controlled by PB14 */ 04162 #define PIO_PC0 (1u << 0) /* Pin Controlled by PC0 */ 04163 #define PIO_PC1 (1u << 1) /* Pin Controlled by PC1 */ 04164 #define PIO_PC2 (1u << 2) /* Pin Controlled by PC2 */ 04165 #define PIO_PC3 (1u << 3) /* Pin Controlled by PC3 */ 04166 #define PIO_PC4 (1u << 4) /* Pin Controlled by PC4 */ 04167 #define PIO_PC5 (1u << 5) /* Pin Controlled by PC5 */ 04168 #define PIO_PC6 (1u << 6) /* Pin Controlled by PC6 */ 04169 #define PIO_PC7 (1u << 7) /* Pin Controlled by PC7 */ 04170 #define PIO_PC8 (1u << 8) /* Pin Controlled by PC8 */ 04171 #define PIO_PC9 (1u << 9) /* Pin Controlled by PC9 */ 04172 #define PIO_PC10 (1u << 10) /* Pin Controlled by PC10 */ 04173 #define PIO_PC11 (1u << 11) /* Pin Controlled by PC11 */ 04174 #define PIO_PC12 (1u << 12) /* Pin Controlled by PC12 */ 04175 #define PIO_PC13 (1u << 13) /* Pin Controlled by PC13 */ 04176 #define PIO_PC14 (1u << 14) /* Pin Controlled by PC14 */ 04177 #define PIO_PC15 (1u << 15) /* Pin Controlled by PC15 */ 04178 #define PIO_PC16 (1u << 16) /* Pin Controlled by PC16 */ 04179 #define PIO_PC17 (1u << 17) /* Pin Controlled by PC17 */ 04180 #define PIO_PC18 (1u << 18) /* Pin Controlled by PC18 */ 04181 #define PIO_PC19 (1u << 19) /* Pin Controlled by PC19 */ 04182 #define PIO_PC20 (1u << 20) /* Pin Controlled by PC20 */ 04183 #define PIO_PC21 (1u << 21) /* Pin Controlled by PC21 */ 04184 #define PIO_PC22 (1u << 22) /* Pin Controlled by PC22 */ 04185 #define PIO_PC23 (1u << 23) /* Pin Controlled by PC23 */ 04186 #define PIO_PC24 (1u << 24) /* Pin Controlled by PC24 */ 04187 #define PIO_PC25 (1u << 25) /* Pin Controlled by PC25 */ 04188 #define PIO_PC26 (1u << 26) /* Pin Controlled by PC26 */ 04189 #define PIO_PC27 (1u << 27) /* Pin Controlled by PC27 */ 04190 #define PIO_PC28 (1u << 28) /* Pin Controlled by PC28 */ 04191 #define PIO_PC29 (1u << 29) /* Pin Controlled by PC29 */ 04192 #define PIO_PC30 (1u << 30) /* Pin Controlled by PC30 */ 04193 #define PIO_PC31 (1u << 31) /* Pin Controlled by PC31 */ 04194 /* ========== Pio definition for SPI peripheral ========== */ 04195 #define PIO_PA12A_MISO (1u << 12) /* Spi signal: MISO */ 04196 #define PIO_PA13A_MOSI (1u << 13) /* Spi signal: MOSI */ 04197 #define PIO_PA11A_NPCS0 (1u << 11) /* Spi signal: NPCS0 */ 04198 #define PIO_PA9B_NPCS1 (1u << 9) /* Spi signal: NPCS1 */ 04199 #define PIO_PA31A_NPCS1 (1u << 31) /* Spi signal: NPCS1 */ 04200 #define PIO_PB14A_NPCS1 (1u << 14) /* Spi signal: NPCS1 */ 04201 #define PIO_PC4B_NPCS1 (1u << 4) /* Spi signal: NPCS1 */ 04202 #define PIO_PA10B_NPCS2 (1u << 10) /* Spi signal: NPCS2 */ 04203 #define PIO_PA30B_NPCS2 (1u << 30) /* Spi signal: NPCS2 */ 04204 #define PIO_PB2B_NPCS2 (1u << 2) /* Spi signal: NPCS2 */ 04205 #define PIO_PC7B_NPCS2 (1u << 7) /* Spi signal: NPCS2 */ 04206 #define PIO_PA3B_NPCS3 (1u << 3) /* Spi signal: NPCS3 */ 04207 #define PIO_PA5B_NPCS3 (1u << 5) /* Spi signal: NPCS3 */ 04208 #define PIO_PA22B_NPCS3 (1u << 22) /* Spi signal: NPCS3 */ 04209 #define PIO_PA14A_SPCK (1u << 14) /* Spi signal: SPCK */ 04210 /* ========== Pio definition for TC0 peripheral ========== */ 04211 #define PIO_PA4B_TCLK0 (1u << 4) /* Tc0 signal: TCLK0 */ 04212 #define PIO_PA28B_TCLK1 (1u << 28) /* Tc0 signal: TCLK1 */ 04213 #define PIO_PA29B_TCLK2 (1u << 29) /* Tc0 signal: TCLK2 */ 04214 #define PIO_PA0B_TIOA0 (1u << 0) /* Tc0 signal: TIOA0 */ 04215 #define PIO_PA15B_TIOA1 (1u << 15) /* Tc0 signal: TIOA1 */ 04216 #define PIO_PA26B_TIOA2 (1u << 26) /* Tc0 signal: TIOA2 */ 04217 #define PIO_PA1B_TIOB0 (1u << 1) /* Tc0 signal: TIOB0 */ 04218 #define PIO_PA16B_TIOB1 (1u << 16) /* Tc0 signal: TIOB1 */ 04219 #define PIO_PA27B_TIOB2 (1u << 27) /* Tc0 signal: TIOB2 */ 04220 /* ========== Pio definition for TC1 peripheral ========== */ 04221 #define PIO_PC25B_TCLK3 (1u << 25) /* Tc1 signal: TCLK3 */ 04222 #define PIO_PC28B_TCLK4 (1u << 28) /* Tc1 signal: TCLK4 */ 04223 #define PIO_PC31B_TCLK5 (1u << 31) /* Tc1 signal: TCLK5 */ 04224 #define PIO_PC23B_TIOA3 (1u << 23) /* Tc1 signal: TIOA3 */ 04225 #define PIO_PC26B_TIOA4 (1u << 26) /* Tc1 signal: TIOA4 */ 04226 #define PIO_PC29B_TIOA5 (1u << 29) /* Tc1 signal: TIOA5 */ 04227 #define PIO_PC24B_TIOB3 (1u << 24) /* Tc1 signal: TIOB3 */ 04228 #define PIO_PC27B_TIOB4 (1u << 27) /* Tc1 signal: TIOB4 */ 04229 #define PIO_PC30B_TIOB5 (1u << 30) /* Tc1 signal: TIOB5 */ 04230 /* ========== Pio definition for TWI0 peripheral ========== */ 04231 #define PIO_PA4A_TWCK0 (1u << 4) /* Twi0 signal: TWCK0 */ 04232 #define PIO_PA3A_TWD0 (1u << 3) /* Twi0 signal: TWD0 */ 04233 /* ========== Pio definition for TWI1 peripheral ========== */ 04234 #define PIO_PB5A_TWCK1 (1u << 5) /* Twi1 signal: TWCK1 */ 04235 #define PIO_PB4A_TWD1 (1u << 4) /* Twi1 signal: TWD1 */ 04236 /* ========== Pio definition for PWM peripheral ========== */ 04237 #define PIO_PA0A_PWM0 (1u << 0) /* Pwm signal: PWM0 */ 04238 #define PIO_PA11B_PWM0 (1u << 11) /* Pwm signal: PWM0 */ 04239 #define PIO_PA23B_PWM0 (1u << 23) /* Pwm signal: PWM0 */ 04240 #define PIO_PB0A_PWM0 (1u << 0) /* Pwm signal: PWM0 */ 04241 #define PIO_PC8B_PWM0 (1u << 8) /* Pwm signal: PWM0 */ 04242 #define PIO_PC18B_PWM0 (1u << 18) /* Pwm signal: PWM0 */ 04243 #define PIO_PC22B_PWM0 (1u << 22) /* Pwm signal: PWM0 */ 04244 #define PIO_PA1A_PWM1 (1u << 1) /* Pwm signal: PWM1 */ 04245 #define PIO_PA12B_PWM1 (1u << 12) /* Pwm signal: PWM1 */ 04246 #define PIO_PA24B_PWM1 (1u << 24) /* Pwm signal: PWM1 */ 04247 #define PIO_PB1A_PWM1 (1u << 1) /* Pwm signal: PWM1 */ 04248 #define PIO_PC9B_PWM1 (1u << 9) /* Pwm signal: PWM1 */ 04249 #define PIO_PC19B_PWM1 (1u << 19) /* Pwm signal: PWM1 */ 04250 #define PIO_PA2A_PWM2 (1u << 2) /* Pwm signal: PWM2 */ 04251 #define PIO_PA13B_PWM2 (1u << 13) /* Pwm signal: PWM2 */ 04252 #define PIO_PA25B_PWM2 (1u << 25) /* Pwm signal: PWM2 */ 04253 #define PIO_PB4B_PWM2 (1u << 4) /* Pwm signal: PWM2 */ 04254 #define PIO_PC10B_PWM2 (1u << 10) /* Pwm signal: PWM2 */ 04255 #define PIO_PC20B_PWM2 (1u << 20) /* Pwm signal: PWM2 */ 04256 #define PIO_PA7B_PWM3 (1u << 7) /* Pwm signal: PWM3 */ 04257 #define PIO_PA14B_PWM3 (1u << 14) /* Pwm signal: PWM3 */ 04258 #define PIO_PB14B_PWM3 (1u << 14) /* Pwm signal: PWM3 */ 04259 #define PIO_PC11B_PWM3 (1u << 11) /* Pwm signal: PWM3 */ 04260 #define PIO_PC21B_PWM3 (1u << 21) /* Pwm signal: PWM3 */ 04261 /* ========== Pio definition for USART0 peripheral ========== */ 04262 #define PIO_PA8A_CTS0 (1u << 8) /* Usart0 signal: CTS0 */ 04263 #define PIO_PA7A_RTS0 (1u << 7) /* Usart0 signal: RTS0 */ 04264 #define PIO_PA5A_RXD0 (1u << 5) /* Usart0 signal: RXD0 */ 04265 #define PIO_PA2B_SCK0 (1u << 2) /* Usart0 signal: SCK0 */ 04266 #define PIO_PA6A_TXD0 (1u << 6) /* Usart0 signal: TXD0 */ 04267 /* ========== Pio definition for USART1 peripheral ========== */ 04268 #define PIO_PA25A_CTS1 (1u << 25) /* Usart1 signal: CTS1 */ 04269 #define PIO_PA24A_RTS1 (1u << 24) /* Usart1 signal: RTS1 */ 04270 #define PIO_PA21A_RXD1 (1u << 21) /* Usart1 signal: RXD1 */ 04271 #define PIO_PA23A_SCK1 (1u << 23) /* Usart1 signal: SCK1 */ 04272 #define PIO_PA22A_TXD1 (1u << 22) /* Usart1 signal: TXD1 */ 04273 /* ========== Pio definition for ADC peripheral ========== */ 04274 #define PIO_PA17X1_AD0 (1u << 17) /* Adc signal: AD0 */ 04275 #define PIO_PA18X1_AD1 (1u << 18) /* Adc signal: AD1 */ 04276 #define PIO_PC13X1_AD10 (1u << 13) /* Adc signal: AD10 */ 04277 #define PIO_PC15X1_AD11 (1u << 15) /* Adc signal: AD11 */ 04278 #define PIO_PC12X1_AD12 (1u << 12) /* Adc signal: AD12 */ 04279 #define PIO_PC29X1_AD13 (1u << 29) /* Adc signal: AD13 */ 04280 #define PIO_PC30X1_AD14 (1u << 30) /* Adc signal: AD14 */ 04281 #define PIO_PC31X1_AD15 (1u << 31) /* Adc signal: AD15 */ 04282 #define PIO_PA19X1_AD2_WKUP9 (1u << 19) /* Adc signal: AD2/WKUP9 */ 04283 #define PIO_PA20X1_AD3_WKUP10 (1u << 20) /* Adc signal: AD3/WKUP10 */ 04284 #define PIO_PB0X1_AD4 (1u << 0) /* Adc signal: AD4 */ 04285 #define PIO_PB1X1_AD5 (1u << 1) /* Adc signal: AD5 */ 04286 #define PIO_PB2X1_AD6_WKUP12 (1u << 2) /* Adc signal: AD6/WKUP12 */ 04287 #define PIO_PB3X1_AD7 (1u << 3) /* Adc signal: AD7 */ 04288 #define PIO_PA21X1_AD8 (1u << 21) /* Adc signal: AD8 */ 04289 #define PIO_PA22X1_AD9 (1u << 22) /* Adc signal: AD9 */ 04290 #define PIO_PA8B_ADTRG (1u << 8) /* Adc signal: ADTRG */ 04291 /* ========== Pio definition for DACC peripheral ========== */ 04292 #define PIO_PB13X1_DAC0 (1u << 13) /* Dacc signal: DAC0 */ 04293 /* ========== Pio definition for PMC peripheral ========== */ 04294 #define PIO_PA6B_PCK0 (1u << 6) /* Pmc signal: PCK0 */ 04295 #define PIO_PB13B_PCK0 (1u << 13) /* Pmc signal: PCK0 */ 04296 #define PIO_PC16B_PCK0 (1u << 16) /* Pmc signal: PCK0 */ 04297 #define PIO_PA17B_PCK1 (1u << 17) /* Pmc signal: PCK1 */ 04298 #define PIO_PA21B_PCK1 (1u << 21) /* Pmc signal: PCK1 */ 04299 #define PIO_PC17B_PCK1 (1u << 17) /* Pmc signal: PCK1 */ 04300 #define PIO_PA18B_PCK2 (1u << 18) /* Pmc signal: PCK2 */ 04301 #define PIO_PA31B_PCK2 (1u << 31) /* Pmc signal: PCK2 */ 04302 #define PIO_PB3B_PCK2 (1u << 3) /* Pmc signal: PCK2 */ 04303 #define PIO_PC14B_PCK2 (1u << 14) /* Pmc signal: PCK2 */ 04304 /* ========== Pio definition for UART0 peripheral ========== */ 04305 #define PIO_PA9A_URXD0 (1u << 9) /* Uart0 signal: URXD0 */ 04306 #define PIO_PA10A_UTXD0 (1u << 10) /* Uart0 signal: UTXD0 */ 04307 /* ========== Pio definition for UART1 peripheral ========== */ 04308 #define PIO_PB2A_URXD1 (1u << 2) /* Uart1 signal: URXD1 */ 04309 #define PIO_PB3A_UTXD1 (1u << 3) /* Uart1 signal: UTXD1 */ 04310 04311 /* ************************************************************************** */ 04312 /* MEMORY MAPPING DEFINITIONS FOR SAM3N */ 04313 /* ************************************************************************** */ 04314 04315 #define IFLASH_ADDR (0x00400000u) /* Internal Flash base address */ 04316 #define IROM_ADDR (0x00800000u) /* Internal ROM base address */ 04317 #define IRAM_ADDR (0x20000000u) /* Internal RAM base address */ 04318 04319 #if CPU_CM3_SAM3N1 04320 #define IFLASH_SIZE 0x10000 04321 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ 04322 #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ 04323 #define IFLASH_NB_OF_PAGES (256) /* Internal FLASH 0 Number of Pages: 256 */ 04324 #define IFLASH_NB_OF_LOCK_BITS (4) /* Internal FLASH 0 Number of Lock Bits: 4 */ 04325 #define IRAM_SIZE 0x2000 04326 #elif CPU_CM3_SAM3N2 04327 #define IFLASH_SIZE 0x20000 04328 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ 04329 #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ 04330 #define IFLASH_NB_OF_PAGES (512) /* Internal FLASH 0 Number of Pages: 512 */ 04331 #define IFLASH_NB_OF_LOCK_BITS (8) /* Internal FLASH 0 Number of Lock Bits: 8 */ 04332 #define IRAM_SIZE 0x4000 04333 #elif CPU_CM3_SAM3N4 04334 #define IFLASH_SIZE 0x40000 04335 #define IFLASH_PAGE_SIZE (256) /* Internal FLASH 0 Page Size: 256 bytes */ 04336 #define IFLASH_LOCK_REGION_SIZE (16384) /* Internal FLASH 0 Lock Region Size: 16 Kbytes */ 04337 #define IFLASH_NB_OF_PAGES (1024) /* Internal FLASH 0 Number of Pages: 1024 */ 04338 #define IFLASH_NB_OF_LOCK_BITS (16) /* Internal FLASH 0 Number of Lock Bits: 16 */ 04339 #define IRAM_SIZE 0x6000 04340 #else 04341 #error Library does not support the specified device. 04342 #endif 04343 04344 #ifdef __cplusplus 04345 } 04346 #endif 04347 04348 04349 #endif /* SAM3N_H */