BeRTOS
sam3_smc.h
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00001 
00036 #ifndef SAM3_SMC_H
00037 #define SAM3_SMC_H
00038 
00039 /*
00040  * SMC registers defined only for SAM3X/A and U for now
00041  */
00042 #if CPU_CM3_SAM3X || CPU_CM3_SAM3U
00043 
00045 #define SMC_BASE  0x400E0000
00046 
00047 
00051 /*\{*/
00052 #define SMC_CFG_OFF         0x000  ///< NFC Configuration
00053 #define SMC_CTRL_OFF        0x004  ///< NFC Control
00054 #define SMC_SR_OFF          0x008  ///< NFC Status
00055 #define SMC_IER_OFF         0x00C  ///< NFC Interrupt Enable
00056 #define SMC_IDR_OFF         0x010  ///< NFC Interrupt Disable
00057 #define SMC_IMR_OFF         0x014  ///< NFC Interrupt Mask
00058 #define SMC_ADDR_OFF        0x018  ///< NFC Address Cycle Zero
00059 #define SMC_BANK_OFF        0x01C  ///< Bank Address
00060 #define SMC_ECC_CTRL_OFF    0x020  ///< ECC Control
00061 #define SMC_ECC_MD_OFF      0x024  ///< ECC Mode
00062 #define SMC_ECC_SR1_OFF     0x028  ///< ECC Status 1
00063 #define SMC_ECC_PR0_OFF     0x02C  ///< ECC Parity 0
00064 #define SMC_ECC_PR1_OFF     0x030  ///< ECC parity 1
00065 #define SMC_ECC_SR2_OFF     0x034  ///< ECC status 2
00066 #define SMC_ECC_PR2_OFF     0x038  ///< ECC parity 2
00067 #define SMC_ECC_PR3_OFF     0x03C  ///< ECC parity 3
00068 #define SMC_ECC_PR4_OFF     0x040  ///< ECC parity 4
00069 #define SMC_ECC_PR5_OFF     0x044  ///< ECC parity 5
00070 #define SMC_ECC_PR6_OFF     0x048  ///< ECC parity 6
00071 #define SMC_ECC_PR7_OFF     0x04C  ///< ECC parity 7
00072 #define SMC_ECC_PR8_OFF     0x050  ///< ECC parity 8
00073 #define SMC_ECC_PR9_OFF     0x054  ///< ECC parity 9
00074 #define SMC_ECC_PR10_OFF    0x058  ///< ECC parity 10
00075 #define SMC_ECC_PR11_OFF    0x05C  ///< ECC parity 11
00076 #define SMC_ECC_PR12_OFF    0x060  ///< ECC parity 12
00077 #define SMC_ECC_PR13_OFF    0x064  ///< ECC parity 13
00078 #define SMC_ECC_PR14_OFF    0x068  ///< ECC parity 14
00079 #define SMC_ECC_PR15_OFF    0x06C  ///< ECC parity 15
00080 #define SMC_SETUP0_OFF      0x070  ///< SETUP (CS_number = 0)
00081 #define SMC_PULSE0_OFF      0x074  ///< PULSE (CS_number = 0)
00082 #define SMC_CYCLE0_OFF      0x078  ///< CYCLE (CS_number = 0)
00083 #define SMC_TIMINGS0_OFF    0x07C  ///< TIMINGS (CS_number = 0)
00084 #define SMC_MODE0_OFF       0x080  ///< MODE (CS_number = 0)
00085 #define SMC_SETUP1_OFF      0x084  ///< SETUP (CS_number = 1)
00086 #define SMC_PULSE1_OFF      0x088  ///< PULSE (CS_number = 1)
00087 #define SMC_CYCLE1_OFF      0x08C  ///< CYCLE (CS_number = 1)
00088 #define SMC_TIMINGS1_OFF    0x090  ///< TIMINGS (CS_number = 1)
00089 #define SMC_MODE1_OFF       0x094  ///< MODE (CS_number = 1)
00090 #define SMC_SETUP2_OFF      0x098  ///< SETUP (CS_number = 2)
00091 #define SMC_PULSE2_OFF      0x09C  ///< PULSE (CS_number = 2)
00092 #define SMC_CYCLE2_OFF      0x0A0  ///< CYCLE (CS_number = 2)
00093 #define SMC_TIMINGS2_OFF    0x0A4  ///< TIMINGS (CS_number = 2)
00094 #define SMC_MODE2_OFF       0x0A8  ///< MODE (CS_number = 2)
00095 #define SMC_SETUP3_OFF      0x0AC  ///< SETUP (CS_number = 3)
00096 #define SMC_PULSE3_OFF      0x0B0  ///< PULSE (CS_number = 3)
00097 #define SMC_CYCLE3_OFF      0x0B4  ///< CYCLE (CS_number = 3)
00098 #define SMC_TIMINGS3_OFF    0x0B8  ///< TIMINGS (CS_number = 3)
00099 #define SMC_MODE3_OFF       0x0BC  ///< MODE (CS_number = 3)
00100 #define SMC_SETUP4_OFF      0x0C0  ///< SETUP (CS_number = 4)
00101 #define SMC_PULSE4_OFF      0x0C4  ///< PULSE (CS_number = 4)
00102 #define SMC_CYCLE4_OFF      0x0C8  ///< CYCLE (CS_number = 4)
00103 #define SMC_TIMINGS4_OFF    0x0CC  ///< TIMINGS (CS_number = 4)
00104 #define SMC_MODE4_OFF       0x0D0  ///< MODE (CS_number = 4)
00105 #define SMC_SETUP5_OFF      0x0D4  ///< SETUP (CS_number = 5)
00106 #define SMC_PULSE5_OFF      0x0D8  ///< PULSE (CS_number = 5)
00107 #define SMC_CYCLE5_OFF      0x0DC  ///< CYCLE (CS_number = 5)
00108 #define SMC_TIMINGS5_OFF    0x0E0  ///< TIMINGS (CS_number = 5)
00109 #define SMC_MODE5_OFF       0x0E4  ///< MODE (CS_number = 5)
00110 #define SMC_SETUP6_OFF      0x0E8  ///< SETUP (CS_number = 6)
00111 #define SMC_PULSE6_OFF      0x0EC  ///< PULSE (CS_number = 6)
00112 #define SMC_CYCLE6_OFF      0x0F0  ///< CYCLE (CS_number = 6)
00113 #define SMC_TIMINGS6_OFF    0x0F4  ///< TIMINGS (CS_number = 6)
00114 #define SMC_MODE6_OFF       0x0F8  ///< MODE (CS_number = 6)
00115 #define SMC_SETUP7_OFF      0x0FC  ///< SETUP (CS_number = 7)
00116 #define SMC_PULSE7_OFF      0x100  ///< PULSE (CS_number = 7)
00117 #define SMC_CYCLE7_OFF      0x104  ///< CYCLE (CS_number = 7)
00118 #define SMC_TIMINGS7_OFF    0x108  ///< TIMINGS (CS_number = 7)
00119 #define SMC_MODE7_OFF       0x10C  ///< MODE (CS_number = 7)
00120 #define SMC_OCMS_OFF        0x110  ///< OCMS MODE
00121 #define SMC_KEY1_OFF        0x114  ///< KEY1
00122 #define SMC_KEY2_OFF        0x118  ///< KEY2
00123 #define SMC_WPCR_OFF        0x1E4  ///< Write Protection Control
00124 #define SMC_WPSR_OFF        0x1E8  ///< Write Protection Status
00125 /*\}*/
00126 
00130 /*\{*/
00131 #define SMC_CFG        (*((reg32_t *)(SMC_BASE + SMC_CFG_OFF)))
00132 #define SMC_CTRL       (*((reg32_t *)(SMC_BASE + SMC_CTRL_OFF)))
00133 #define SMC_SR         (*((reg32_t *)(SMC_BASE + SMC_SR_OFF)))
00134 #define SMC_IER        (*((reg32_t *)(SMC_BASE + SMC_IER_OFF)))
00135 #define SMC_IDR        (*((reg32_t *)(SMC_BASE + SMC_IDR_OFF)))
00136 #define SMC_IMR        (*((reg32_t *)(SMC_BASE + SMC_IMR_OFF)))
00137 #define SMC_ADDR       (*((reg32_t *)(SMC_BASE + SMC_ADDR_OFF)))
00138 #define SMC_BANK       (*((reg32_t *)(SMC_BASE + SMC_BANK_OFF)))
00139 #define SMC_ECC_CTRL   (*((reg32_t *)(SMC_BASE + SMC_ECC_CTRL_OFF)))
00140 #define SMC_ECC_MD     (*((reg32_t *)(SMC_BASE + SMC_ECC_MD_OFF)))
00141 #define SMC_ECC_SR1    (*((reg32_t *)(SMC_BASE + SMC_ECC_SR1_OFF)))
00142 #define SMC_ECC_PR0    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR0_OFF)))
00143 #define SMC_ECC_PR1    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR1_OFF)))
00144 #define SMC_ECC_SR2    (*((reg32_t *)(SMC_BASE + SMC_ECC_SR2_OFF)))
00145 #define SMC_ECC_PR2    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR2_OFF)))
00146 #define SMC_ECC_PR3    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR3_OFF)))
00147 #define SMC_ECC_PR4    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR4_OFF)))
00148 #define SMC_ECC_PR5    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR5_OFF)))
00149 #define SMC_ECC_PR6    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR6_OFF)))
00150 #define SMC_ECC_PR7    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR7_OFF)))
00151 #define SMC_ECC_PR8    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR8_OFF)))
00152 #define SMC_ECC_PR9    (*((reg32_t *)(SMC_BASE + SMC_ECC_PR9_OFF)))
00153 #define SMC_ECC_PR10   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR10_OFF)))
00154 #define SMC_ECC_PR11   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR11_OFF)))
00155 #define SMC_ECC_PR12   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR12_OFF)))
00156 #define SMC_ECC_PR13   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR13_OFF)))
00157 #define SMC_ECC_PR14   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR14_OFF)))
00158 #define SMC_ECC_PR15   (*((reg32_t *)(SMC_BASE + SMC_ECC_PR15_OFF)))
00159 #define SMC_SETUP0     (*((reg32_t *)(SMC_BASE + SMC_SETUP0_OFF)))
00160 #define SMC_PULSE0     (*((reg32_t *)(SMC_BASE + SMC_PULSE0_OFF)))
00161 #define SMC_CYCLE0     (*((reg32_t *)(SMC_BASE + SMC_CYCLE0_OFF)))
00162 #define SMC_TIMINGS0   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS0_OFF)))
00163 #define SMC_MODE0      (*((reg32_t *)(SMC_BASE + SMC_MODE0_OFF)))
00164 #define SMC_SETUP1     (*((reg32_t *)(SMC_BASE + SMC_SETUP1_OFF)))
00165 #define SMC_PULSE1     (*((reg32_t *)(SMC_BASE + SMC_PULSE1_OFF)))
00166 #define SMC_CYCLE1     (*((reg32_t *)(SMC_BASE + SMC_CYCLE1_OFF)))
00167 #define SMC_TIMINGS1   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS1_OFF)))
00168 #define SMC_MODE1      (*((reg32_t *)(SMC_BASE + SMC_MODE1_OFF)))
00169 #define SMC_SETUP2     (*((reg32_t *)(SMC_BASE + SMC_SETUP2_OFF)))
00170 #define SMC_PULSE2     (*((reg32_t *)(SMC_BASE + SMC_PULSE2_OFF)))
00171 #define SMC_CYCLE2     (*((reg32_t *)(SMC_BASE + SMC_CYCLE2_OFF)))
00172 #define SMC_TIMINGS2   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS2_OFF)))
00173 #define SMC_MODE2      (*((reg32_t *)(SMC_BASE + SMC_MODE2_OFF)))
00174 #define SMC_SETUP3     (*((reg32_t *)(SMC_BASE + SMC_SETUP3_OFF)))
00175 #define SMC_PULSE3     (*((reg32_t *)(SMC_BASE + SMC_PULSE3_OFF)))
00176 #define SMC_CYCLE3     (*((reg32_t *)(SMC_BASE + SMC_CYCLE3_OFF)))
00177 #define SMC_TIMINGS3   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS3_OFF)))
00178 #define SMC_MODE3      (*((reg32_t *)(SMC_BASE + SMC_MODE3_OFF)))
00179 #define SMC_SETUP4     (*((reg32_t *)(SMC_BASE + SMC_SETUP4_OFF)))
00180 #define SMC_PULSE4     (*((reg32_t *)(SMC_BASE + SMC_PULSE4_OFF)))
00181 #define SMC_CYCLE4     (*((reg32_t *)(SMC_BASE + SMC_CYCLE4_OFF)))
00182 #define SMC_TIMINGS4   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS4_OFF)))
00183 #define SMC_MODE4      (*((reg32_t *)(SMC_BASE + SMC_MODE4_OFF)))
00184 #define SMC_SETUP5     (*((reg32_t *)(SMC_BASE + SMC_SETUP5_OFF)))
00185 #define SMC_PULSE5     (*((reg32_t *)(SMC_BASE + SMC_PULSE5_OFF)))
00186 #define SMC_CYCLE5     (*((reg32_t *)(SMC_BASE + SMC_CYCLE5_OFF)))
00187 #define SMC_TIMINGS5   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS5_OFF)))
00188 #define SMC_MODE5      (*((reg32_t *)(SMC_BASE + SMC_MODE5_OFF)))
00189 #define SMC_SETUP6     (*((reg32_t *)(SMC_BASE + SMC_SETUP6_OFF)))
00190 #define SMC_PULSE6     (*((reg32_t *)(SMC_BASE + SMC_PULSE6_OFF)))
00191 #define SMC_CYCLE6     (*((reg32_t *)(SMC_BASE + SMC_CYCLE6_OFF)))
00192 #define SMC_TIMINGS6   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS6_OFF)))
00193 #define SMC_MODE6      (*((reg32_t *)(SMC_BASE + SMC_MODE6_OFF)))
00194 #define SMC_SETUP7     (*((reg32_t *)(SMC_BASE + SMC_SETUP7_OFF)))
00195 #define SMC_PULSE7     (*((reg32_t *)(SMC_BASE + SMC_PULSE7_OFF)))
00196 #define SMC_CYCLE7     (*((reg32_t *)(SMC_BASE + SMC_CYCLE7_OFF)))
00197 #define SMC_TIMINGS7   (*((reg32_t *)(SMC_BASE + SMC_TIMINGS7_OFF)))
00198 #define SMC_MODE7      (*((reg32_t *)(SMC_BASE + SMC_MODE7_OFF)))
00199 #define SMC_OCMS       (*((reg32_t *)(SMC_BASE + SMC_OCMS_OFF)))
00200 #define SMC_KEY1       (*((reg32_t *)(SMC_BASE + SMC_KEY1_OFF)))
00201 #define SMC_KEY2       (*((reg32_t *)(SMC_BASE + SMC_KEY2_OFF)))
00202 #define SMC_WPCR       (*((reg32_t *)(SMC_BASE + SMC_WPCR_OFF)))
00203 #define SMC_WPSR       (*((reg32_t *)(SMC_BASE + SMC_WPSR_OFF)))
00204 /*\}*/
00205 
00209 /*\{*/
00210 #define NFC_SRAM_BASE_ADDR  0x20100000  ///< Base address of NFC SRAM
00211 #define NFC_CMD_BASE_ADDR   0x60000000  ///< Base address for NFC Address Command
00212 /*\}*/
00213 
00217 /*\{*/
00218 #define NFC_CMD_CMD1           (0xFF <<  2)  ///< Command Register Value for Cycle 1
00219 #define NFC_CMD_CMD2           (0xFF << 10)  ///< Command Register Value for Cycle 2
00220 #define NFC_CMD_VCMD2          BV(18)        ///< Valid Cycle 2 Command
00221 #define NFC_CMD_ACYCLE_MASK    (0x7 << 19)   ///< Number of Address required for the current command
00222 #define NFC_CMD_ACYCLE_NONE    (0x0 << 19)   ///< No address cycle
00223 #define NFC_CMD_ACYCLE_ONE     (0x1 << 19)   ///< One address cycle
00224 #define NFC_CMD_ACYCLE_TWO     (0x2 << 19)   ///< Two address cycles
00225 #define NFC_CMD_ACYCLE_THREE   (0x3 << 19)   ///< Three address cycles
00226 #define NFC_CMD_ACYCLE_FOUR    (0x4 << 19)   ///< Four address cycles
00227 #define NFC_CMD_ACYCLE_FIVE    (0x5 << 19)   ///< Five address cycles
00228 #define NFC_CMD_CSID_SHIFT     22            ///< Chip Select shift
00229 #define NFC_CMD_CSID_MASK      (0x7 << NFC_CMD_CSID_SHIFT)   ///< Chip Select mask
00230 #define NFC_CMD_NFCEN          BV(25)        ///< NFC Enable
00231 #define NFC_CMD_NFCWR          BV(26)        ///< NFC Write Enable
00232 #define NFC_CMD_NFCCMD         BV(27)        ///< NFC Command Enable
00233 /*\}*/
00234 
00235 
00239 /*\{*/
00240 #define SMC_CFG_PAGESIZE_SHIFT       0
00241 #define SMC_CFG_PAGESIZE_MASK        (0x3 << SMC_CFG_PAGESIZE_SHIFT)
00242 #define SMC_CFG_PAGESIZE_PS512_16    (0x0 << 0)
00243 #define SMC_CFG_PAGESIZE_PS1024_32   (0x1 << 0)
00244 #define SMC_CFG_PAGESIZE_PS2048_64   (0x2 << 0)
00245 #define SMC_CFG_PAGESIZE_PS4096_128  (0x3 << 0)
00246 #define SMC_CFG_WSPARE               (0x1 << 8)
00247 #define SMC_CFG_RSPARE               (0x1 << 9)
00248 #define SMC_CFG_EDGECTRL             (0x1 << 12)
00249 #define SMC_CFG_RBEDGE               (0x1 << 13)
00250 #define SMC_CFG_DTOCYC_SHIFT         16
00251 #define SMC_CFG_DTOCYC_MASK          (0xf << SMC_CFG_DTOCYC_SHIFT)
00252 #define SMC_CFG_DTOCYC(value)        (SMC_CFG_DTOCYC_MASK & ((value) << SMC_CFG_DTOCYC_SHIFT))
00253 #define SMC_CFG_DTOMUL_SHIFT         20
00254 #define SMC_CFG_DTOMUL_MASK          (0x7 << SMC_CFG_DTOMUL_SHIFT)
00255 #define SMC_CFG_DTOMUL_X1            (0x0 << 20)
00256 #define SMC_CFG_DTOMUL_X16           (0x1 << 20)
00257 #define SMC_CFG_DTOMUL_X128          (0x2 << 20)
00258 #define SMC_CFG_DTOMUL_X256          (0x3 << 20)
00259 #define SMC_CFG_DTOMUL_X1024         (0x4 << 20)
00260 #define SMC_CFG_DTOMUL_X4096         (0x5 << 20)
00261 #define SMC_CFG_DTOMUL_X65536        (0x6 << 20)
00262 #define SMC_CFG_DTOMUL_X1048576      (0x7 << 20)
00263 /*\}*/
00264 
00268 /*\{*/
00269 #define SMC_CTRL_NFCEN   BV(0)
00270 #define SMC_CTRL_NFCDIS  BV(1)
00271 /*\}*/
00272 
00276 /*\{*/
00277 #define SMC_SR_SMCSTS        BV(0)
00278 #define SMC_SR_RB_RISE       BV(4)
00279 #define SMC_SR_RB_FALL       BV(5)
00280 #define SMC_SR_NFCBUSY       BV(8)
00281 #define SMC_SR_NFCWR         BV(11)
00282 #define SMC_SR_NFCSID_SHIFT  12
00283 #define SMC_SR_NFCSID_MASK   (0x7 << SMC_SR_NFCSID_SHIFT)
00284 #define SMC_SR_XFRDONE       BV(16)
00285 #define SMC_SR_CMDDONE       BV(17)
00286 #define SMC_SR_DTOE          BV(20)
00287 #define SMC_SR_UNDEF         BV(21)
00288 #define SMC_SR_AWB           BV(22)
00289 #define SMC_SR_NFCASE        BV(23)
00290 #define SMC_SR_RB_EDGE0      BV(24)
00291 /*\}*/
00292 
00296 /*\{*/
00297 #define SMC_ECC_CTRL_RST    BV(0)
00298 #define SMC_ECC_CTRL_SWRST  BV(1)
00299 /*\}*/
00300 
00304 /*\{*/
00305 #define SMC_ECC_MD_ECC_PAGESIZE_SHIFT        0
00306 #define SMC_ECC_MD_ECC_PAGESIZE_MASK         0x3
00307 #define SMC_ECC_MD_ECC_PAGESIZE_PS512_16     0x0
00308 #define SMC_ECC_MD_ECC_PAGESIZE_PS1024_32    0x1
00309 #define SMC_ECC_MD_ECC_PAGESIZE_PS2048_64    0x2
00310 #define SMC_ECC_MD_ECC_PAGESIZE_PS4096_128   0x3
00311 #define SMC_ECC_MD_TYPCORREC_SHIFT           4
00312 #define SMC_ECC_MD_TYPCORREC_MASK            (0x3 << SMC_ECC_MD_TYPCORREC_SHIFT)
00313 #define SMC_ECC_MD_TYPCORREC_CPAGE           (0x0 << SMC_ECC_MD_TYPCORREC_SHIFT)
00314 #define SMC_ECC_MD_TYPCORREC_C256B           (0x1 << SMC_ECC_MD_TYPCORREC_SHIFT)
00315 #define SMC_ECC_MD_TYPCORREC_C512B           (0x2 << SMC_ECC_MD_TYPCORREC_SHIFT)
00316 /*\}*/
00317 
00321 /*\{*/
00322 #define SMC_SETUP_NWE_SETUP_MASK      0x3f
00323 #define SMC_SETUP_NWE_SETUP(x)        (SMC_SETUP_NWE_SETUP_MASK & (x))
00324 #define SMC_SETUP_NCS_WR_SETUP_SHIFT  8
00325 #define SMC_SETUP_NCS_WR_SETUP_MASK   (0x3f << SMC_SETUP_NCS_WR_SETUP_SHIFT)
00326 #define SMC_SETUP_NCS_WR_SETUP(x)     (SMC_SETUP_NCS_WR_SETUP_MASK & ((x) << SMC_SETUP_NCS_WR_SETUP_SHIFT))
00327 #define SMC_SETUP_NRD_SETUP_SHIFT     16
00328 #define SMC_SETUP_NRD_SETUP_MASK      (0x3f << SMC_SETUP_NRD_SETUP_SHIFT)
00329 #define SMC_SETUP_NRD_SETUP(x)        (SMC_SETUP_NRD_SETUP_MASK & ((x) << SMC_SETUP_NRD_SETUP_SHIFT))
00330 #define SMC_SETUP_NCS_RD_SETUP_SHIFT  24
00331 #define SMC_SETUP_NCS_RD_SETUP_MASK   (0x3f << SMC_SETUP_NCS_RD_SETUP_SHIFT)
00332 #define SMC_SETUP_NCS_RD_SETUP(x)     (SMC_SETUP_NCS_RD_SETUP_MASK & ((x) << SMC_SETUP_NCS_RD_SETUP_SHIFT))
00333 /*\}*/
00334 
00338 /*\{*/
00339 #define SMC_PULSE_NWE_PULSE_MASK      0x3f
00340 #define SMC_PULSE_NWE_PULSE(x)        (SMC_PULSE_NWE_PULSE_MASK & (x))
00341 #define SMC_PULSE_NCS_WR_PULSE_SHIFT  8
00342 #define SMC_PULSE_NCS_WR_PULSE_MASK   (0x3f << SMC_PULSE_NCS_WR_PULSE_SHIFT)
00343 #define SMC_PULSE_NCS_WR_PULSE(x)     (SMC_PULSE_NCS_WR_PULSE_MASK & ((x) << SMC_PULSE_NCS_WR_PULSE_SHIFT))
00344 #define SMC_PULSE_NRD_PULSE_SHIFT     16
00345 #define SMC_PULSE_NRD_PULSE_MASK      (0x3f << SMC_PULSE_NRD_PULSE_SHIFT)
00346 #define SMC_PULSE_NRD_PULSE(x)        (SMC_PULSE_NRD_PULSE_MASK & ((x) << SMC_PULSE_NRD_PULSE_SHIFT))
00347 #define SMC_PULSE_NCS_RD_PULSE_SHIFT  24
00348 #define SMC_PULSE_NCS_RD_PULSE_MASK   (0x3f << SMC_PULSE_NCS_RD_PULSE_SHIFT)
00349 #define SMC_PULSE_NCS_RD_PULSE(x)     (SMC_PULSE_NCS_RD_PULSE_MASK & ((x) << SMC_PULSE_NCS_RD_PULSE_SHIFT))
00350 /*\}*/
00351 
00355 /*\{*/
00356 #define SMC_CYCLE_NWE_CYCLE_MASK      0x1ff
00357 #define SMC_CYCLE_NWE_CYCLE(x)        (SMC_CYCLE_NWE_CYCLE_MASK & (x))
00358 #define SMC_CYCLE_NRD_CYCLE_SHIFT     16
00359 #define SMC_CYCLE_NRD_CYCLE_MASK      (0x1ff << SMC_CYCLE_NRD_CYCLE_SHIFT)
00360 #define SMC_CYCLE_NRD_CYCLE(x)        (SMC_CYCLE_NRD_CYCLE_MASK & ((x) << SMC_CYCLE_NRD_CYCLE_SHIFT))
00361 /*\}*/
00362 
00366 /*\{*/
00367 #define SMC_TIMINGS_TCLR_SHIFT     0
00368 #define SMC_TIMINGS_TCLR_MASK      (0xf << SMC_TIMINGS_TCLR_SHIFT)
00369 #define SMC_TIMINGS_TCLR(value)    (SMC_TIMINGS_TCLR_MASK & ((value) << SMC_TIMINGS_TCLR_SHIFT))
00370 #define SMC_TIMINGS_TADL_SHIFT     4
00371 #define SMC_TIMINGS_TADL_MASK      (0xf << SMC_TIMINGS_TADL_SHIFT)
00372 #define SMC_TIMINGS_TADL(value)    (SMC_TIMINGS_TADL_MASK & ((value) << SMC_TIMINGS_TADL_SHIFT))
00373 #define SMC_TIMINGS_TAR_SHIFT      8
00374 #define SMC_TIMINGS_TAR_MASK       (0xf << SMC_TIMINGS_TAR_SHIFT)
00375 #define SMC_TIMINGS_TAR(value)     (SMC_TIMINGS_TAR_MASK & ((value) << SMC_TIMINGS_TAR_SHIFT))
00376 #define SMC_TIMINGS_OCMS           BV(12)
00377 #define SMC_TIMINGS_TRR_SHIFT      16
00378 #define SMC_TIMINGS_TRR_MASK       (0xf << SMC_TIMINGS_TRR_SHIFT)
00379 #define SMC_TIMINGS_TRR(value)     (SMC_TIMINGS_TRR_MASK & ((value) << SMC_TIMINGS_TRR_SHIFT))
00380 #define SMC_TIMINGS_TWB_SHIFT      24
00381 #define SMC_TIMINGS_TWB_MASK       (0xf << SMC_TIMINGS_TWB_SHIFT)
00382 #define SMC_TIMINGS_TWB(value)     (SMC_TIMINGS_TWB_MASK & ((value) << SMC_TIMINGS_TWB_SHIFT))
00383 #define SMC_TIMINGS_RBNSEL_SHIFT   28
00384 #define SMC_TIMINGS_RBNSEL_MASK    (0x7 << SMC_TIMINGS_RBNSEL_SHIFT)
00385 #define SMC_TIMINGS_RBNSEL(value)  (SMC_TIMINGS_RBNSEL_MASK & ((value) << SMC_TIMINGS_RBNSEL_SHIFT))
00386 #define SMC_TIMINGS_NFSEL          BV(31)
00387 /*\}*/
00388 
00392 /*\{*/
00393 #define SMC_MODE_READ_MODE            BV(0)
00394 #define SMC_MODE_WRITE_MODE           BV(1)
00395 #define SMC_MODE_EXNW_MODE_SHIFT      4
00396 #define SMC_MODE_EXNW_MODE_MASK       (0x3 << SMC_MODE_EXNW_MODE_SHIFT)
00397 #define   SMC_MODE_EXNW_MODE_DISABLED (0x0 << SNC_MODE_EXNW_MODE_SHIFT)
00398 #define   SMC_MODE_EXNW_MODE_FROZEN   (0x2 << SNC_MODE_EXNW_MODE_SHIFT)
00399 #define   SMC_MODE_EXNW_MODE_READY    (0x3 << SNC_MODE_EXNW_MODE_SHIFT)
00400 #define SMC_MODE_BAT                  BV(8)
00401 #define SMC_MODE_DBW                  BV(12)
00402 #define SMC_MODE_TDF_CYCLES_SHIFT     16
00403 #define SMC_MODE_TDF_CYCLES_MASK      (0xf << SMC_MODE_TDF_CYCLES_SHIFT)
00404 #define SMC_MODE_TDF_CYCLES(x)        (SMC_MODE_TDF_CYCLES_MASK & ((x) << SMC_MODE_TDF_CYCLES_SHIFT))
00405 #define SMC_MODE_TDF_MODE             BV(20)
00406 /*\}*/
00407 
00408 #endif /* CPU_CM3_SAM3X || CPU_CM3_SAM3U */
00409 
00410 #endif /* SAM3_SMC_H */