BeRTOS
at91_ssc.h
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00001 
00040 /*
00041  * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 
00072 #ifndef AT91_SSC_H
00073 #define AT91_SSC_H
00074 
00075 #include <io/at91sam7.h>
00076 
00080 /*\{*/
00081 #define SSC_CR_OFF                  0x00000000  ///< Control register offset.
00082 
00083 #define SSC_RXEN                     0  ///< Receive enable.
00084 #define SSC_RXDIS                    1  ///< Receive disable.
00085 #define SSC_TXEN                     8  ///< Transmit enable.
00086 #define SSC_TXDIS                    9  ///< Transmit disable.
00087 #define SSC_SWRST                   15  ///< Software reset.
00088 /*\}*/
00089 
00093 /*\{*/
00094 #define SSC_CMR_OFF                 0x00000004  ///< Clock mode register offset.
00095 
00096 #define SSC_DIV_MASK                0x00000FFF  ///< Clock divider.
00097 /*\}*/
00098 
00102 /*\{*/
00103 #define SSC_RCMR_OFF                0x00000010  ///< Receive clock mode register offset.
00104 #define SSC_TCMR_OFF                0x00000018  ///< Transmit clock mode register offset.
00105 
00106 #define SSC_CKS_MASK                0x00000003  ///< Receive clock selection.
00107 #define SSC_CKS_DIV                 0x00000000  ///< Divided clock.
00108 #define SSC_CKS_CLK                 0x00000001  ///< RK/TK clock signal.
00109 #define SSC_CKS_PIN                 0x00000002  ///< TK/RK pin.
00110 #define SSC_CKO_MASK                0x0000001C  ///< Receive clock output mode selection.
00111 #define SSC_CKO_NONE                0x00000000  ///< None.
00112 #define SSC_CKO_CONT                0x00000004  ///< Continous receive clock.
00113 #define SSC_CKO_TRAN                0x00000008  ///< Receive clock only during data transfers.
00114 #define SSC_CKI                              5  ///< Receive clock inversion.
00115 #define SSC_CKG_MASK                0x000000C0  ///< Receive clock gating selection.
00116 #define SSC_CKG_NONE                0x00000000  ///< None, continous clock.
00117 #define SSC_CKG_FL                  0x00000040  ///< Continous receive clock.
00118 #define SSC_CKG_FH                  0x00000080  ///< Receive clock only during data transfers.
00119 #define SSC_START_MASK              0x00000F00  ///< Receive start selection.
00120 #define SSC_START_CONT              0x00000000  ///< Receive start as soon as enabled.
00121 #define SSC_START_TX                0x00000100  ///< Receive start on transmit start.
00122 #define SSC_START_RX                0x00000100  ///< Receive start on receive start.
00123 #define SSC_START_LOW_F             0x00000200  ///< Receive start on low level RF.
00124 #define SSC_START_HIGH_F            0x00000300  ///< Receive start on high level RF.
00125 #define SSC_START_FALL_F            0x00000400  ///< Receive start on falling edge RF.
00126 #define SSC_START_RISE_F            0x00000500  ///< Receive start on rising edge RF.
00127 #define SSC_START_LEVEL_F           0x00000600  ///< Receive start on any RF level change.
00128 #define SSC_START_EDGE_F            0x00000700  ///< Receive start on any RF edge.
00129 #define SSC_START_COMP0             0x00000800  ///< Receive on compare 0.
00130 #define SSC_STOP                            12  ///< Receive stop selection.
00131 #define SSC_STTDLY_MASK             0x00FF0000  ///< Receive start delay.
00132 #define SSC_STTDLY_SHIFT                    16  ///< Least significant bit of receive start delay.
00133 #define SSC_PERIOD_MASK             0xFF000000  ///< Receive period divider selection.
00134 #define SSC_PERIOD_SHIFT                    24  ///< Least significant bit of receive period divider selection.
00135 /*\}*/
00136 
00140 /*\{*/
00141 #define SSC_RFMR_OFF                0x00000014  ///< Receive frame mode register offset.
00142 #define SSC_TFMR_OFF                0x0000001C  ///< Transmit frame mode register offset.
00143 
00144 #define SSC_DATLEN_MASK             0x0000001F  ///< Data length.
00145 #define SSC_LOOP                             5  ///< Receiver loop mode.
00146 #define SSC_DATDEF                           5  ///< Transmit default value.
00147 
00148 #define SSC_MSBF                             7  ///< Most significant bit first.
00149 #define SSC_DATNB_MASK              0x00000F00  ///< Data number per frame.
00150 #define SSC_DATNB_SHIFT                      8  ///< Least significant bit of data number per frame.
00151 #define SSC_FSLEN_MASK              0x000F0000  ///< Receive frame sync. length.
00152 #define SSC_FSLEN_SHIFT                     16  ///< Least significant bit of receive frame sync. length.
00153 #define SSC_FSOS                    0x00700000  ///< Receive frame sync. output selection.
00154 #define SSC_FSOS_NONE               0x00000000  ///< No frame sync. Line set to input.
00155 #define SSC_FSOS_NEGATIVE           0x00100000  ///< Negative pulse.
00156 #define SSC_FSOS_POSITIVE           0x00200000  ///< Positive pulse.
00157 #define SSC_FSOS_LOW                0x00300000  ///< Low during transfer.
00158 #define SSC_FSOS_HIGH               0x00400000  ///< High during transfer.
00159 #define SSC_FSOS_TOGGLE             0x00500000  ///< Toggling at each start.
00160 #define SSC_FSDEN                           23  ///< Frame sync. data enable.
00161 #define SSC_FSEDGE                          24  ///< Frame sync. edge detection.
00162 /*\}*/
00163 
00167 /*\{*/
00168 #define SSC_RHR_OFF                 0x00000020  ///< Receive holding register offset.
00169 /*\}*/
00170 
00174 /*\{*/
00175 #define SSC_THR_OFF                 0x00000024  ///< Transmit holding register offset.
00176 /*\}*/
00177 
00181 /*\{*/
00182 #define SSC_RSHR_OFF                0x00000030  ///< Receive sync. holding register offset.
00183 /*\}*/
00184 
00188 /*\{*/
00189 #define SSC_TSHR_OFF                0x00000034  ///< Transmit sync. holding register offset.
00190 /*\}*/
00191 
00195 /*\{*/
00196 #define SSC_RC0R_OFF                0x00000038  ///< Receive compare 0 register offset.
00197 /*\}*/
00198 
00202 /*\{*/
00203 #define SSC_RC1R_OFF                0x0000003C  ///< Receive compare 1 register offset.
00204 /*\}*/
00205 
00209 /*\{*/
00210 #define SSC_SR_OFF                  0x00000040  ///< Status register offset.
00211 #define SSC_IER_OFF                 0x00000044  ///< Interrupt enable register offset.
00212 #define SSC_IDR_OFF                 0x00000048  ///< Interrupt disable register offset.
00213 #define SSC_IMR_OFF                 0x0000004C  ///< Interrupt mask register offset.
00214 
00215 #define SSC_TXRDY                            0  ///< Transmit ready.
00216 #define SSC_TXEMPTY                          1  ///< Transmit empty.
00217 #define SSC_ENDTX                            2  ///< End of transmission.
00218 #define SSC_TXBUFE                           3  ///< Transmit buffer empty.
00219 #define SSC_RXRDY                            4  ///< Receive ready.
00220 #define SSC_OVRUN                            5  ///< Receive overrun.
00221 #define SSC_ENDRX                            6  ///< End of receiption.
00222 #define SSC_RXBUFF                           7  ///< Receive buffer full.
00223 #define SSC_CP0                              8  ///< Compare 0.
00224 #define SSC_CP1                              9  ///< Compare 1.
00225 #define SSC_TXSYN                           10  ///< Transmit sync.
00226 #define SSC_RXSYN                           11  ///< Receive sync.
00227 #define SSC_TXENA                           16  ///< Transmit enable.
00228 #define SSC_RXENA                           17  ///< Receive enable.
00229 
00230 
00231 #if defined(SSC_BASE)
00232     #define SSC_CR      (*((reg32_t *)(SSC_BASE + SSC_CR_OFF)))     ///< Control register address.
00233     #define SSC_CMR     (*((reg32_t *)(SSC_BASE + SSC_CMR_OFF)))    ///< Clock mode register address.
00234     #define SSC_RCMR    (*((reg32_t *)(SSC_BASE + SSC_RCMR_OFF)))   ///< Receive clock mode register address.
00235     #define SSC_TCMR    (*((reg32_t *)(SSC_BASE + SSC_TCMR_OFF)))   ///< Transmit clock mode register address.
00236     #define SSC_RFMR    (*((reg32_t *)(SSC_BASE + SSC_RFMR_OFF)))   ///< Receive frame mode register address.
00237     #define SSC_TFMR    (*((reg32_t *)(SSC_BASE + SSC_TFMR_OFF)))   ///< Transmit frame mode register address.
00238     #define SSC_RHR     (*((reg32_t *)(SSC_BASE + SSC_RHR_OFF)))    ///< Receive holding register address.
00239     #define SSC_THR     (*((reg32_t *)(SSC_BASE + SSC_THR_OFF)))    ///< Transmit holding register address.
00240     #define SSC_RSHR    (*((reg32_t *)(SSC_BASE + SSC_RSHR_OFF)))   ///< Receive sync. holding register address.
00241     #define SSC_TSHR    (*((reg32_t *)(SSC_BASE + SSC_TSHR_OFF)))   ///< Transmit sync. holding register address.
00242     #define SSC_RC0R    (*((reg32_t *)(SSC_BASE + SSC_RC0R_OFF)))   ///< Receive compare 0 register address.
00243     #define SSC_RC1R    (*((reg32_t *)(SSC_BASE + SSC_RC1R_OFF)))   ///< Receive compare 1 register address.
00244     #define SSC_SR      (*((reg32_t *)(SSC_BASE + SSC_SR_OFF)))     ///< Status register address.
00245     #define SSC_IER     (*((reg32_t *)(SSC_BASE + SSC_IER_OFF)))    ///< Interrupt enable register address.
00246     #define SSC_IDR     (*((reg32_t *)(SSC_BASE + SSC_IDR_OFF)))    ///< Interrupt disable register address.
00247     #define SSC_IMR     (*((reg32_t *)(SSC_BASE + SSC_IMR_OFF)))    ///< Interrupt mask register address.
00248     #if defined(SSC_HAS_PDC)
00249         #define SSC_RPR    (*((reg32_t *)(SSC_BASE + PERIPH_RPR_OFF)))  ///< PDC receive pointer register address.
00250         #define SSC_RCR    (*((reg32_t *)(SSC_BASE + PERIPH_RCR_OFF)))  ///< PDC receive counter register address.
00251         #define SSC_TPR    (*((reg32_t *)(SSC_BASE + PERIPH_TPR_OFF)))  ///< PDC transmit pointer register address.
00252         #define SSC_TCR    (*((reg32_t *)(SSC_BASE + PERIPH_TCR_OFF)))  ///< PDC transmit counter register address.
00253         #define SSC_RNPR   (*((reg32_t *)(SSC_BASE + PERIPH_RNPR_OFF))) ///< PDC receive next pointer register address.
00254         #define SSC_RNCR   (*((reg32_t *)(SSC_BASE + PERIPH_RNCR_OFF))) ///< PDC receive next counter register address.
00255         #define SSC_TNPR   (*((reg32_t *)(SSC_BASE + PERIPH_TNPR_OFF))) ///< PDC transmit next pointer register address.
00256         #define SSC_TNCR   (*((reg32_t *)(SSC_BASE + PERIPH_TNCR_OFF))) ///< PDC transmit next counter register address.
00257         #define SSC_PTCR   (*((reg32_t *)(SSC_BASE + PERIPH_PTCR_OFF))) ///< PDC transfer control register address.
00258         #define SSC_PTSR   (*((reg32_t *)(SSC_BASE + PERIPH_PTSR_OFF))) ///< PDC transfer status register address.
00259     #endif /* SSC_HAS_PDC */
00260 
00261 #endif /* SSC_BASE */
00262 
00263 
00264 #endif /* AT91_SSC_H */