BeRTOS
dac.h
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00001 
00048 #ifndef DRV_DAC_H
00049 #define DRV_DAC_H
00050 
00051 #include <cfg/compiler.h>
00052 #include <cfg/debug.h>
00053 #include <cfg/macros.h>
00054 
00055 #include <cpu/attr.h>
00056 
00057 #include CPU_HEADER(dac)
00058 
00059 struct DacContext;
00060 struct Dac;
00061 
00062 typedef int (*DacWriteFunc_t) (struct Dac *dac, unsigned channel, uint16_t sample);
00063 typedef void (*SetChannelMaskFunc_t) (struct Dac *dac, uint32_t mask);
00064 typedef void (*SetSamplingRate_t) (struct Dac *dac, uint32_t rate);
00065 typedef void (*DmaConversionBufFunc_t) (struct Dac *dac, void *buf, size_t len);
00066 typedef bool (*DmaConversionIsFinished_t) (struct Dac *dac);
00067 typedef void (*DmaStartStreamingFunc_t) (struct Dac *dac, void *buf, size_t len, size_t slice_len);
00068 typedef void (*DmaStopFunc_t) (struct Dac *dac);
00069 typedef void (*DmaCallbackFunc_t) (struct Dac *dac);
00070 
00071 typedef struct DacContext
00072 {
00073     DacWriteFunc_t write;
00074     SetChannelMaskFunc_t setCh;
00075     SetSamplingRate_t setSampleRate;
00076     DmaConversionBufFunc_t conversion;
00077     DmaConversionIsFinished_t isFinished;
00078     DmaStartStreamingFunc_t start;
00079     DmaStopFunc_t stop;
00080     DmaCallbackFunc_t *callback;
00081     size_t slice_len;
00082 
00083     DB(id_t _type);
00084 
00085 } DacContext;
00086 
00087 typedef struct Dac
00088 {
00089     DacContext ctx;
00090     struct DacHardware *hw;
00091 } Dac;
00092 
00093 INLINE int dac_write(Dac *dac, unsigned channel, uint16_t sample)
00094 {
00095     ASSERT(dac->ctx.write);
00096     return dac->ctx.write(dac, channel, sample);
00097 }
00098 
00099 INLINE void dac_setChannelMask(struct Dac *dac, uint32_t mask)
00100 {
00101     ASSERT(dac->ctx.setCh);
00102     dac->ctx.setCh(dac, mask);
00103 }
00104 
00105 INLINE void dac_setSamplingRate(Dac *dac, uint32_t rate)
00106 {
00107     ASSERT(dac->ctx.setSampleRate);
00108     dac->ctx.setSampleRate(dac, rate);
00109 }
00110 
00111 /*
00112  * Convert \param len samples stored into \param buf.
00113  */
00114 INLINE void dac_dmaConversionBuffer(Dac *dac, void *buf, size_t len)
00115 {
00116     ASSERT(dac->ctx.conversion);
00117     dac->ctx.conversion(dac, buf, len);
00118 }
00119 
00120 /*
00121  * Check if a dma transfer is finished.
00122  *
00123  * Useful for kernel-less applications.
00124  */
00125 INLINE bool dac_dmaIsFinished(Dac *dac)
00126 {
00127     ASSERT(dac->ctx.isFinished);
00128     return dac->ctx.isFinished(dac);
00129 }
00130 
00131 /*
00132  * \param slicelen Must be a divisor of len, ie. len % slicelen == 0.
00133  */
00134 INLINE void dac_dmaStartStreaming(Dac *dac, void *buf, size_t len, size_t slice_len, DmaCallbackFunc_t *callback)
00135 {
00136     ASSERT(dac->ctx.start);
00137     ASSERT(len % slice_len == 0);
00138     ASSERT(callback);
00139 
00140     dac->ctx.callback = callback;
00141     dac->ctx.slice_len = slice_len;
00142     dac->ctx.start(dac, buf, len, slice_len);
00143 }
00144 
00145 INLINE void dac_dmaStop(Dac *dac)
00146 {
00147     ASSERT(dac->ctx.stop);
00148     dac->ctx.stop(dac);
00149 }
00150 
00151 #define dac_bits() DAC_BITS
00152 
00153 void dac_init(Dac *dac);
00154  //defgroup dac
00156 #endif /* DRV_DAC_H */