BeRTOS
at91_pmc.h File Reference

Go to the source code of this file.

Defines

#define PMC_SCER_OFF   0x00000000
 System Clock Enable, Disable and Status Register.
#define PMC_SCER   (*((reg32_t *)(PMC_BASE + PMC_SCER_OFF)))
 System clock enable register address.
#define PMC_SCDR_OFF   0x00000004
 System clock disable register offset.
#define PMC_SCDR   (*((reg32_t *)(PMC_BASE + PMC_SCDR_OFF)))
 System clock disable register address.
#define PMC_SCSR_OFF   0x00000008
 System clock status register offset.
#define PMC_SCSR   (*((reg32_t *)(PMC_BASE + PMC_SCSR_OFF)))
 System clock status register address.
#define PMC_PCK   0
 Processor clock.
#define PMC_UDP   7
 USB device port clock.
#define PMC_PCK0   8
 Programmable clock 0 output.
#define PMC_PCK1   9
 Programmable clock 1 output.
#define PMC_PCK2   10
 Programmable clock 2 output.
#define PMC_PCER_OFF   0x00000010
 Peripheral Clock Enable, Disable and Status Register.
#define PMC_PCER   (*((reg32_t *)(PMC_BASE + PMC_PCER_OFF)))
 Peripheral clock enable register address.
#define PMC_PCDR_OFF   0x00000014
 Peripheral clock disable register offset.
#define PMC_PCDR   (*((reg32_t *)(PMC_BASE + PMC_PCDR_OFF)))
 Peripheral clock disable register address.
#define PMC_PCSR_OFF   0x00000018
 Peripheral clock status register offset.
#define PMC_PCSR   (*((reg32_t *)(PMC_BASE + PMC_PCSR_OFF)))
 Peripheral clock status register address.
#define CKGR_MOR_OFF   0x00000020
 Clock Generator Main Oscillator Register.
#define CKGR_MOR   (*((reg32_t *)(PMC_BASE + CKGR_MOR_OFF)))
 Main oscillator register address.
#define CKGR_MOSCEN   0
 Main oscillator enable.
#define CKGR_OSCBYPASS   1
 Main oscillator bypass.
#define CKGR_OSCOUNT_MASK   0x0000FF00
 Main oscillator start-up time mask.
#define CKGR_OSCOUNT_SHIFT   8
 Main oscillator start-up time LSB.
#define CKGR_MCFR_OFF   0x00000024
 Clock Generator Main Clock Frequency Register.
#define CKGR_MCFR   (*((reg32_t *)(PMC_BASE + CKGR_MCFR_OFF)))
 Main clock frequency register address.
#define CKGR_MAINF_MASK   0x0000FFFF
 Main clock frequency mask mask.
#define CKGR_MAINRDY   16
 Main clock ready.
#define CKGR_PLLR_OFF   0x0000002C
 PLL Registers.
#define CKGR_PLLR   (*((reg32_t *)(PMC_BASE + CKGR_PLLR_OFF)))
 Clock generator PLL register address.
#define CKGR_DIV_MASK   0x000000FF
 Divider.
#define CKGR_DIV_SHIFT   0
 Least significant bit of the divider.
#define CKGR_DIV_0   0x00000000
 Divider output is 0.
#define CKGR_DIV_BYPASS   0x00000001
 Divider is bypassed.
#define CKGR_PLLCOUNT_MASK   0x00003F00
 PLL counter mask.
#define CKGR_PLLCOUNT_SHIFT   8
 PLL counter LSB.
#define CKGR_OUT_MASK   0x0000C000
 PLL output frequency range.
#define CKGR_OUT_0   0x00000000
 Please refer to the PLL datasheet.
#define CKGR_OUT_1   0x00004000
 Please refer to the PLL datasheet.
#define CKGR_OUT_2   0x00008000
 Please refer to the PLL datasheet.
#define CKGR_OUT_3   0x0000C000
 Please refer to the PLL datasheet.
#define CKGR_MUL_MASK   0x07FF0000
 PLL multiplier.
#define CKGR_MUL_SHIFT   16
 Least significant bit of the PLL multiplier.
#define CKGR_USBDIV_MASK   0x30000000
 Divider for USB clocks.
#define CKGR_USBDIV_1   0x00000000
 Divider output is PLL clock output.
#define CKGR_USBDIV_2   0x10000000
 Divider output is PLL clock output divided by 2.
#define CKGR_USBDIV_4   0x20000000
 Divider output is PLL clock output divided by 4.
#define PMC_MCKR_OFF   0x00000030
 Master Clock Register.
#define PMC_MCKR   (*((reg32_t *)(PMC_BASE + PMC_MCKR_OFF)))
 Master clock register address.
#define PMC_PCKR0_OFF   0x00000040
 Programmable clock 0 register offset.
#define PMC_PCKR0   (*((reg32_t *)(PMC_BASE + PMC_PCKR0_OFF)))
 Programmable clock 0 register address.
#define PMC_PCKR1_OFF   0x00000044
 Programmable clock 1 register offset.
#define PMC_PCKR1   (*((reg32_t *)(PMC_BASE + PMC_PCKR1_OFF)))
 Programmable clock 1 register address.
#define PMC_PCKR2_OFF   0x00000048
 Programmable clock 2 register offset.
#define PMC_PCKR2   (*((reg32_t *)(PMC_BASE + PMC_PCKR2_OFF)))
 Programmable clock 2 register address.
#define PMC_CSS_MASK   0x00000003
 Clock selection mask.
#define PMC_CSS_SLOW_CLK   0x00000000
 Slow clock selected.
#define PMC_CSS_MAIN_CLK   0x00000001
 Main clock selected.
#define PMC_CSS_PLL_CLK   0x00000003
 PLL clock selected.
#define PMC_PRES_MASK   0x0000001C
 Clock prescaler mask.
#define PMC_PRES_SHIFT   2
 Clock prescaler LSB.
#define PMC_PRES_CLK   0x00000000
 Selected clock, not divided.
#define PMC_PRES_CLK_2   0x00000004
 Selected clock divided by 2.
#define PMC_PRES_CLK_4   0x00000008
 Selected clock divided by 4.
#define PMC_PRES_CLK_8   0x0000000C
 Selected clock divided by 8.
#define PMC_PRES_CLK_16   0x00000010
 Selected clock divided by 16.
#define PMC_PRES_CLK_32   0x00000014
 Selected clock divided by 32.
#define PMC_PRES_CLK_64   0x00000018
 Selected clock divided by 64.
#define PMC_IER_OFF   0x00000060
 Power Management Status and Interrupt Registers.
#define PMC_IER   (*((reg32_t *)(PMC_BASE + PMC_IER_OFF)))
 Interrupt enable register address.
#define PMC_IDR_OFF   0x00000064
 Interrupt disable register offset.
#define PMC_IDR   (*((reg32_t *)(PMC_BASE + PMC_IDR_OFF)))
 Interrupt disable register address.
#define PMC_SR_OFF   0x00000068
 Status register offset.
#define PMC_SR   (*((reg32_t *)(PMC_BASE + PMC_SR_OFF)))
 Status register address.
#define PMC_IMR_OFF   0x0000006C
 Interrupt mask register offset.
#define PMC_IMR   (*((reg32_t *)(PMC_BASE + PMC_IMR_OFF)))
 Interrupt mask register address.
#define PMC_MOSCS   0
 Main oscillator.
#define PMC_LOCK   2
 PLL lock.
#define PMC_MCKRDY   3
 Master clock ready.
#define PMC_PCKRDY0   8
 Programmable clock 0 ready.
#define PMC_PCKRDY1   9
 Programmable clock 1 ready.
#define PMC_PCKRDY2   10
 Programmable clock 2 ready.

Detailed Description

Author:
Francesco Sacchi <batt@develer.com>

AT91 power management controller. This file is based on NUT/OS implementation. See license below.

Definition in file at91_pmc.h.


Define Documentation

#define CKGR_MCFR_OFF   0x00000024

Clock Generator Main Clock Frequency Register.

Main clock frequency register offset.

Definition at line 114 of file at91_pmc.h.

#define CKGR_MOR_OFF   0x00000020

Clock Generator Main Oscillator Register.

Main oscillator register offset.

Definition at line 103 of file at91_pmc.h.

#define CKGR_PLLR_OFF   0x0000002C

PLL Registers.

Clock generator PLL register offset.

Definition at line 123 of file at91_pmc.h.

#define PMC_IER_OFF   0x00000060

Power Management Status and Interrupt Registers.

Interrupt enable register offset.

Definition at line 177 of file at91_pmc.h.

#define PMC_MCKR_OFF   0x00000030

Master Clock Register.

Master clock register offset.

Definition at line 149 of file at91_pmc.h.

#define PMC_PCER_OFF   0x00000010

Peripheral Clock Enable, Disable and Status Register.

Peripheral clock enable register offset.

Definition at line 93 of file at91_pmc.h.

#define PMC_SCER_OFF   0x00000000

System Clock Enable, Disable and Status Register.

System clock enable register offset.

Definition at line 77 of file at91_pmc.h.