BeRTOS
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00001 00041 /* 00042 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved. 00043 * 00044 * Redistribution and use in source and binary forms, with or without 00045 * modification, are permitted provided that the following conditions 00046 * are met: 00047 * 00048 * 1. Redistributions of source code must retain the above copyright 00049 * notice, this list of conditions and the following disclaimer. 00050 * 2. Redistributions in binary form must reproduce the above copyright 00051 * notice, this list of conditions and the following disclaimer in the 00052 * documentation and/or other materials provided with the distribution. 00053 * 3. Neither the name of the copyright holders nor the names of 00054 * contributors may be used to endorse or promote products derived 00055 * from this software without specific prior written permission. 00056 * 00057 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00058 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00059 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00060 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00061 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00062 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00063 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00064 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00065 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00066 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00067 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00068 * SUCH DAMAGE. 00069 * 00070 * For additional information see http://www.ethernut.de/ 00071 00072 */ 00073 00074 #ifndef AT91_SPI_H 00075 #define AT91_SPI_H 00076 00080 /*\{*/ 00081 #define SPI_CR_OFF 0x00000000 ///< Control register offset. 00082 00083 #define SPI_SPIEN 0 ///< SPI enable. 00084 #define SPI_SPIDIS 1 ///< SPI disable. 00085 #define SPI_SWRST 7 ///< Software reset. 00086 #define SPI_LASTXFER 24 ///< Last transfer. 00087 /*\}*/ 00088 00092 /*\{*/ 00093 #define SPI_MR_OFF 0x00000004 ///< Mode register offset. 00094 00095 #define SPI_MSTR 0 ///< Master mode. 00096 #define SPI_PS 1 ///< Peripheral select. 00097 #define SPI_PCSDEC 2 ///< Chip select decode. 00098 #define SPI_FDIV 3 ///< Clock selection. 00099 #define SPI_MODFDIS 4 ///< Mode fault detection. 00100 #define SPI_LLB 7 ///< Local loopback enable. 00101 #define SPI_PCS 0x000F0000 ///< Peripheral chip select mask. 00102 #define SPI_PCS_0 0x000E0000 ///< Peripheral chip select 0. 00103 #define SPI_PCS_1 0x000D0000 ///< Peripheral chip select 1. 00104 #define SPI_PCS_2 0x000B0000 ///< Peripheral chip select 2. 00105 #define SPI_PCS_3 0x00070000 ///< Peripheral chip select 3. 00106 #define SPI_PCS_SHIFT 16 ///< Least significant bit of peripheral chip select. 00107 #define SPI_DLYBCS 0xFF000000 ///< Mask for delay between chip selects. 00108 #define SPI_DLYBCS_SHIFT 24 ///< Least significant bit of delay between chip selects. 00109 /*\}*/ 00110 00114 /*\{*/ 00115 #define SPI_RDR_OFF 0x00000008 ///< Receive data register offset. 00116 00117 #define SPI_RD 0x0000FFFF ///< Receive data mask. 00118 #define SPI_RD_SHIFT 0 ///< Least significant bit of receive data. 00119 /*\}*/ 00120 00124 /*\{*/ 00125 #define SPI_TDR_OFF 0x0000000C ///< Transmit data register offset. 00126 00127 #define SPI_TD 0x0000FFFF ///< Transmit data mask. 00128 #define SPI_TD_SHIFT 0 ///< Least significant bit of transmit data. 00129 /*\}*/ 00130 00134 /*\{*/ 00135 #define SPI_SR_OFF 0x00000010 ///< Status register offset. 00136 #define SPI_IER_OFF 0x00000014 ///< Interrupt enable register offset. 00137 #define SPI_IDR_OFF 0x00000018 ///< Interrupt disable register offset. 00138 #define SPI_IMR_OFF 0x0000001C ///< Interrupt mask register offset. 00139 00140 #define SPI_RDRF 0 ///< Receive data register full. 00141 #define SPI_TDRE 1 ///< Transmit data register empty. 00142 #define SPI_MODF 2 ///< Mode fault error. 00143 #define SPI_OVRES 3 ///< Overrun error status. 00144 #define SPI_ENDRX 4 ///< End of RX buffer. 00145 #define SPI_ENDTX 5 ///< End of TX buffer. 00146 #define SPI_RXBUFF 6 ///< RX buffer full. 00147 #define SPI_TXBUFE 7 ///< TX buffer empty. 00148 #define SPI_NSSR 8 ///< NSS rising. 00149 #define SPI_TXEMPTY 9 ///< Transmission register empty. 00150 #define SPI_SPIENS 16 ///< SPI enable status. 00151 /*\}*/ 00152 00156 /*\{*/ 00157 #define SPI_CSR0_OFF 0x00000030 ///< Chip select register 0 offset. 00158 #define SPI_CSR1_OFF 0x00000034 ///< Chip select register 1 offset. 00159 #define SPI_CSR2_OFF 0x00000038 ///< Chip select register 2 offset. 00160 #define SPI_CSR3_OFF 0x0000003C ///< Chip select register 3 offset. 00161 00162 #define SPI_CPOL 0 ///< Clock polarity. 00163 #define SPI_NCPHA 1 ///< Clock phase. 00164 #define SPI_CSAAT 3 ///< Chip select active after transfer. 00165 #define SPI_BITS 0x000000F0 ///< Bits per transfer mask. 00166 #define SPI_BITS_8 0x00000000 ///< 8 bits per transfer. 00167 #define SPI_BITS_9 0x00000010 ///< 9 bits per transfer. 00168 #define SPI_BITS_10 0x00000020 ///< 10 bits per transfer. 00169 #define SPI_BITS_11 0x00000030 ///< 11 bits per transfer. 00170 #define SPI_BITS_12 0x00000040 ///< 12 bits per transfer. 00171 #define SPI_BITS_13 0x00000050 ///< 13 bits per transfer. 00172 #define SPI_BITS_14 0x00000060 ///< 14 bits per transfer. 00173 #define SPI_BITS_15 0x00000070 ///< 15 bits per transfer. 00174 #define SPI_BITS_16 0x00000080 ///< 16 bits per transfer. 00175 #define SPI_BITS_SHIFT 4 ///< Least significant bit of bits per transfer. 00176 #define SPI_SCBR 0x0000FF00 ///< Serial clock baud rate mask. 00177 #define SPI_SCBR_SHIFT 8 ///< Least significant bit of serial clock baud rate. 00178 #define SPI_DLYBS 0x00FF0000 ///< Delay before SPCK mask. 00179 #define SPI_DLYBS_SHIFT 16 ///< Least significant bit of delay before SPCK. 00180 #define SPI_DLYBCT 0xFF000000 ///< Delay between consecutive transfers mask. 00181 #define SPI_DLYBCT_SHIFT 24 ///< Least significant bit of delay between consecutive transfers. 00182 /*\}*/ 00183 00187 /*\{*/ 00188 #if defined(SPI_BASE) 00189 #define SPI0_BASE SPI_BASE 00190 #define SPI_CR SPI0_CR ///< SPI Control Register Write-only. 00191 #define SPI_MR SPI0_MR ///< SPI Mode Register Read/Write Reset=0x0. 00192 #define SPI_RDR SPI0_RDR ///< SPI Receive Data Register Read-only Reset=0x0. 00193 #define SPI_TDR SPI0_TDR ///< SPI Transmit Data Register Write-only . 00194 #define SPI_SR SPI0_SR ///< SPI Status Register Read-only Reset=0x000000F0. 00195 #define SPI_IER SPI0_IER ///< SPI Interrupt Enable Register Write-only. 00196 #define SPI_IDR SPI0_IDR ///< SPI Interrupt Disable Register Write-only. 00197 #define SPI_IMR SPI0_IMR ///< SPI Interrupt Mask Register Read-only Reset=0x0. 00198 #define SPI_CSR0 SPI0_CSR0 ///< SPI Chip Select Register 0 Read/Write Reset=0x0. 00199 #define SPI_CSR1 SPI0_CSR1 ///< SPI Chip Select Register 1 Read/Write Reset=0x0. 00200 #define SPI_CSR2 SPI0_CSR2 ///< SPI Chip Select Register 2 Read/Write Reset=0x0. 00201 #define SPI_CSR3 SPI0_CSR3 ///< SPI Chip Select Register 3 Read/Write Reset=0x0. 00202 #if defined(SPI_HAS_PDC) 00203 #define SPI_RPR SPI0_RPR ///< PDC channel 0 receive pointer register. 00204 #define SPI_RCR SPI0_RCR ///< PDC channel 0 receive counter register. 00205 #define SPI_TPR SPI0_TPR ///< PDC channel 0 transmit pointer register. 00206 #define SPI_TCR SPI0_TCR ///< PDC channel 0 transmit counter register. 00207 #define SPI_RNPR SPI0_RNPR ///< PDC channel 0 receive next pointer register. 00208 #define SPI_RNCR SPI0_RNCR ///< PDC channel 0 receive next counter register. 00209 #define SPI_TNPR SPI0_TNPR ///< PDC channel 0 transmit next pointer register. 00210 #define SPI_TNCR SPI0_TNCR ///< PDC channel 0 transmit next counter register. 00211 #define SPI_PTCR SPI0_PTCR ///< PDC channel 0 transfer control register. 00212 #define SPI_PTSR SPI0_PTSR ///< PDC channel 0 transfer status register. 00213 #endif /* SPI_HAS_PDC */ 00214 #endif /* SPI_BASE */ 00215 /*\}*/ 00216 00220 /*\{*/ 00221 #if defined(SPI0_BASE) 00222 #define SPI0_CR (*((reg32_t *)(SPI0_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only. 00223 #define SPI0_MR (*((reg32_t *)(SPI0_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0. 00224 #define SPI0_RDR (*((reg32_t *)(SPI0_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0. 00225 #define SPI0_TDR (*((reg32_t *)(SPI0_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only . 00226 #define SPI0_SR (*((reg32_t *)(SPI0_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0. 00227 #define SPI0_IER (*((reg32_t *)(SPI0_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only. 00228 #define SPI0_IDR (*((reg32_t *)(SPI0_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only. 00229 #define SPI0_IMR (*((reg32_t *)(SPI0_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0. 00230 #define SPI0_CSR0 (*((reg32_t *)(SPI0_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0. 00231 #define SPI0_CSR1 (*((reg32_t *)(SPI0_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0. 00232 #define SPI0_CSR2 (*((reg32_t *)(SPI0_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0. 00233 #define SPI0_CSR3 (*((reg32_t *)(SPI0_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0. 00234 #if defined(SPI_HAS_PDC) 00235 #define SPI0_RPR (*((reg32_t *)(SPI0_BASE + PERIPH_RPR_OFF))) ///< PDC channel 0 receive pointer register. 00236 #define SPI0_RCR (*((reg32_t *)(SPI0_BASE + PERIPH_RCR_OFF))) ///< PDC channel 0 receive counter register. 00237 #define SPI0_TPR (*((reg32_t *)(SPI0_BASE + PERIPH_TPR_OFF))) ///< PDC channel 0 transmit pointer register. 00238 #define SPI0_TCR (*((reg32_t *)(SPI0_BASE + PERIPH_TCR_OFF))) ///< PDC channel 0 transmit counter register. 00239 #define SPI0_RNPR (*((reg32_t *)(SPI0_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 0 receive next pointer register. 00240 #define SPI0_RNCR (*((reg32_t *)(SPI0_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 0 receive next counter register. 00241 #define SPI0_TNPR (*((reg32_t *)(SPI0_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 0 transmit next pointer register. 00242 #define SPI0_TNCR (*((reg32_t *)(SPI0_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 0 transmit next counter register. 00243 #define SPI0_PTCR (*((reg32_t *)(SPI0_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 0 transfer control register. 00244 #define SPI0_PTSR (*((reg32_t *)(SPI0_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 0 transfer status register. 00245 #endif /* SPI_HAS_PDC */ 00246 #endif /* SPI0_BASE */ 00247 /*\}*/ 00248 00252 /*\{*/ 00253 #if defined(SPI1_BASE) 00254 #define SPI1_CR (*((reg32_t *)(SPI1_BASE + SPI_CR_OFF))) ///< SPI Control Register Write-only. 00255 #define SPI1_MR (*((reg32_t *)(SPI1_BASE + SPI_MR_OFF))) ///< SPI Mode Register Read/Write Reset=0x0. 00256 #define SPI1_RDR (*((reg32_t *)(SPI1_BASE + SPI_RDR_OFF))) ///< SPI Receive Data Register Read-only Reset=0x0. 00257 #define SPI1_TDR (*((reg32_t *)(SPI1_BASE + SPI_TDR_OFF))) ///< SPI Transmit Data Register Write-only . 00258 #define SPI1_SR (*((reg32_t *)(SPI1_BASE + SPI_SR_OFF))) ///< SPI Status Register Read-only Reset=0x000000F0. 00259 #define SPI1_IER (*((reg32_t *)(SPI1_BASE + SPI_IER_OFF))) ///< SPI Interrupt Enable Register Write-only. 00260 #define SPI1_IDR (*((reg32_t *)(SPI1_BASE + SPI_IDR_OFF))) ///< SPI Interrupt Disable Register Write-only. 00261 #define SPI1_IMR (*((reg32_t *)(SPI1_BASE + SPI_IMR_OFF))) ///< SPI Interrupt Mask Register Read-only Reset=0x0. 00262 #define SPI1_CSR0 (*((reg32_t *)(SPI1_BASE + SPI_CSR0_OFF))) ///< SPI Chip Select Register 0 Read/Write Reset=0x0. 00263 #define SPI1_CSR1 (*((reg32_t *)(SPI1_BASE + SPI_CSR1_OFF))) ///< SPI Chip Select Register 1 Read/Write Reset=0x0. 00264 #define SPI1_CSR2 (*((reg32_t *)(SPI1_BASE + SPI_CSR2_OFF))) ///< SPI Chip Select Register 2 Read/Write Reset=0x0. 00265 #define SPI1_CSR3 (*((reg32_t *)(SPI1_BASE + SPI_CSR3_OFF))) ///< SPI Chip Select Register 3 Read/Write Reset=0x0. 00266 #if defined(SPI_HAS_PDC) 00267 #define SPI1_RPR (*((reg32_t *)(SPI1_BASE + PERIPH_RPR_OFF))) ///< PDC channel 1 receive pointer register. 00268 #define SPI1_RCR (*((reg32_t *)(SPI1_BASE + PERIPH_RCR_OFF))) ///< PDC channel 1 receive counter register. 00269 #define SPI1_TPR (*((reg32_t *)(SPI1_BASE + PERIPH_TPR_OFF))) ///< PDC channel 1 transmit pointer register. 00270 #define SPI1_TCR (*((reg32_t *)(SPI1_BASE + PERIPH_TCR_OFF))) ///< PDC channel 1 transmit counter register. 00271 #define SPI1_RNPR (*((reg32_t *)(SPI1_BASE + PERIPH_RNPR_OFF))) ///< PDC channel 1 receive next pointer register. 00272 #define SPI1_RNCR (*((reg32_t *)(SPI1_BASE + PERIPH_RNCR_OFF))) ///< PDC channel 1 receive next counter register. 00273 #define SPI1_TNPR (*((reg32_t *)(SPI1_BASE + PERIPH_TNPR_OFF))) ///< PDC channel 1 transmit next pointer register. 00274 #define SPI1_TNCR (*((reg32_t *)(SPI1_BASE + PERIPH_TNCR_OFF))) ///< PDC channel 1 transmit next counter register. 00275 #define SPI1_PTCR (*((reg32_t *)(SPI1_BASE + PERIPH_PTCR_OFF))) ///< PDC channel 1 transfer control register. 00276 #define SPI1_PTSR (*((reg32_t *)(SPI1_BASE + PERIPH_PTSR_OFF))) ///< PDC channel 1 transfer status register. 00277 #endif /* SPI_HAS_PDC */ 00278 #endif /* SPI1_BASE */ 00279 /*\}*/ 00280 00281 #endif /* AT91_SPI_H */