BeRTOS
|
00001 00040 /* 00041 * Copyright (C) 2007 by egnite Software GmbH. All rights reserved. 00042 * 00043 * Redistribution and use in source and binary forms, with or without 00044 * modification, are permitted provided that the following conditions 00045 * are met: 00046 * 00047 * 1. Redistributions of source code must retain the above copyright 00048 * notice, this list of conditions and the following disclaimer. 00049 * 2. Redistributions in binary form must reproduce the above copyright 00050 * notice, this list of conditions and the following disclaimer in the 00051 * documentation and/or other materials provided with the distribution. 00052 * 3. Neither the name of the copyright holders nor the names of 00053 * contributors may be used to endorse or promote products derived 00054 * from this software without specific prior written permission. 00055 * 00056 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00057 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00058 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00059 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00060 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00061 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00062 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00063 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00064 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00065 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00066 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00067 * SUCH DAMAGE. 00068 * 00069 * For additional information see http://www.ethernut.de/ 00070 */ 00071 00072 #ifndef AT91_PIT_H 00073 #define AT91_PIT_H 00074 00075 #include <cfg/compiler.h> 00080 #define PIT_MR_OFF 0x00000000 ///< Mode register offset. 00081 #define PIT_MR (*((reg32_t *)(PIT_BASE + PIT_MR_OFF))) ///< Mode register address. 00082 00083 #define PIV_MASK 0x000FFFFF ///< Periodic interval value mask. 00084 #define PIV_SHIFT 0 ///< Periodic interval value shift. 00085 #define PITEN 24 ///< Periodic interval timer enable. 00086 #define PITIEN 25 ///< Periodic interval timer interrupt enable. 00087 /*\}*/ 00088 00093 #define PIT_SR_OFF 0x00000004 ///< Status register offset. 00094 #define PIT_SR (*((reg32_t *)(PIT_BASE + PIT_SR_OFF))) ///< Status register address. 00095 00096 #define PITS 0 ///< Timer has reached PIV. 00097 /*\}*/ 00098 00103 #define PIVR_OFF 0x00000008 ///< Value register offset. 00104 #define PIVR (*((reg32_t *)(PIT_BASE + PIVR_OFF))) ///< Value register address. 00105 00106 #define PIIR_OFF 0x0000000C ///< Image register offset. 00107 #define PIIR (*((reg32_t *)(PIT_BASE + PIIR_OFF))) ///< Image register address. 00108 #define CPIV_MASK 0x000FFFFF ///< Current periodic interval value mask. 00109 #define CPIV_SHIFT 0 ///< Current periodic interval value SHIFT. 00110 #define PICNT_MASK 0xFFF00000 ///< Periodic interval counter mask. 00111 #define PICNT_SHIFT 20 ///< Periodic interval counter LSB. 00112 /*\}*/ 00113 00114 #endif /* AT91_PIT_H */