BeRTOS
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Low-level clocking driver for Cortex-M3 STM32. More...
#include <cfg/compiler.h>
Go to the source code of this file.
Defines | |
#define | CR_OFFSET (RCC_OFFSET + 0x00) |
CR Register. | |
#define | HSION_BITNUMBER 0x00 |
CR Register. | |
#define | CR_HSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BITNUMBER * 4))) |
CR Register. | |
#define | PLLON_BITNUMBER 0x18 |
CR Register. | |
#define | CR_PLLON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BITNUMBER * 4))) |
CR Register. | |
#define | CSSON_BITNUMBER 0x13 |
CR Register. | |
#define | CR_CSSON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BITNUMBER * 4))) |
CR Register. | |
#define | CFGR_OFFSET (RCC_OFFSET + 0x04) |
CFGR Register. | |
#define | USBPRE_BITNUMBER 0x16 |
CFGR Register. | |
#define | CFGR_USBPRE_BB ((reg32_t *)(PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BITNUMBER * 4))) |
CFGR Register. | |
#define | BDCR_OFFSET (RCC_OFFSET + 0x20) |
BDCR Register. | |
#define | RTCEN_BITNUMBER 0x0F |
BDCR Register. | |
#define | BDCR_RTCEN_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BITNUMBER * 4))) |
BDCR Register. | |
#define | BDRST_BITNUMBER 0x10 |
BDCR Register. | |
#define | BDCR_BDRST_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BITNUMBER * 4))) |
BDCR Register. | |
#define | CSR_OFFSET (RCC_OFFSET + 0x24) |
CSR Register. | |
#define | LSION_BITNUMBER 0x00 |
CSR Register. | |
#define | CSR_LSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BITNUMBER * 4))) |
CSR Register. | |
#define | CR_HSEBYP_RESET (0xFFFBFFFF) |
RCC registers bit mask. | |
#define | CR_HSEBYP_SET (0x00040000) |
RCC registers bit mask. | |
#define | CR_HSEON_RESET (0xFFFEFFFF) |
RCC registers bit mask. | |
#define | CR_HSEON_SET (0x00010000) |
RCC registers bit mask. | |
#define | CR_HSITRIM_MASK (0xFFFFFF07) |
RCC registers bit mask. | |
#define | CFGR_PLL_MASK (0xFFC0FFFF) |
RCC registers bit mask. | |
#define | CFGR_PLLMull_MASK (0x003C0000) |
RCC registers bit mask. | |
#define | CFGR_PLLSRC_MASK (0x00010000) |
RCC registers bit mask. | |
#define | CFGR_PLLXTPRE_MASK (0x00020000) |
RCC registers bit mask. | |
#define | CFGR_SWS_MASK (0x0000000C) |
RCC registers bit mask. | |
#define | CFGR_SW_MASK (0xFFFFFFFC) |
RCC registers bit mask. | |
#define | CFGR_HPRE_RESET_MASK (0xFFFFFF0F) |
RCC registers bit mask. | |
#define | CFGR_HPRE_SET_MASK (0x000000F0) |
RCC registers bit mask. | |
#define | CFGR_PPRE1_RESET_MASK (0xFFFFF8FF) |
RCC registers bit mask. | |
#define | CFGR_PPRE1_SET_MASK (0x00000700) |
RCC registers bit mask. | |
#define | CFGR_PPRE2_RESET_MASK (0xFFFFC7FF) |
RCC registers bit mask. | |
#define | CFGR_PPRE2_SET_MASK (0x00003800) |
RCC registers bit mask. | |
#define | CFGR_ADCPRE_RESET_MASK (0xFFFF3FFF) |
RCC registers bit mask. | |
#define | CFGR_ADCPRE_SET_MASK (0x0000C000) |
RCC registers bit mask. | |
#define | CSR_RVMF_SET (0x01000000) |
RCC registers bit mask. | |
#define | FLAG_MASK (0x1F) |
RCC registers bit mask. | |
#define | HSI_VALUE (8000000) |
RCC registers bit mask. | |
#define | BDCR_BASE (PERIPH_BASE + BDCR_OFFSET) |
RCC registers bit mask. | |
#define | RCC_FLAG_HSIRDY (0x20) |
RCC registers bit mask. | |
#define | RCC_FLAG_HSERDY (0x31) |
RCC registers bit mask. | |
#define | RCC_FLAG_PLLRDY (0x39) |
RCC registers bit mask. | |
#define | RCC_FLAG_LSERDY (0x41) |
RCC registers bit mask. | |
#define | RCC_FLAG_LSIRDY (0x61) |
RCC registers bit mask. | |
#define | RCC_FLAG_PINRST (0x7A) |
RCC registers bit mask. | |
#define | RCC_FLAG_PORRST (0x7B) |
RCC registers bit mask. | |
#define | RCC_FLAG_SFTRST (0x7C) |
RCC registers bit mask. | |
#define | RCC_FLAG_IWDGRST (0x7D) |
RCC registers bit mask. | |
#define | RCC_FLAG_WWDGRST (0x7E) |
RCC registers bit mask. | |
#define | RCC_FLAG_LPWRRST (0x7F) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_HSI (0x00000000) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_HSE (0x00000001) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_PLLCLK (0x00000002) |
RCC registers bit mask. | |
#define | RCC_PLL_HSI_DIV2 (0x00000000) |
RCC registers bit mask. | |
#define | RCC_PLL_HSE_DIV1 (0x00010000) |
RCC registers bit mask. | |
#define | RCC_PLL_HSE_DIV2 (0x00030000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_2 (0x00000000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_3 (0x00040000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_4 (0x00080000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_5 (0x000C0000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_6 (0x00100000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_7 (0x00140000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_8 (0x00180000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_9 (0x001C0000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_10 (0x00200000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_11 (0x00240000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_12 (0x00280000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_13 (0x002C0000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_14 (0x00300000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_15 (0x00340000) |
RCC registers bit mask. | |
#define | RCC_PLLMUL_16 (0x00380000) |
RCC registers bit mask. | |
#define | RCC_HCLK_DIV1 (0x00000000) |
RCC registers bit mask. | |
#define | RCC_HCLK_DIV2 (0x00000400) |
RCC registers bit mask. | |
#define | RCC_HCLK_DIV4 (0x00000500) |
RCC registers bit mask. | |
#define | RCC_HCLK_DIV8 (0x00000600) |
RCC registers bit mask. | |
#define | RCC_HCLK_DIV16 (0x00000700) |
RCC registers bit mask. | |
#define | RCC_USBCLK_PLLCLK_1DIV5 (0x00) |
RCC registers bit mask. | |
#define | RCC_USBCLK_PLLCLK_DIV1 (0x01) |
RCC registers bit mask. | |
#define | RCC_PCLK2_DIV2 (0x00000000) |
RCC registers bit mask. | |
#define | RCC_PCLK2_DIV4 (0x00004000) |
RCC registers bit mask. | |
#define | RCC_PCLK2_DIV6 (0x00008000) |
RCC registers bit mask. | |
#define | RCC_PCLK2_DIV8 (0x0000C000) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV1 (0x00000000) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV2 (0x00000080) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV4 (0x00000090) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV8 (0x000000A0) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV16 (0x000000B0) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV64 (0x000000C0) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV128 (0x000000D0) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV256 (0x000000E0) |
RCC registers bit mask. | |
#define | RCC_SYSCLK_DIV512 (0x000000F0) |
RCC registers bit mask. | |
#define | RCC_APB1_TIM2 (0x00000001) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_TIM3 (0x00000002) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_TIM4 (0x00000004) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_WWDG (0x00000800) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_SPI2 (0x00004000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_USART2 (0x00020000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_USART3 (0x00040000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_I2C1 (0x00200000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_I2C2 (0x00400000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_USB (0x00800000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_CAN (0x02000000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_BKP (0x08000000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_PWR (0x10000000) |
RCC register: APB1 peripheral. | |
#define | RCC_APB1_ALL (0x1AE64807) |
RCC register: APB1 peripheral. | |
#define | RCC_APB2_AFIO (0x00000001) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_GPIOA (0x00000004) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_GPIOB (0x00000008) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_GPIOC (0x00000010) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_GPIOD (0x00000020) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_GPIOE (0x00000040) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_ADC1 (0x00000200) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_ADC2 (0x00000400) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_TIM1 (0x00000800) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_SPI1 (0x00001000) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_USART1 (0x00004000) |
RCC register: APB2 peripheral. | |
#define | RCC_APB2_ALL (0x00005E7D) |
RCC register: APB2 peripheral. | |
#define | RCC_BDCR_LSEON (0x00000001) |
RCC register: BCDR. | |
#define | RCC_BDCR_LSERDY (0x00000002) |
RCC register: APB2 peripheral. | |
#define | RCC_BDCR_RTCSEL (0x00000300) |
RCC register: APB2 peripheral. | |
#define | RCC_BDCR_RTCEN (0x00008000) |
RCC register: APB2 peripheral. |
Low-level clocking driver for Cortex-M3 STM32.
Definition in file clock_stm32.h.