BeRTOS
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00001 00042 #ifndef SAM3_ADC_H 00043 #define SAM3_ADC_H 00044 00046 #define ADC_BASE 0x400C0000 00047 00052 #define ADC_CR_OFF 0x00000000 ///< Control register offeset. 00053 #define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address. 00054 #define ADC_SWRST 0 ///< Software reset. 00055 #define ADC_START 1 ///< Start conversion. 00056 /* \} */ 00057 00062 #define ADC_MR_OFF 0x00000004 ///< Mode register offeset. 00063 #define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address. 00064 #define ADC_TRGEN 0 ///< Trigger enable. 00065 00066 #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0. 00067 #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1. 00068 #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2. 00069 #define ADC_TRGSEL_PWM0 0x0000000A ///< PWM Event Line 0. 00070 #define ADC_TRGSEL_PWM1 0x0000000C ///< PWM Event Line 1. 00071 00072 #define ADC_LOWRES 4 ///< Resolution 0: 12-bit, 1: 10-bit. 00073 #define ADC_SLEEP 5 ///< Sleep mode. 00074 #define ADC_FREERUN 7 ///< Freerun. 00075 00080 #define ADC_PRESCALER_MASK 0x0000FF00 ///< Prescaler rate selection mask. 00081 #define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift. 00082 00086 #define ADC_STARTUP_MASK 0x000F0000 ///< Start up timer mask. 00087 #define ADC_STARTUP_SHIFT 16 ///< Start up timer shift. 00088 00094 #define ADC_SUT0 0 ///< 0 period of ADCClock. 00095 #define ADC_SUT8 1 ///< 8 period of ADCClock. 00096 #define ADC_SUT16 2 ///< 16 period of ADCClock. 00097 #define ADC_SUT24 3 ///< 24 period of ADCClock. 00098 #define ADC_SUT64 4 ///< 64 period of ADCClock. 00099 #define ADC_SUT80 5 ///< 80 period of ADCClock. 00100 #define ADC_SUT96 6 ///< 96 period of ADCClock. 00101 #define ADC_SUT112 7 ///< 112 period of ADCClock. 00102 #define ADC_SUT512 8 ///< 512 period of ADCClock. 00103 #define ADC_SUT576 9 ///< 576 period of ADCClock. 00104 #define ADC_SUT640 10 ///< 640 period of ADCClock. 00105 #define ADC_SUT704 11 ///< 704 period of ADCClock. 00106 #define ADC_SUT768 12 ///< 768 period of ADCClock. 00107 #define ADC_SUT832 13 ///< 832 period of ADCClock. 00108 #define ADC_SUT896 14 ///< 896 period of ADCClock. 00109 #define ADC_SUT960 15 ///< 896 period of ADCClock. 00110 00116 #define ADC_SETTLING_MASK 0x00300000 ///< Analog Settling Time mask. 00117 #define ADC_SETTLING_SHIFT 20 ///< Analog Settling Time shift. 00118 #define ADC_AST3 0 ///< 3 period of ADCClock 00119 #define ADC_AST5 1 ///< 5 period of ADCClock 00120 #define ADC_AST9 2 ///< 9 period of ADCClock 00121 #define ADC_AST17 3 ///< 17 period of ADCClock 00122 00127 #define ADC_TRACKTIM_MASK 0x0F000000 ///< Tracking Time mask. 00128 #define ADC_TRACKTIM_SHIFT 24 ///< Tracking Time shift. 00129 00134 #define ADC_TRANSFER_MASK 0x30000000 ///< Transfer Period mask. 00135 #define ADC_TRANSFER_SHIFT 28 ///< Transfer Period shift. 00136 /* \} */ 00137 00138 00142 #define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset. 00143 #define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address. 00144 00148 #define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset. 00149 #define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address. 00150 00154 #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset. 00155 #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address. 00156 00157 00161 #define ADC_SR_OFF 0x0000001C ///< Status register offeset. 00162 #define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address. 00163 00164 00165 #define ADC_CH_MASK 0x000000FF ///< Channel mask. 00166 #define ADC_CH0 0 ///< Channel 0 00167 #define ADC_CH1 1 ///< Channel 1 00168 #define ADC_CH2 2 ///< Channel 2 00169 #define ADC_CH3 3 ///< Channel 3 00170 #define ADC_CH4 4 ///< Channel 4 00171 #define ADC_CH5 5 ///< Channel 5 00172 #define ADC_CH6 6 ///< Channel 6 00173 #define ADC_CH7 7 ///< Channel 7 00174 00178 #define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset. 00179 #define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register. 00180 00184 #define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset. 00185 #define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register. 00186 00190 #define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset. 00191 #define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register. 00192 00196 #define ADC_ISR_OFF 0x00000030 ///< Interrupt status register offeset. 00197 #define ADC_ISR (*((reg32_t *)(ADC_BASE + ADC_ISR_OFF))) ///< Interrupt status register. 00198 00199 #define ADC_EOC_MASK 0x000000FF ///< End of converison mask. 00200 #define ADC_EOC0 0 ///< End of conversion channel 0. 00201 #define ADC_EOC1 1 ///< End of conversion channel 1. 00202 #define ADC_EOC2 2 ///< End of conversion channel 2. 00203 #define ADC_EOC3 3 ///< End of conversion channel 3. 00204 #define ADC_EOC4 4 ///< End of conversion channel 4. 00205 #define ADC_EOC5 5 ///< End of conversion channel 5. 00206 #define ADC_EOC6 6 ///< End of conversion channel 6. 00207 #define ADC_EOC7 7 ///< End of conversion channel 7. 00208 00209 #define ADC_OVRE0 8 ///< Overrun error channel 0. 00210 #define ADC_OVRE1 9 ///< Overrun error channel 1. 00211 #define ADC_OVRE2 10 ///< Overrun error channel 2. 00212 #define ADC_OVRE3 11 ///< Overrun error channel 3. 00213 #define ADC_OVRE4 12 ///< Overrun error channel 4. 00214 #define ADC_OVRE5 13 ///< Overrun error channel 5. 00215 #define ADC_OVRE6 14 ///< Overrun error channel 6. 00216 #define ADC_OVRE7 15 ///< Overrun error channel 7. 00217 00218 #define ADC_DRDY 24 ///< Data ready. 00219 #define ADC_GOVRE 25 ///< General overrun error. 00220 #define ADC_COMPE 26 ///< Comparition event interrupt mask. 00221 #define ADC_ENDRX 27 ///< End of RX buffer. 00222 #define ADC_RXBUFF 28 ///< Rx buffer full. 00223 00228 #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset. 00229 #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted RAW data register. 00230 #define ADC_LDATA (ADC_LCDR & 0xFFF) ///< Last data converted register. 00231 #define ADC_CHNB ((ADC_LCDR & 0xF000) >> 12) ///< Channel number. 00232 /* \} */ 00233 00234 00239 #define ADC_CDR_OFF 0x00000050 ///< Channel data register offeset. 00240 #define ADC_CDR (*((reg32_t *)(ADC_BASE + ADC_CDR_OFF))) ///< Channel data register. 00241 /* \} */ 00242 00243 00248 #define ADC_ACR_OFF 0x00000094 ///< Analog control register offeset. 00249 #define ADC_ACR (*((reg32_t *)(ADC_BASE + ADC_ACR_OFF))) ///< Analog control register. 00250 #define ADC_TSON 4 ///< Temperature Sensor On. 00251 #define ADC_TEMPERATURE_CH 15 ///< Channel where is the internal sensor temperature 00252 /* \} */ 00253 00254 #endif /* SAM3_ADC_H */