BeRTOS
clock_sam3.c
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00001 
00038 #include "clock_sam3.h"
00039 #include <cfg/compiler.h>
00040 #include <cfg/macros.h>
00041 #include <io/sam3.h>
00042 
00043 
00044 /* Frequency of board main oscillator */
00045 #define BOARDOSC_FREQ  12000000
00046 
00047 /* Timer countdown timeout for clock initialization operations */
00048 #define CLOCK_TIMEOUT    0xFFFFFFFF
00049 
00050 
00051 #if CPU_FREQ == 84000000 || CPU_FREQ == 48000000
00052 
00053 INLINE uint32_t evaluate_pll(void)
00054 {
00055     return CKGR_PLLR_MUL(CPU_FREQ / BOARDOSC_FREQ * 2 - 1) | CKGR_PLLR_DIV(2);
00056 }
00057 
00058 #else
00059 
00060 #warning CPU clock frequency non-standard setting: multiplier and divider values \
00061  will be computed at runtime: effective computed frequency could be different \
00062  from expected.
00063 
00064 /*
00065  * Try to evaluate the correct divider and multiplier value depending
00066  * on the desired CPU frequency.
00067  *
00068  * We try all combinations in a certain range of divider and multiplier
00069  * values.  Start with higher multipliers and divisors, generally better.
00070  */
00071 INLINE uint32_t evaluate_pll(void)
00072 {
00073     int mul, div, best_mul, best_div;
00074     int best_delta = CPU_FREQ;
00075     int freq = 0;
00076 
00077     for (mul = 13; mul > 0; mul--)
00078     {
00079         for (div = 24; div > 0; div--)
00080         {
00081             freq = BOARDOSC_FREQ / div * (1 + mul);
00082             if (ABS((int)CPU_FREQ - freq) < best_delta) {
00083                 best_delta = ABS((int)CPU_FREQ - freq);
00084                 best_mul = mul;
00085                 best_div = div;
00086             }
00087         }
00088     }
00089 
00090     return CKGR_PLLR_DIV(best_div) | CKGR_PLLR_MUL(best_mul);
00091 }
00092 
00093 #endif /* CPU_FREQ */
00094 
00095 void clock_init(void)
00096 {
00097     uint32_t timeout;
00098 
00099     /* Disable watchdog */
00100     WDT_MR = BV(WDT_WDDIS);
00101 
00102     /* Set wait states for flash access, needed for higher CPU clock rates */
00103     EEFC0_FMR = EEFC_FMR_FWS(3);
00104 #ifdef EEFC1_FMR
00105     EEFC1_FMR = EEFC_FMR_FWS(3);
00106 #endif
00107 
00108     // Initialize main oscillator
00109     if (!(CKGR_MOR & BV(CKGR_MOR_MOSCSEL)))
00110     {
00111         CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
00112             | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN);
00113         timeout = CLOCK_TIMEOUT;
00114         while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
00115     }
00116 
00117     // Switch to external oscillator
00118     CKGR_MOR = CKGR_MOR_KEY(0x37) | CKGR_MOR_MOSCXTST(0x8)
00119         | BV(CKGR_MOR_MOSCRCEN) | BV(CKGR_MOR_MOSCXTEN) | BV(CKGR_MOR_MOSCSEL);
00120     timeout = CLOCK_TIMEOUT;
00121     while (!(PMC_SR & BV(PMC_SR_MOSCXTS)) && --timeout);
00122 
00123     // Initialize and enable PLL clock
00124     CKGR_PLLR = evaluate_pll() | BV(CKGR_PLLR_STUCKTO1) | CKGR_PLLR_PLLCOUNT(0x2);
00125     timeout = CLOCK_TIMEOUT;
00126     while (!(PMC_SR & BV(PMC_SR_LOCK)) && --timeout);
00127 
00128     PMC_MCKR = PMC_MCKR_CSS_MAIN_CLK;
00129     timeout = CLOCK_TIMEOUT;
00130     while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
00131 
00132     PMC_MCKR = PMC_MCKR_CSS_PLL_CLK;
00133     timeout = CLOCK_TIMEOUT;
00134     while (!(PMC_SR & BV(PMC_SR_MCKRDY)) && --timeout);
00135 
00136     /* Enable clock on PIO for inputs */
00137     // TODO: move this in gpio_init() for better power management?
00138     pmc_periphEnable(PIOA_ID);
00139     pmc_periphEnable(PIOB_ID);
00140     pmc_periphEnable(PIOC_ID);
00141 #ifdef PIOF_ID
00142     pmc_periphEnable(PIOD_ID);
00143     pmc_periphEnable(PIOE_ID);
00144     pmc_periphEnable(PIOF_ID);
00145 #endif
00146 }