BeRTOS
lm3s_i2c.h
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00001 
00036 #ifndef LM3S_I2C_H
00037 #define LM3S_I2C_H
00038 
00039 
00040 /* The following are defines for the I2C register offsets. */
00041 #define I2C_O_MSA               0x00000000  ///< I2C Master Slave Address
00042 #define I2C_O_SOAR              0x00000000  ///< I2C Slave Own Address
00043 #define I2C_O_SCSR              0x00000004  ///< I2C Slave Control/Status
00044 #define I2C_O_MCS               0x00000004  ///< I2C Master Control/Status
00045 #define I2C_O_SDR               0x00000008  ///< I2C Slave Data
00046 #define I2C_O_MDR               0x00000008  ///< I2C Master Data
00047 #define I2C_O_MTPR              0x0000000C  ///< I2C Master Timer Period
00048 #define I2C_O_SIMR              0x0000000C  ///< I2C Slave Interrupt Mask
00049 #define I2C_O_SRIS              0x00000010  ///< I2C Slave Raw Interrupt Status
00050 #define I2C_O_MIMR              0x00000010  ///< I2C Master Interrupt Mask
00051 #define I2C_O_MRIS              0x00000014  ///< I2C Master Raw Interrupt Status
00052 #define I2C_O_SMIS              0x00000014  ///< I2C Slave Masked Interrupt
00053 
00054 #define I2C_O_SICR              0x00000018  ///< I2C Slave Interrupt Clear
00055 #define I2C_O_MMIS              0x00000018  ///< I2C Master Masked Interrupt
00056 
00057 #define I2C_O_MICR              0x0000001C  ///< I2C Master Interrupt Clear
00058 #define I2C_O_MCR               0x00000020  ///< I2C Master Configuration
00059 
00060 
00061 /* The following are defines for the bit fields in the I2C_O_MSA register. */
00062 #define I2C_MSA_SA_M            0x000000FE  ///< I2C Slave Address
00063 #define I2C_MSA_RS              0x00000001  ///< Receive not send
00064 #define I2C_MSA_SA_S            1
00065 #define I2C_MSA_ADDS            0           ///< Set address write bit
00066 #define I2C_MSA_ADDR            1           ///< Set address read bit
00067 
00068 
00069 /* The following are defines for the bit fields in the I2C_O_SOAR register. */
00070 #define I2C_SOAR_OAR_M          0x0000007F  ///< I2C Slave Own Address
00071 #define I2C_SOAR_OAR_S          0
00072 
00073 
00074 /* The following are defines for the bit fields in the I2C_O_SCSR register. */
00075 #define I2C_SCSR_FBR            0x00000004  ///< First Byte Received
00076 #define I2C_SCSR_TREQ           0x00000002  ///< Transmit Request
00077 #define I2C_SCSR_DA             0x00000001  ///< Device Active
00078 #define I2C_SCSR_RREQ           0x00000001  ///< Receive Request
00079 
00080 /* The following are defines for the bit fields in the I2C_O_MCS register. */
00081 #define I2C_MCS_BUSBSY          0x00000040  ///< Bus Busy
00082 #define I2C_MCS_IDLE            0x00000020  ///< I2C Idle
00083 #define I2C_MCS_ARBLST          0x00000010  ///< Arbitration Lost
00084 #define I2C_MCS_ACK             0x00000008  ///< Data Acknowledge Enable
00085 #define I2C_MCS_DATACK          0x00000008  ///< Acknowledge Data
00086 #define I2C_MCS_ADRACK          0x00000004  ///< Acknowledge Address
00087 #define I2C_MCS_STOP            0x00000004  ///< Generate STOP
00088 #define I2C_MCS_START           0x00000002  ///< Generate START
00089 #define I2C_MCS_ERROR           0x00000002  ///< Error
00090 #define I2C_MCS_RUN             0x00000001  ///< I2C Master Enable
00091 #define I2C_MCS_BUSY            0x00000001  ///< I2C Busy
00092 
00093 
00094 /* The following are defines for the bit fields in the I2C_O_SDR register. */
00095 #define I2C_SDR_DATA_M          0x000000FF  ///< Data for Transfer
00096 #define I2C_SDR_DATA_S          0
00097 
00098 /* The following are defines for the bit fields in the I2C_O_MDR register. */
00099 #define I2C_MDR_DATA_M          0x000000FF  ///< Data Transferred
00100 #define I2C_MDR_DATA_S          0
00101 
00102 
00103 /* The following are defines for the bit fields in the I2C_O_MTPR register. */
00104 #define I2C_MTPR_TPR_M          0x000000FF  ///< SCL Clock Period
00105 #define I2C_MTPR_TPR_S          0
00106 
00107 
00108 /* The following are defines for the bit fields in the I2C_O_SIMR register. */
00109 #define I2C_SIMR_STOPIM         0x00000004  ///< Stop Condition Interrupt Mask
00110 #define I2C_SIMR_STARTIM        0x00000002  ///< Start Condition Interrupt Mask
00111 #define I2C_SIMR_DATAIM         0x00000001  ///< Data Interrupt Mask
00112 
00113 
00114 /* The following are defines for the bit fields in the I2C_O_SRIS register. */
00115 #define I2C_SRIS_STOPRIS        0x00000004  ///< Stop Condition Raw Interrupt
00116 
00117 #define I2C_SRIS_STARTRIS       0x00000002  ///< Start Condition Raw Interrupt
00118 
00119 #define I2C_SRIS_DATARIS        0x00000001  ///< Data Raw Interrupt Status
00120 
00121 
00122 /* The following are defines for the bit fields in the I2C_O_MIMR register. */
00123 #define I2C_MIMR_IM             0x00000001  ///< Interrupt Mask
00124 
00125 
00126 /* The following are defines for the bit fields in the I2C_O_MRIS register. */
00127 #define I2C_MRIS_RIS            0x00000001  ///< Raw Interrupt Status
00128 
00129 /* The following are defines for the bit fields in the I2C_O_SMIS register. */
00130 #define I2C_SMIS_STOPMIS        0x00000004  ///< Stop Condition Masked Interrupt
00131 
00132 #define I2C_SMIS_STARTMIS       0x00000002  ///< Start Condition Masked Interrupt
00133 
00134 #define I2C_SMIS_DATAMIS        0x00000001  ///< Data Masked Interrupt Status
00135 
00136 /* The following are defines for the bit fields in the I2C_O_SICR register. */
00137 #define I2C_SICR_STOPIC         0x00000004  ///< Stop Condition Interrupt Clear
00138 #define I2C_SICR_STARTIC        0x00000002  ///< Start Condition Interrupt Clear
00139 #define I2C_SICR_DATAIC         0x00000001  ///< Data Interrupt Clear
00140 
00141 /* The following are defines for the bit fields in the I2C_O_MMIS register. */
00142 #define I2C_MMIS_MIS            0x00000001  ///< Masked Interrupt Status
00143 
00144 
00145 /* The following are defines for the bit fields in the I2C_O_MICR register. */
00146 #define I2C_MICR_IC             0x00000001  ///< Interrupt Clear
00147 
00148 
00149 /* The following are defines for the bit fields in the I2C_O_MCR register. */
00150 #define I2C_MCR_SFE             0x00000020  ///< I2C Slave Function Enable
00151 #define I2C_MCR_MFE             0x00000010  ///< I2C Master Function Enable
00152 #define I2C_MCR_LPBK            0x00000001  ///< I2C Loopback
00153 
00154 
00155 
00156 #define I2C_MASTER_CMD_SINGLE_SEND                     0x00000007
00157 #define I2C_MASTER_CMD_SINGLE_RECEIVE                  0x00000007
00158 
00159 #define I2C_MASTER_CMD_BURST_SEND_START                0x00000003
00160 #define I2C_MASTER_CMD_BURST_SEND_CONT                 0x00000001
00161 #define I2C_MASTER_CMD_BURST_SEND_FINISH               0x00000005
00162 #define I2C_MASTER_CMD_BURST_SEND_ERROR_STOP           0x00000004
00163 
00164 #define I2C_MASTER_CMD_BURST_RECEIVE_START             0x0000000b
00165 #define I2C_MASTER_CMD_BURST_RECEIVE_CONT              0x00000009
00166 #define I2C_MASTER_CMD_BURST_RECEIVE_FINISH            0x00000005
00167 #define I2C_MASTER_CMD_BURST_RECEIVE_ERROR_STOP        0x00000004
00168 
00169 
00170 /* The following definitions are deprecated. */
00171 
00172 #ifndef DEPRECATED
00173 
00174     #define I2C_O_SLAVE             0x00000800  ///< Offset from master to slave
00175 
00176     #define I2C_SIMR_IM             0x00000001  ///< Interrupt Mask
00177 
00178     #define I2C_SRIS_RIS            0x00000001  ///< Raw Interrupt Status
00179 
00180     #define I2C_SMIS_MIS            0x00000001  ///< Masked Interrupt Status
00181 
00182     #define I2C_SICR_IC             0x00000001  ///< Clear Interrupt
00183 
00184     #define I2C_MASTER_O_SA         0x00000000  ///< Slave address register
00185     #define I2C_MASTER_O_CS         0x00000004  ///< Control and Status register
00186     #define I2C_MASTER_O_DR         0x00000008  ///< Data register
00187     #define I2C_MASTER_O_TPR        0x0000000C  ///< Timer period register
00188     #define I2C_MASTER_O_IMR        0x00000010  ///< Interrupt mask register
00189     #define I2C_MASTER_O_RIS        0x00000014  ///< Raw interrupt status register
00190     #define I2C_MASTER_O_MIS        0x00000018  ///< Masked interrupt status reg
00191     #define I2C_MASTER_O_MICR       0x0000001C  ///< Interrupt clear register
00192     #define I2C_MASTER_O_CR         0x00000020  ///< Configuration register
00193 
00194     #define I2C_SLAVE_O_SICR        0x00000018  ///< Interrupt clear register
00195     #define I2C_SLAVE_O_MIS         0x00000014  ///< Masked interrupt status reg
00196     #define I2C_SLAVE_O_RIS         0x00000010  ///< Raw interrupt status register
00197     #define I2C_SLAVE_O_IM          0x0000000C  ///< Interrupt mask register
00198     #define I2C_SLAVE_O_DR          0x00000008  ///< Data register
00199     #define I2C_SLAVE_O_CSR         0x00000004  ///< Control/Status register
00200     #define I2C_SLAVE_O_OAR         0x00000000  ///< Own address register
00201 
00202     #define I2C_MASTER_SA_SA_MASK   0x000000FE  ///< Slave address
00203     #define I2C_MASTER_SA_RS        0x00000001  ///< Receive/send
00204     #define I2C_MASTER_SA_SA_SHIFT  1
00205 
00206     #define I2C_MASTER_CS_BUS_BUSY  0x00000040  ///< Bus busy
00207     #define I2C_MASTER_CS_IDLE      0x00000020  ///< Idle
00208     #define I2C_MASTER_CS_ERR_MASK  0x0000001C
00209     #define I2C_MASTER_CS_BUSY      0x00000001  ///< Controller is TX/RX data
00210     #define I2C_MASTER_CS_ERROR     0x00000002  ///< Error occurred
00211     #define I2C_MASTER_CS_ADDR_ACK  0x00000004  ///< Address byte not acknowledged
00212     #define I2C_MASTER_CS_DATA_ACK  0x00000008  ///< Data byte not acknowledged
00213     #define I2C_MASTER_CS_ARB_LOST  0x00000010  ///< Lost arbitration
00214     #define I2C_MASTER_CS_ACK       0x00000008  ///< Acknowlegde
00215     #define I2C_MASTER_CS_STOP      0x00000004  ///< Stop
00216     #define I2C_MASTER_CS_START     0x00000002  ///< Start
00217     #define I2C_MASTER_CS_RUN       0x00000001  ///< Run
00218 
00219 
00220     #define I2C_SCL_FAST            400000      ///< SCL fast frequency
00221     #define I2C_SCL_STANDARD        100000      ///< SCL standard frequency
00222     #define I2C_MASTER_TPR_SCL_LP   0x00000006  ///< SCL low period
00223     #define I2C_MASTER_TPR_SCL_HP   0x00000004  ///< SCL high period
00224     #define I2C_MASTER_TPR_SCL      (I2C_MASTER_TPR_SCL_HP + I2C_MASTER_TPR_SCL_LP)
00225 
00226     #define I2C_MASTER_IMR_IM       0x00000001  ///< Master interrupt mask
00227 
00228     #define I2C_MASTER_RIS_RIS      0x00000001  ///< Master raw interrupt status
00229 
00230     #define I2C_MASTER_MIS_MIS      0x00000001  ///< Master masked interrupt status
00231 
00232     #define I2C_MASTER_MICR_IC      0x00000001  ///< Master interrupt clear
00233 
00234     #define I2C_MASTER_CR_SFE       0x00000020  ///< Slave function enable
00235     #define I2C_MASTER_CR_MFE       0x00000010  ///< Master function enable
00236     #define I2C_MASTER_CR_LPBK      0x00000001  ///< Loopback enable
00237 
00238     #define I2C_SLAVE_SOAR_OAR_MASK 0x0000007F  ///< Slave address
00239 
00240     #define I2C_SLAVE_CSR_FBR       0x00000004  ///< First byte received from master
00241     #define I2C_SLAVE_CSR_TREQ      0x00000002  ///< Transmit request received
00242     #define I2C_SLAVE_CSR_DA        0x00000001  ///< Enable the device
00243     #define I2C_SLAVE_CSR_RREQ      0x00000001  ///< Receive data from I2C master
00244 
00245     #define I2C_SLAVE_IMR_IM        0x00000001  ///< Slave interrupt mask
00246 
00247     #define I2C_SLAVE_RIS_RIS       0x00000001  ///< Slave raw interrupt status
00248 
00249     #define I2C_SLAVE_MIS_MIS       0x00000001  ///< Slave masked interrupt status
00250 
00251     #define I2C_SLAVE_SICR_IC       0x00000001  ///< Slave interrupt clear
00252 
00253 #endif
00254 
00255 #endif /* LM3S_I2C_H */