BeRTOS
lm3s_ssi.h
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00001 
00036 #ifndef LM3S_SSI_H
00037 #define LM3S_SSI_H
00038 
00042 /*\{*/
00043 #define SSI_O_CR0               0x00000000  //< SSI Control 0
00044 #define SSI_O_CR1               0x00000004  //< SSI Control 1
00045 #define SSI_O_DR                0x00000008  //< SSI Data
00046 #define SSI_O_SR                0x0000000C  //< SSI Status
00047 #define SSI_O_CPSR              0x00000010  //< SSI Clock Prescale
00048 #define SSI_O_IM                0x00000014  //< SSI Interrupt Mask
00049 #define SSI_O_RIS               0x00000018  //< SSI Raw Interrupt Status
00050 #define SSI_O_MIS               0x0000001C  //< SSI Masked Interrupt Status
00051 #define SSI_O_ICR               0x00000020  //< SSI Interrupt Clear
00052 #define SSI_O_DMACTL            0x00000024  //< SSI DMA Control
00053 /*\}*/
00054 
00058 /*\{*/
00059 #define SSI_CR0_SCR_M           0x0000FF00  //< SSI Serial Clock Rate
00060 #define SSI_CR0_SPH             0x00000080  //< SSI Serial Clock Phase
00061 #define SSI_CR0_SPO             0x00000040  //< SSI Serial Clock Polarity
00062 #define SSI_CR0_FRF_M           0x00000030  //< SSI Frame Format Select
00063 #define SSI_CR0_FRF_MOTO        0x00000000  //< Freescale SPI Frame Format
00064 #define SSI_CR0_FRF_TI          0x00000010  //< Texas Instruments Synchronous
00065                                             //< Serial Frame Format
00066 #define SSI_CR0_FRF_NMW         0x00000020  //< MICROWIRE Frame Format
00067 #define SSI_CR0_DSS_M           0x0000000F  //< SSI Data Size Select
00068 #define SSI_CR0_DSS_4           0x00000003  //< 4-bit data
00069 #define SSI_CR0_DSS_5           0x00000004  //< 5-bit data
00070 #define SSI_CR0_DSS_6           0x00000005  //< 6-bit data
00071 #define SSI_CR0_DSS_7           0x00000006  //< 7-bit data
00072 #define SSI_CR0_DSS_8           0x00000007  //< 8-bit data
00073 #define SSI_CR0_DSS_9           0x00000008  //< 9-bit data
00074 #define SSI_CR0_DSS_10          0x00000009  //< 10-bit data
00075 #define SSI_CR0_DSS_11          0x0000000A  //< 11-bit data
00076 #define SSI_CR0_DSS_12          0x0000000B  //< 12-bit data
00077 #define SSI_CR0_DSS_13          0x0000000C  //< 13-bit data
00078 #define SSI_CR0_DSS_14          0x0000000D  //< 14-bit data
00079 #define SSI_CR0_DSS_15          0x0000000E  //< 15-bit data
00080 #define SSI_CR0_DSS_16          0x0000000F  //< 16-bit data
00081 #define SSI_CR0_SCR_S           8
00082 /*\}*/
00083 
00087 /*\{*/
00088 #define SSI_CR1_EOT             0x00000010  //< End of Transmission
00089 #define SSI_CR1_SOD             0x00000008  //< SSI Slave Mode Output Disable
00090 #define SSI_CR1_MS              0x00000004  //< SSI Master/Slave Select
00091 #define SSI_CR1_SSE             0x00000002  //< SSI Synchronous Serial Port
00092                                             //< Enable
00093 #define SSI_CR1_LBM             0x00000001  //< SSI Loopback Mode
00094 /*\}*/
00095 
00099 /*\{*/
00100 #define SSI_DR_DATA_M           0x0000FFFF  //< SSI Receive/Transmit Data
00101 #define SSI_DR_DATA_S           0
00102 /*\}*/
00103 
00107 /*\{*/
00108 #define SSI_SR_BSY              0x00000010  //< SSI Busy Bit
00109 #define SSI_SR_RFF              0x00000008  //< SSI Receive FIFO Full
00110 #define SSI_SR_RNE              0x00000004  //< SSI Receive FIFO Not Empty
00111 #define SSI_SR_TNF              0x00000002  //< SSI Transmit FIFO Not Full
00112 #define SSI_SR_TFE              0x00000001  //< SSI Transmit FIFO Empty
00113 /*\}*/
00114 
00118 /*\{*/
00119 #define SSI_CPSR_CPSDVSR_M      0x000000FF  //< SSI Clock Prescale Divisor
00120 #define SSI_CPSR_CPSDVSR_S      0
00121 /*\}*/
00122 
00126 /*\{*/
00127 #define SSI_IM_TXIM             0x00000008  //< SSI Transmit FIFO Interrupt Mask
00128 #define SSI_IM_RXIM             0x00000004  //< SSI Receive FIFO Interrupt Mask
00129 #define SSI_IM_RTIM             0x00000002  //< SSI Receive Time-Out Interrupt
00130                                             //< Mask
00131 #define SSI_IM_RORIM            0x00000001  //< SSI Receive Overrun Interrupt
00132                                             //< Mask
00133 /*\}*/
00134 
00138 /*\{*/
00139 #define SSI_RIS_TXRIS           0x00000008  //< SSI Transmit FIFO Raw Interrupt
00140                                             //< Status
00141 #define SSI_RIS_RXRIS           0x00000004  //< SSI Receive FIFO Raw Interrupt
00142                                             //< Status
00143 #define SSI_RIS_RTRIS           0x00000002  //< SSI Receive Time-Out Raw
00144                                             //< Interrupt Status
00145 #define SSI_RIS_RORRIS          0x00000001  //< SSI Receive Overrun Raw
00146                                             //< Interrupt Status
00147 /*\}*/
00148 
00152 /*\{*/
00153 #define SSI_MIS_TXMIS           0x00000008  //< SSI Transmit FIFO Masked
00154                                             //< Interrupt Status
00155 #define SSI_MIS_RXMIS           0x00000004  //< SSI Receive FIFO Masked
00156                                             //< Interrupt Status
00157 #define SSI_MIS_RTMIS           0x00000002  //< SSI Receive Time-Out Masked
00158                                             //< Interrupt Status
00159 #define SSI_MIS_RORMIS          0x00000001  //< SSI Receive Overrun Masked
00160                                             //< Interrupt Status
00161 /*\}*/
00162 
00166 /*\{*/
00167 #define SSI_ICR_RTIC            0x00000002  //< SSI Receive Time-Out Interrupt
00168                                             //< Clear
00169 #define SSI_ICR_RORIC           0x00000001  //< SSI Receive Overrun Interrupt
00170                                             //< Clear
00171 /*\}*/
00172 
00176 /*\{*/
00177 #define SSI_DMACTL_TXDMAE       0x00000002  //< Transmit DMA Enable
00178 #define SSI_DMACTL_RXDMAE       0x00000001  //< Receive DMA Enable
00179 /*\}*/
00180 
00184 /*\{*/
00185 #ifndef DEPRECATED
00186 /*\}*/
00187 
00192 /*\{*/
00193 #define SSI_CR0_SCR             0x0000FF00  //< Serial clock rate
00194 #define SSI_CR0_FRF_MASK        0x00000030  //< Frame format mask
00195 #define SSI_CR0_DSS             0x0000000F  //< Data size select
00196 /*\}*/
00197 
00202 /*\{*/
00203 #define SSI_CPSR_CPSDVSR_MASK   0x000000FF  //< Clock prescale
00204 /*\}*/
00205 
00209 /*\{*/
00210 #define TX_FIFO_SIZE            (8)         //< Number of entries in the TX FIFO
00211 #define RX_FIFO_SIZE            (8)         //< Number of entries in the RX FIFO
00212 /*\}*/
00213 
00219 /*\{*/
00220 #define SSI_INT_TXFF            0x00000008  //< TX FIFO interrupt
00221 #define SSI_INT_RXFF            0x00000004  //< RX FIFO interrupt
00222 #define SSI_INT_RXTO            0x00000002  //< RX timeout interrupt
00223 #define SSI_INT_RXOR            0x00000001  //< RX overrun interrupt
00224 /*\}*/
00225 
00226 #endif /* DEPRECATED */
00227 
00228 #endif /* LM3S_SSI_H */