BeRTOS
at91_tc.h
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00001 
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 
00072 #ifndef AT91_TC_H
00073 #define AT91_TC_H
00074 
00075 
00079 #define TC_TC0_OFF              0x00000000     ///< Channel 0 control register offset.
00080 #define TC_TC1_OFF              0x00000040     ///< Channel 1 control register offset.
00081 #define TC_TC2_OFF              0x00000080     ///< Channel 2 control register offset.
00082 #define TC0_CCR         (*((reg32_t *)(TC_BASE + TC_TC0_OFF))) ///< Channel 0 control register address.
00083 #define TC1_CCR         (*((reg32_t *)(TC_BASE + TC_TC1_OFF))) ///< Channel 1 control register address.
00084 #define TC2_CCR         (*((reg32_t *)(TC_BASE + TC_TC2_OFF))) ///< Channel 2 control register address.
00085 #define TC_CLKEN                         0      ///< Clock enable command.
00086 #define TC_CLKDIS                        1      ///< Clock disable command.
00087 #define TC_SWTRG                         2      ///< Software trigger command.
00088 
00092 #define TC_CMR_OFF              0x00000004      ///< Mode register offset.
00093 #define TC0_CMR         (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CMR_OFF))) ///< Channel 0 mode register address.
00094 #define TC1_CMR         (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CMR_OFF))) ///< Channel 1 mode register address.
00095 #define TC2_CMR         (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CMR_OFF))) ///< Channel 2 mode register address.
00096 
00097 #define TC_CLKS_MASK            0x00000007      ///< Clock selection mask.
00098 #define TC_CLKS_MCK2            0x00000000      ///< Selects MCK / 2.
00099 #define TC_CLKS_MCK8            0x00000001      ///< Selects MCK / 8.
00100 #define TC_CLKS_MCK32           0x00000002      ///< Selects MCK / 32.
00101 #define TC_CLKS_MCK128          0x00000003      ///< Selects MCK / 128.
00102 #define TC_CLKS_MCK1024         0x00000004      ///< Selects MCK / 1024.
00103 #define TC_CLKS_XC0             0x00000005      ///< Selects external clock 0.
00104 #define TC_CLKS_XC1             0x00000006      ///< Selects external clock 1.
00105 #define TC_CLKS_XC2             0x00000007      ///< Selects external clock 2.
00106 
00107 #define TC_CLKI                          3      ///< Increments on falling edge.
00108 
00109 #define TC_BURST_MASK           0x00000030      ///< Burst signal selection mask.
00110 #define TC_BURST_NONE           0x00000000      ///< Clock is not gated by an external signal.
00111 #define TC_BUSRT_XC0            0x00000010      ///< ANDed with external clock 0.
00112 #define TC_BURST_XC1            0x00000020      ///< ANDed with external clock 1.
00113 #define TC_BURST_XC2            0x00000030      ///< ANDed with external clock 2.
00114 
00115 
00116 
00117 #define TC_WAVE                         15      ///< Selects waveform mode.
00118 //To select capture mode you must set TC_WAVE bit to 0.
00119 //#define TC_CAPT                         15      ///< Selects capture mode.
00120 
00124 #define TC_CPCTRG                       14      ///< RC Compare Enable Trigger Enable.
00125 #define TC_LDBSTOP                       6      ///< Counter clock stopped on RB loading.
00126 #define TC_LDBDIS                        7      ///< Counter clock disabled on RB loading.
00127 
00128 #define TC_ETRGEDG_MASK         0x00000300      ///< External trigger edge selection mask.
00129 #define TC_ETRGEDG_RISING_EDGE  0x00000100      ///< Trigger on external rising edge.
00130 #define TC_ETRGEDG_FALLING_EDGE 0x00000200      ///< Trigger on external falling edge.
00131 #define TC_ETRGEDG_BOTH_EDGE    0x00000300      ///< Trigger on both external edges.
00132 
00133 #define TC_ABETRG_MASK          0x00000400      ///< TIOA or TIOB external trigger selection mask.
00134 #define TC_ABETRG_TIOA                  10      ///< TIOA used as an external trigger.
00135 //To use external trigger TIOB you must set TC_ABETRG_TIOA bit to 0.
00136 //#define TC_ABETRG_TIOB                  10      ///< TIOB used as an external trigger.
00137 
00138 
00139 #define TC_LDRA_MASK            0x00030000      ///< RA loading selection mask.
00140 #define TC_LDRA_RISING_EDGE     0x00010000      ///< Load RA on rising edge of TIOA.
00141 #define TC_LDRA_FALLING_EDGE    0x00020000      ///< Load RA on falling edge of TIOA.
00142 #define TC_LDRA_BOTH_EDGE       0x00030000      ///< Load RA on any edge of TIOA.
00143 
00144 #define TC_LDRB_MASK            0x000C0000      ///< RB loading selection mask.
00145 #define TC_LDRB_RISING_EDGE     0x00040000      ///< Load RB on rising edge of TIOA.
00146 #define TC_LDRB_FALLING_EDGE    0x00080000      ///< Load RB on falling edge of TIOA.
00147 #define TC_LDRB_BOTH_EDGE       0x000C0000      ///< Load RB on any edge of TIOA.
00148 
00149 
00153 #define TC_CPCSTOP                       6      ///< Counter clock stopped on RC compare.
00154 #define TC_CPCDIS                        7      ///< Counter clock disabled on RC compare.
00155 
00156 #define TC_EEVTEDG_MASK         0x00000300      ///< External event edge selection mask.
00157 #define TC_EEVTEDG_RISING_EDGE  0x00000100      ///< External event on rising edge..
00158 #define TC_EEVTEDG_FALLING_EDGE 0x00000200      ///< External event on falling edge..
00159 #define TC_EEVTEDG_BOTH_EDGE    0x00000300      ///< External event on any edge..
00160 
00161 #define TC_EEVT_MASK            0x00000C00      ///< External event selection mask.
00162 #define TC_EEVT_TIOB            0x00000000      ///< TIOB selected as external event.
00163 #define TC_EEVT_XC0             0x00000400      ///< XC0 selected as external event.
00164 #define TC_EEVT_XC1             0x00000800      ///< XC1 selected as external event.
00165 #define TC_EEVT_XC2             0x00000C00      ///< XC2 selected as external event.
00166 
00167 #define TC_ENETRG                       12      ///< External event trigger enable.
00168 
00169 #define TC_WAVSEL_MASK          0x00006000      ///< Waveform selection mask.
00170 #define TC_WAVSEL_UP            0x00000000      ///< UP mode whitout automatic trigger on RC compare.
00171 #define TC_WAVSEL_UP_RC_TRG     0x00004000      ///< UP mode whit automatic trigger on RC compare.
00172 #define TC_WAVSEL_UPDOWN        0x00002000      ///< UPDOWN mode whitout automatic trigger on RC compare.
00173 #define TC_WAVSEL_UPDOWN_RC_TRG 0x00003000      ///< UPDOWN mode whit automatic trigger on RC compare.
00174 
00175 
00176 #define TC_ACPA_MASK            0x00030000      ///< Masks RA compare effect on TIOA.
00177 #define TC_ACPA_SET_OUTPUT      0x00010000      ///< RA compare sets TIOA.
00178 #define TC_ACPA_CLEAR_OUTPUT    0x00020000      ///< RA compare clears TIOA.
00179 #define TC_ACPA_TOGGLE_OUTPUT   0x00030000      ///< RA compare toggles TIOA.
00180 
00181 #define TC_ACPC_MASK            0x000C0000      ///< Masks RC compare effect on TIOA.
00182 #define TC_ACPC_SET_OUTPUT      0x00040000      ///< RC compare sets TIOA.
00183 #define TC_ACPC_CLEAR_OUTPUT    0x00080000      ///< RC compare clears TIOA.
00184 #define TC_ACPC_TOGGLE_OUTPUT   0x000C0000      ///< RC compare toggles TIOA.
00185 
00186 #define TC_AEEVT_MASK           0x00300000      ///< Masks external event effect on TIOA.
00187 #define TC_AEEVT_SET_OUTPUT     0x00100000      ///< External event sets TIOA.
00188 #define TC_AEEVT_CLEAR_OUTPUT   0x00200000      ///< External event clears TIOA.
00189 #define TC_AEEVT_TOGGLE_OUTPUT  0x00300000      ///< External event toggles TIOA.
00190 
00191 #define TC_ASWTRG_MASK          0x00C00000      ///< Masks software trigger effect on TIOA.
00192 #define TC_ASWTRG_SET_OUTPUT    0x00400000      ///< Software trigger sets TIOA.
00193 #define TC_ASWTRG_CLEAR_OUTPUT  0x00800000      ///< Software trigger clears TIOA.
00194 #define TC_ASWTRG_TOGGLE_OUTPUT 0x00C00000      ///< Software trigger toggles TIOA.
00195 
00196 #define TC_BCPB_MASK            0x03000000      ///< Masks RB compare effect on TIOB.
00197 #define TC_BCPB_SET_OUTPUT      0x01000000      ///< RB compare sets TIOB.
00198 #define TC_BCPB_CLEAR_OUTPUT    0x02000000      ///< RB compare clears TIOB.
00199 #define TC_BCPB_TOGGLE_OUTPUT   0x03000000      ///< RB compare toggles TIOB.
00200 
00201 #define TC_BCPC_MASK            0x0C000000      ///< Masks RC compare effect on TIOB.
00202 #define TC_BCPC_SET_OUTPUT      0x04000000      ///< RC compare sets TIOB.
00203 #define TC_BCPC_CLEAR_OUTPUT    0x08000000      ///< RC compare clears TIOB.
00204 #define TC_BCPC_TOGGLE_OUTPUT   0x0C000000      ///< RC compare toggles TIOB.
00205 
00206 #define TC_BEEVT_MASK           0x30000000      ///< Masks external event effect on TIOB.
00207 #define TC_BEEVT_SET_OUTPUT     0x10000000      ///< External event sets TIOB.
00208 #define TC_BEEVT_CLEAR_OUTPUT   0x20000000      ///< External event clears TIOB.
00209 #define TC_BEEVT_TOGGLE_OUTPUT  0x30000000      ///< External event toggles TIOB.
00210 
00211 #define TC_BSWTRG_MASK          0xC0000000      ///< Masks software trigger effect on TIOB.
00212 #define TC_BSWTRG_SET_OUTPUT    0x40000000      ///< Software trigger sets TIOB.
00213 #define TC_BSWTRG_CLEAR_OUTPUT  0x80000000      ///< Software trigger clears TIOB.
00214 #define TC_BSWTRG_TOGGLE_OUTPUT 0xC0000000      ///< Software trigger toggles TIOB.
00215 
00219 #define TC_CV_OFF               0x00000010      ///< Counter register value offset.
00220 #define TC0_CV          (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_CV_OFF))) ///< Counter 0 value.
00221 #define TC1_CV          (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_CV_OFF))) ///< Counter 1 value.
00222 #define TC2_CV          (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_CV_OFF))) ///< Counter 2 value.
00223 
00227 #define TC_RA_OFF               0x00000014      ///< Register A offset.
00228 #define TC0_RA          (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RA_OFF))) ///< Channel 0 register A.
00229 #define TC1_RA          (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RA_OFF))) ///< Channel 1 register A.
00230 #define TC2_RA          (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RA_OFF))) ///< Channel 2 register A.
00231 
00232 
00236 #define TC_RB_OFF               0x00000018      ///< Register B offset.
00237 #define TC0_RB           (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RB_OFF))) ///< Channel 0 register B.
00238 #define TC1_RB           (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RB_OFF))) ///< Channel 1 register B.
00239 #define TC2_RB           (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RB_OFF))) ///< Channel 2 register B.
00240 
00241 
00245 #define TC_RC_OFF               0x0000001C      ///< Register C offset.
00246 #define TC0_RC          (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_RC_OFF))) ///< Channel 0 register C.
00247 #define TC1_RC          (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_RC_OFF))) ///< Channel 1 register C.
00248 #define TC2_RC          (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_RC_OFF))) ///< Channel 2 register C.
00249 
00250 
00251 
00255 #define TC_SR_OFF               0x00000020      ///< Status Register offset.
00256 #define TC0_SR          (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_SR_OFF))) ///< Status register address.
00257 #define TC1_SR          (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_SR_OFF))) ///< Status register address.
00258 #define TC2_SR          (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_SR_OFF))) ///< Status register address.
00259 
00260 #define TC_IER_OFF              0x00000024      ///< Interrupt Enable Register offset.
00261 #define TC0_IER         (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IER_OFF))) ///< Channel 0 interrupt enable register address.
00262 #define TC1_IER         (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IER_OFF))) ///< Channel 1 interrupt enable register address.
00263 #define TC2_IER         (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IER_OFF))) ///< Channel 2 interrupt enable register address.
00264 
00265 #define TC_IDR_OFF              0x00000028      ///< Interrupt Disable Register offset.
00266 #define TC0_IDR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IDR_OFF))) ///< Channel 0 interrupt disable register address.
00267 #define TC1_IDR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IDR_OFF))) ///< Channel 1 interrupt disable register address.
00268 #define TC2_IDR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IDR_OFF))) ///< Channel 2 interrupt disable register address.
00269 
00270 #define TC_IMR_OFF              0x0000002C      ///< Interrupt Mask Register offset.
00271 #define TC0_IMR        (*((reg32_t *)(TC_BASE + TC_TC0_OFF + TC_IMR_OFF))) ///< Channel 0 interrupt mask register address.
00272 #define TC1_IMR        (*((reg32_t *)(TC_BASE + TC_TC1_OFF + TC_IMR_OFF))) ///< Channel 1 interrupt mask register address.
00273 #define TC2_IMR        (*((reg32_t *)(TC_BASE + TC_TC2_OFF + TC_IMR_OFF))) ///< Channel 2 interrupt mask register address.
00274 
00275 #define TC_COVFS                         0      ///< Counter overflow flag.
00276 #define TC_LOVRS                         1      ///< Load overrun flag.
00277 #define TC_CPAS                          2      ///< RA compare flag.
00278 #define TC_CPBS                          3      ///< RB compare flag.
00279 #define TC_CPCS                          4      ///< RC compare flag.
00280 #define TC_LDRAS                         5      ///< RA loading flag.
00281 #define TC_LDRBS                         6      ///< RB loading flag.
00282 #define TC_ETRGS                         7      ///< External trigger flag.
00283 #define TC_CLKSTA                       16      ///< Clock enable flag.
00284 #define TC_MTIOA                        17      ///< TIOA flag.
00285 #define TC_MTIOB                        18      ///< TIOB flag.
00286 
00287 
00291 #define TC_BCR_OFF              0x000000C0      ///< Block control register offset.
00292 #define TC_BCR         (*((reg32_t *)(TC_BASE + TC_BCR_OFF))) ///< Block control register address.
00293 #define TC_SYNC                          0      ///< Synchronisation trigger
00294 
00295 
00299 #define TC_BMR_OFF              0x000000C4      ///< Block mode register offset.
00300 #define TC_BMR         (*((reg32_t *)(TC_BASE + TC_BMR_OFF))) ///< Block mode register address.
00301 #define TC_TC0XC0S              0x00000003      ///< External clock signal 0 selection mask.
00302 #define TC_TCLK0XC0             0x00000000      ///< Selects TCLK0.
00303 #define TC_NONEXC0              0x00000001      ///< None selected.
00304 #define TC_TIOA1XC0             0x00000002      ///< Selects TIOA1.
00305 #define TC_TIOA2XC0             0x00000003      ///< Selects TIOA2.
00306 
00307 #define TC_TC1XC1S              0x0000000C      ///< External clock signal 1 selection mask.
00308 #define TC_TCLK1XC1             0x00000000      ///< Selects TCLK1.
00309 #define TC_NONEXC1              0x00000004      ///< None selected.
00310 #define TC_TIOA0XC1             0x00000008      ///< Selects TIOA0.
00311 #define TC_TIOA2XC1             0x0000000C      ///< Selects TIOA2.
00312 
00313 #define TC_TC2XC2S              0x00000030      ///< External clock signal 2 selection mask.
00314 #define TC_TCLK2XC2             0x00000000      ///< Selects TCLK2.
00315 #define TC_NONEXC2              0x00000010      ///< None selected.
00316 #define TC_TIOA0XC2             0x00000020      ///< Selects TIOA0.
00317 #define TC_TIOA1XC2             0x00000030      ///< Selects TIOA1.
00318 
00319 
00320 #endif /* AT91_TC_H */