BeRTOS
|
00001 00036 #ifndef STM32_MEMMAP_H 00037 #define STM32_MEMMAP_H 00038 00039 /* Peripheral and SRAM base address in the alias region */ 00040 #define PERIPH_BB_BASE (0x42000000) 00041 #define SRAM_BB_BASE (0x22000000) 00042 00043 /* Peripheral and SRAM base address in the bit-band region */ 00044 #define SRAM_BASE (0x20000000) 00045 #define PERIPH_BASE (0x40000000) 00046 00047 /* Flash refisters base address */ 00048 #define FLASH_BASE (0x40022000) 00049 /* Flash Option Bytes base address */ 00050 #define OB_BASE (0x1FFFF800) 00051 00052 /* Peripheral memory map */ 00053 #define APB1PERIPH_BASE (PERIPH_BASE) 00054 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) 00055 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) 00056 00057 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) 00058 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) 00059 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) 00060 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) 00061 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) 00062 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) 00063 #define RTC_BASE (APB1PERIPH_BASE + 0x2800) 00064 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) 00065 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) 00066 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) 00067 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) 00068 #define USART2_BASE (APB1PERIPH_BASE + 0x4400) 00069 #define USART3_BASE (APB1PERIPH_BASE + 0x4800) 00070 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) 00071 #define UART5_BASE (APB1PERIPH_BASE + 0x5000) 00072 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) 00073 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) 00074 #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) 00075 #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) 00076 #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) 00077 #define PWR_BASE (APB1PERIPH_BASE + 0x7000) 00078 #define DAC_BASE (APB1PERIPH_BASE + 0x7400) 00079 #define CEC_BASE (APB1PERIPH_BASE + 0x7800) 00080 00081 #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) 00082 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) 00083 #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) 00084 #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) 00085 #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) 00086 #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) 00087 #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) 00088 #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) 00089 #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) 00090 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) 00091 #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) 00092 #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) 00093 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) 00094 #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) 00095 #define USART1_BASE (APB2PERIPH_BASE + 0x3800) 00096 #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) 00097 #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) 00098 #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) 00099 #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) 00100 00101 #define SDIO_BASE (PERIPH_BASE + 0x18000) 00102 00103 00104 #define DMA1_BASE (AHBPERIPH_BASE + 0X0000) 00105 #define DMA1_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0008) 00106 #define DMA1_CHANNEL2_BASE (AHBPERIPH_BASE + 0X001C) 00107 #define DMA1_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0030) 00108 #define DMA1_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0044) 00109 #define DMA1_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0058) 00110 #define DMA1_CHANNEL6_BASE (AHBPERIPH_BASE + 0X006C) 00111 #define DMA1_CHANNEL7_BASE (AHBPERIPH_BASE + 0X0080) 00112 #define DMA2_BASE (AHBPERIPH_BASE + 0X0400) 00113 #define DMA2_CHANNEL1_BASE (AHBPERIPH_BASE + 0X0408) 00114 #define DMA2_CHANNEL2_BASE (AHBPERIPH_BASE + 0X041C) 00115 #define DMA2_CHANNEL3_BASE (AHBPERIPH_BASE + 0X0430) 00116 #define DMA2_CHANNEL4_BASE (AHBPERIPH_BASE + 0X0444) 00117 #define DMA2_CHANNEL5_BASE (AHBPERIPH_BASE + 0X0458) 00118 #define RCC_BASE (AHBPERIPH_BASE + 0X1000) 00119 #define CRC_BASE (AHBPERIPH_BASE + 0X3000) 00120 00121 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) ///< Flash registers base address 00122 00123 #define ETH_BASE (AHBPERIPH_BASE + 0x8000) 00124 #define ETH_MAC_BASE (ETH_BASE) 00125 #define ETH_MMC_BASE (ETH_BASE + 0x0100) 00126 #define ETH_PTP_BASE (ETH_BASE + 0x0700) 00127 #define ETH_DMA_BASE (ETH_BASE + 0x1000) 00128 00129 #define FSMC_BANK1_R_BASE (FSMC_R_BASE + 0x0000) ///< FSMC Bank1 registers base address 00130 #define FSMC_BANK1E_R_BASE (FSMC_R_BASE + 0x0104) ///< FSMC Bank1E registers base address 00131 #define FSMC_BANK2_R_BASE (FSMC_R_BASE + 0x0060) ///< FSMC Bank2 registers base address 00132 #define FSMC_BANK3_R_BASE (FSMC_R_BASE + 0x0080) ///< FSMC Bank3 registers base address 00133 #define FSMC_BANK4_R_BASE (FSMC_R_BASE + 0x00A0) ///< FSMC Bank4 registers base address 00134 00135 #define DBGMCU_BASE ((uint32_t)0xE0042000) ///< Debug MCU registers base address 00136 00137 /* System Control Space memory map */ 00138 #define SCS_BASE (0xE000E000) 00139 00140 #define SYSTICK_BASE (SCS_BASE + 0x0010) 00141 #define NVIC_BASE (SCS_BASE + 0x0100) 00142 #define SCB_BASE (SCS_BASE + 0x0D00) 00143 00144 #endif /* STM32_MEMMAP_H */