BeRTOS
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00001 00038 #ifndef CLOCK_STM32_H 00039 #define CLOCK_STM32_H 00040 00041 00042 #include <cfg/compiler.h> 00043 00044 /* RCC registers bit address */ 00045 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) 00046 00050 /*\{*/ 00051 /* Alias word address of HSION bit */ 00052 #define CR_OFFSET (RCC_OFFSET + 0x00) 00053 #define HSION_BITNUMBER 0x00 00054 #define CR_HSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BITNUMBER * 4))) 00055 00056 /* Alias word address of PLLON bit */ 00057 #define PLLON_BITNUMBER 0x18 00058 #define CR_PLLON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BITNUMBER * 4))) 00059 00060 /* Alias word address of CSSON bit */ 00061 #define CSSON_BITNUMBER 0x13 00062 #define CR_CSSON_BB ((reg32_t *)(PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BITNUMBER * 4))) 00063 /*\}*/ 00064 00068 /*\{*/ 00069 /* Alias word address of USBPRE bit */ 00070 #define CFGR_OFFSET (RCC_OFFSET + 0x04) 00071 #define USBPRE_BITNUMBER 0x16 00072 #define CFGR_USBPRE_BB ((reg32_t *)(PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BITNUMBER * 4))) 00073 /*\}*/ 00074 00078 /*\{*/ 00079 /* Alias word address of RTCEN bit */ 00080 #define BDCR_OFFSET (RCC_OFFSET + 0x20) 00081 #define RTCEN_BITNUMBER 0x0F 00082 #define BDCR_RTCEN_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BITNUMBER * 4))) 00083 00084 /* Alias word address of BDRST bit */ 00085 #define BDRST_BITNUMBER 0x10 00086 #define BDCR_BDRST_BB ((reg32_t *)(PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BITNUMBER * 4))) 00087 /*\}*/ 00088 00092 /*\{*/ 00093 /* Alias word address of LSION bit */ 00094 #define CSR_OFFSET (RCC_OFFSET + 0x24) 00095 #define LSION_BITNUMBER 0x00 00096 #define CSR_LSION_BB ((reg32_t *)(PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BITNUMBER * 4))) 00097 /*\}*/ 00098 00102 /*\{*/ 00103 /* CR register bit mask */ 00104 #define CR_HSEBYP_RESET (0xFFFBFFFF) 00105 #define CR_HSEBYP_SET (0x00040000) 00106 #define CR_HSEON_RESET (0xFFFEFFFF) 00107 #define CR_HSEON_SET (0x00010000) 00108 #define CR_HSITRIM_MASK (0xFFFFFF07) 00109 00110 /* CFGR register bit mask */ 00111 #define CFGR_PLL_MASK (0xFFC0FFFF) 00112 #define CFGR_PLLMull_MASK (0x003C0000) 00113 #define CFGR_PLLSRC_MASK (0x00010000) 00114 #define CFGR_PLLXTPRE_MASK (0x00020000) 00115 #define CFGR_SWS_MASK (0x0000000C) 00116 #define CFGR_SW_MASK (0xFFFFFFFC) 00117 #define CFGR_HPRE_RESET_MASK (0xFFFFFF0F) 00118 #define CFGR_HPRE_SET_MASK (0x000000F0) 00119 #define CFGR_PPRE1_RESET_MASK (0xFFFFF8FF) 00120 #define CFGR_PPRE1_SET_MASK (0x00000700) 00121 #define CFGR_PPRE2_RESET_MASK (0xFFFFC7FF) 00122 #define CFGR_PPRE2_SET_MASK (0x00003800) 00123 #define CFGR_ADCPRE_RESET_MASK (0xFFFF3FFF) 00124 #define CFGR_ADCPRE_SET_MASK (0x0000C000) 00125 00126 /* CSR register bit mask */ 00127 #define CSR_RVMF_SET (0x01000000) 00128 00129 /* RCC Flag MASK */ 00130 #define FLAG_MASK (0x1F) 00131 00132 /* Typical VALUE of the HSI in Hz */ 00133 #define HSI_VALUE (8000000) 00134 00135 /* BDCR register base address */ 00136 #define BDCR_BASE (PERIPH_BASE + BDCR_OFFSET) 00137 00138 /* RCC Flag */ 00139 #define RCC_FLAG_HSIRDY (0x20) 00140 #define RCC_FLAG_HSERDY (0x31) 00141 #define RCC_FLAG_PLLRDY (0x39) 00142 #define RCC_FLAG_LSERDY (0x41) 00143 #define RCC_FLAG_LSIRDY (0x61) 00144 #define RCC_FLAG_PINRST (0x7A) 00145 #define RCC_FLAG_PORRST (0x7B) 00146 #define RCC_FLAG_SFTRST (0x7C) 00147 #define RCC_FLAG_IWDGRST (0x7D) 00148 #define RCC_FLAG_WWDGRST (0x7E) 00149 #define RCC_FLAG_LPWRRST (0x7F) 00150 00151 /* System clock source */ 00152 #define RCC_SYSCLK_HSI (0x00000000) 00153 #define RCC_SYSCLK_HSE (0x00000001) 00154 #define RCC_SYSCLK_PLLCLK (0x00000002) 00155 00156 /* PLL entry clock source */ 00157 #define RCC_PLL_HSI_DIV2 (0x00000000) 00158 #define RCC_PLL_HSE_DIV1 (0x00010000) 00159 #define RCC_PLL_HSE_DIV2 (0x00030000) 00160 00161 /* PLL multiplication factor */ 00162 #define RCC_PLLMUL_2 (0x00000000) 00163 #define RCC_PLLMUL_3 (0x00040000) 00164 #define RCC_PLLMUL_4 (0x00080000) 00165 #define RCC_PLLMUL_5 (0x000C0000) 00166 #define RCC_PLLMUL_6 (0x00100000) 00167 #define RCC_PLLMUL_7 (0x00140000) 00168 #define RCC_PLLMUL_8 (0x00180000) 00169 #define RCC_PLLMUL_9 (0x001C0000) 00170 #define RCC_PLLMUL_10 (0x00200000) 00171 #define RCC_PLLMUL_11 (0x00240000) 00172 #define RCC_PLLMUL_12 (0x00280000) 00173 #define RCC_PLLMUL_13 (0x002C0000) 00174 #define RCC_PLLMUL_14 (0x00300000) 00175 #define RCC_PLLMUL_15 (0x00340000) 00176 #define RCC_PLLMUL_16 (0x00380000) 00177 00178 /* APB1/APB2 clock source */ 00179 #define RCC_HCLK_DIV1 (0x00000000) 00180 #define RCC_HCLK_DIV2 (0x00000400) 00181 #define RCC_HCLK_DIV4 (0x00000500) 00182 #define RCC_HCLK_DIV8 (0x00000600) 00183 #define RCC_HCLK_DIV16 (0x00000700) 00184 00185 /* USB clock source */ 00186 #define RCC_USBCLK_PLLCLK_1DIV5 (0x00) 00187 #define RCC_USBCLK_PLLCLK_DIV1 (0x01) 00188 00189 /* ADC clock source */ 00190 #define RCC_PCLK2_DIV2 (0x00000000) 00191 #define RCC_PCLK2_DIV4 (0x00004000) 00192 #define RCC_PCLK2_DIV6 (0x00008000) 00193 #define RCC_PCLK2_DIV8 (0x0000C000) 00194 00195 /* AHB clock source */ 00196 #define RCC_SYSCLK_DIV1 (0x00000000) 00197 #define RCC_SYSCLK_DIV2 (0x00000080) 00198 #define RCC_SYSCLK_DIV4 (0x00000090) 00199 #define RCC_SYSCLK_DIV8 (0x000000A0) 00200 #define RCC_SYSCLK_DIV16 (0x000000B0) 00201 #define RCC_SYSCLK_DIV64 (0x000000C0) 00202 #define RCC_SYSCLK_DIV128 (0x000000D0) 00203 #define RCC_SYSCLK_DIV256 (0x000000E0) 00204 #define RCC_SYSCLK_DIV512 (0x000000F0) 00205 /*\}*/ 00206 00210 /*\{*/ 00211 #define RCC_APB1_TIM2 (0x00000001) 00212 #define RCC_APB1_TIM3 (0x00000002) 00213 #define RCC_APB1_TIM4 (0x00000004) 00214 #define RCC_APB1_WWDG (0x00000800) 00215 #define RCC_APB1_SPI2 (0x00004000) 00216 #define RCC_APB1_USART2 (0x00020000) 00217 #define RCC_APB1_USART3 (0x00040000) 00218 #define RCC_APB1_I2C1 (0x00200000) 00219 #define RCC_APB1_I2C2 (0x00400000) 00220 #define RCC_APB1_USB (0x00800000) 00221 #define RCC_APB1_CAN (0x02000000) 00222 #define RCC_APB1_BKP (0x08000000) 00223 #define RCC_APB1_PWR (0x10000000) 00224 #define RCC_APB1_ALL (0x1AE64807) 00225 /*\}*/ 00226 00230 /*\{*/ 00231 #define RCC_APB2_AFIO (0x00000001) 00232 #define RCC_APB2_GPIOA (0x00000004) 00233 #define RCC_APB2_GPIOB (0x00000008) 00234 #define RCC_APB2_GPIOC (0x00000010) 00235 #define RCC_APB2_GPIOD (0x00000020) 00236 #define RCC_APB2_GPIOE (0x00000040) 00237 #define RCC_APB2_ADC1 (0x00000200) 00238 #define RCC_APB2_ADC2 (0x00000400) 00239 #define RCC_APB2_TIM1 (0x00000800) 00240 #define RCC_APB2_SPI1 (0x00001000) 00241 #define RCC_APB2_USART1 (0x00004000) 00242 #define RCC_APB2_ALL (0x00005E7D) 00243 00247 #define RCC_BDCR_LSEON (0x00000001) 00248 #define RCC_BDCR_LSERDY (0x00000002) 00249 #define RCC_BDCR_RTCSEL (0x00000300) 00250 #define RCC_BDCR_RTCEN (0x00008000) 00251 /*\}*/ 00252 00253 /* Crystal frequency of the main oscillator (8MHz) */ 00254 #define PLL_VCO 8000000 00255 00256 /* Reset and Clock Controller registers */ 00257 struct RCC 00258 { 00259 reg32_t CR; 00260 reg32_t CFGR; 00261 reg32_t CIR; 00262 reg32_t APB2RSTR; 00263 reg32_t APB1RSTR; 00264 reg32_t AHBENR; 00265 reg32_t APB2ENR; 00266 reg32_t APB1ENR; 00267 reg32_t BDCR; 00268 reg32_t CSR; 00269 }; 00270 00271 /* RCC registers base */ 00272 extern struct RCC *RCC; 00273 00274 void clock_init(void); 00275 00276 #endif /* CLOCK_STM32_h */