BeRTOS
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00001 00040 /* 00041 * Copyright (C) 2006 by egnite Software GmbH. All rights reserved. 00042 * 00043 * Redistribution and use in source and binary forms, with or without 00044 * modification, are permitted provided that the following conditions 00045 * are met: 00046 * 00047 * 1. Redistributions of source code must retain the above copyright 00048 * notice, this list of conditions and the following disclaimer. 00049 * 2. Redistributions in binary form must reproduce the above copyright 00050 * notice, this list of conditions and the following disclaimer in the 00051 * documentation and/or other materials provided with the distribution. 00052 * 3. Neither the name of the copyright holders nor the names of 00053 * contributors may be used to endorse or promote products derived 00054 * from this software without specific prior written permission. 00055 * 00056 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00057 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00058 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00059 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00060 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00061 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00062 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00063 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00064 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00065 * OR TORT (*((reg32_t *)(INCLUDING NEGLIGENCE OR OTHERWISE))) ARISING IN ANY WAY OUT OF 00066 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00067 * SUCH DAMAGE. 00068 * 00069 * For additional information see http://www.ethernut.de/ 00070 */ 00071 00072 #ifndef AT91_TWI_H 00073 #define AT91_TWI_H 00074 00075 00080 #define TWI_CR_OFF 0x00000000 ///< Control register offset. 00081 #define TWI_CR (*((reg32_t *)(TWI_BASE + TWI_CR_OFF))) ///< Control register address. 00082 #define TWI_START 0 ///< Send start condition. 00083 #define TWI_STOP 1 ///< Send stop condition. 00084 #define TWI_MSEN 2 ///< Enable master mode. 00085 #define TWI_MSDIS 3 ///< Disable master mode. 00086 /* 00087 #define TWI_SVEN 4 ///< Enable slave mode. 00088 #define TWI_SVDIS 5 ///< Disable slave mode. 00089 */ 00090 #define TWI_SWRST 7 ///< Software reset. 00091 /*\}*/ 00092 00097 #define TWI_MMR_OFF 0x00000004 ///< Master mode register offset. 00098 #define TWI_MMR (*((reg32_t *)(TWI_BASE + TWI_MMR_OFF))) ///< Master mode register address. 00099 #define TWI_IADRSZ_SHIFT 8 ///< Internal device address size shift. 00100 #define TWI_IADRSZ 0x00000300 ///< Internal device address size mask. 00101 #define TWI_IADRSZ_NONE 0x00000000 ///< No internal device address. 00102 #define TWI_IADRSZ_1BYTE 0x00000100 ///< One byte internal device address. 00103 #define TWI_IADRSZ_2BYTE 0x00000200 ///< Two byte internal device address. 00104 #define TWI_IADRSZ_3BYTE 0x00000300 ///< Three byte internal device address. 00105 #define TWI_MREAD 12 ///< Master read direction. 00106 #define TWI_DADR 0x007F0000 ///< Device address mask. 00107 #define TWI_DADR_SHIFT 16 ///< Device address LSB. 00108 /*\}*/ 00109 00114 #define TWI_IADR_OFF 0x0000000C ///< Internal address register offset. 00115 #define TWI_IADR (*((reg32_t *)(TWI_BASE + TWI_IADR_OFF))) ///< Internal address register address. 00116 #define TWI_IADR_MASK 0x00FFFFFF ///< Internal address mask. 00117 #define TWI_IADR_SHIFT 0 ///< Internal address LSB. 00118 /*\}*/ 00119 00124 #define TWI_CWGR_OFF 0x00000010 ///< Clock waveform generator register offset. 00125 #define TWI_CWGR (*((reg32_t *)(TWI_BASE + TWI_CWGR_OFF))) ///< Clock waveform generator register address. 00126 #define TWI_CLDIV 0x000000FF ///< Clock low divider mask. 00127 #define TWI_CLDIV_SHIFT 0 ///< Clock low divider LSB. 00128 #define TWI_CHDIV 0x0000FF00 ///< Clock high divider mask. 00129 #define TWI_CHDIV_SHIFT 8 ///< Clock high divider LSB. 00130 #define TWI_CKDIV 0x00070000 ///< Clock divider mask. 00131 #define TWI_CKDIV_SHIFT 16 ///< Clock divider LSB. 00132 /*\}*/ 00133 00138 #define TWI_SR_OFF 0x00000020 ///< Status register offset. 00139 #define TWI_SR (*((reg32_t *)(TWI_BASE + TWI_SR_OFF))) ///< Status register address. 00140 00141 #define TWI_IER_OFF 0x00000024 ///< Interrupt enable register offset. 00142 #define TWI_IER (*((reg32_t *)(TWI_BASE + TWI_IER_OFF))) ///< Interrupt enable register address. 00143 00144 #define TWI_IDR_OFF 0x00000028 ///< Interrupt disable register offset. 00145 #define TWI_IDR (*((reg32_t *)(TWI_BASE + TWI_IDR_OFF))) ///< Interrupt disable register address. 00146 00147 #define TWI_IMR_OFF 0x0000002C ///< Interrupt mask register offset. 00148 #define TWI_IMR (*((reg32_t *)(TWI_BASE + TWI_IMR_OFF))) ///< Interrupt mask register address. 00149 00150 #define TWI_TXCOMP 0 ///< Transmission completed. 00151 #define TWI_RXRDY 1 ///< Receive holding register ready. 00152 #define TWI_TXRDY 2 ///< Transmit holding register ready. 00153 00154 /* 00155 #define TWI_SVREAD 0x00000008 ///< Slave read. 00156 #define TWI_SVACC 0x00000010 ///< Slave access. 00157 #define TWI_GACC 0x00000020 ///< General call access. 00158 */ 00159 00160 #if CPU_ARM_SAM7X 00161 #define TWI_OVRE 6 ///< Overrun error. 00162 #define TWI_UNRE 7 ///< Underrun error. 00163 #endif 00164 00165 #define TWI_NACK 8 ///< Not acknowledged. 00166 /* 00167 #define TWI_ARBLST 0x00000200 ///< Arbitration lost. 00168 #define TWI_SCLWS 0x00000400 ///< Clock wait state. 00169 #define TWI_EOSACC 0x00000800 ///< End of slave access. 00170 */ 00171 /*\}*/ 00172 00177 #define TWI_RHR_OFF 0x00000030 ///< Receive holding register offset. 00178 #define TWI_RHR (*((reg32_t *)(TWI_BASE + TWI_RHR_OFF))) ///< Receive holding register address. 00179 /*\}*/ 00180 00185 #define TWI_THR_OFF 0x00000034 ///< Transmit holding register offset. 00186 #define TWI_THR (*((reg32_t *)(TWI_BASE + TWI_THR_OFF))) ///< Transmit holding register address. 00187 /*\}*/ 00188 00189 00190 #endif /* AT91_TWI_H */