BeRTOS
sam3_usart.h
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00001 
00039 /*
00040  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00041  *
00042  * Redistribution and use in source and binary forms, with or without
00043  * modification, are permitted provided that the following conditions
00044  * are met:
00045  *
00046  * 1. Redistributions of source code must retain the above copyright
00047  *    notice, this list of conditions and the following disclaimer.
00048  * 2. Redistributions in binary form must reproduce the above copyright
00049  *    notice, this list of conditions and the following disclaimer in the
00050  *    documentation and/or other materials provided with the distribution.
00051  * 3. Neither the name of the copyright holders nor the names of
00052  *    contributors may be used to endorse or promote products derived
00053  *    from this software without specific prior written permission.
00054  *
00055  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00056  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00057  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00058  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00059  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00060  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00061  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00062  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00063  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00064  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00065  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00066  * SUCH DAMAGE.
00067  *
00068  * For additional information see http://www.ethernut.de/
00069  */
00070 
00071 #ifndef SAM3_USART_H
00072 #define SAM3_USART_H
00073 
00077 #if CPU_CM3_SAM3N
00078     #define USART0_BASE  0x40024000
00079     #define USART1_BASE  0x40028000
00080 #elif CPU_CM3_SAM3U
00081     #define USART0_BASE  0x40090000
00082     #define USART1_BASE  0x40094000
00083     #define USART2_BASE  0x40098000
00084     #define USART3_BASE  0x4009C000
00085 #elif CPU_CM3_SAM3X
00086     #define USART0_BASE  0x40098000
00087     #define USART1_BASE  0x4009C000
00088     #define USART2_BASE  0x400A0000
00089     #define USART3_BASE  0x400A4000
00090 #endif
00091 
00095 /*\{*/
00096 #define US_CR_OFF               0x00000000      ///< USART control register offset.
00097 #define US0_CR  (*((reg32_t *)(USART0_BASE + US_CR_OFF)))       ///< Channel 0 control register address.
00098 #define US1_CR  (*((reg32_t *)(USART1_BASE + US_CR_OFF)))       ///< Channel 1 control register address.
00099 #define US_RSTRX                         2      ///< Reset receiver.
00100 #define US_RSTTX                         3      ///< Reset transmitter.
00101 #define US_RXEN                          4      ///< Receiver enable.
00102 #define US_RXDIS                         5      ///< Receiver disable.
00103 #define US_TXEN                          6      ///< Transmitter enable.
00104 #define US_TXDIS                         7      ///< Transmitter disable.
00105 #define US_RSTSTA                        8      ///< Reset status bits.
00106 #define US_STTBRK                        9      ///< Start break.
00107 #define US_STPBRK                        10     ///< Stop break.
00108 #define US_STTTO                         11     ///< Start timeout.
00109 #define US_SENDA                         12     ///< Send next byte with address bit set.
00110 #define US_RSTIT                         13     ///< Reset interations.
00111 #define US_RSTNAK                        14     ///< Reset non acknowledge.
00112 #define US_RETTO                         15     ///< Rearm time out.
00113 #define US_DTREN                         16     ///< Data terminal ready enable.
00114 #define US_DTRDIS                        17     ///< Data terminal ready disable.
00115 #define US_RTSEN                         18     ///< Request to send enable.
00116 #define US_RTSDIS                        19     ///< Request to send disable.
00117 /*\}*/
00118 
00122 /*\{*/
00123 #define US_MR_OFF               0x00000004      ///< USART mode register offset.
00124 #define US0_MR  (*((reg32_t *)(USART0_BASE + US_MR_OFF)))       ///< Channel 0 mode register address.
00125 #define US1_MR  (*((reg32_t *)(USART1_BASE + US_MR_OFF)))       ///< Channel 1 mode register address.
00126 
00127 #define US_USART_MODE_MASK      0x0000000F      ///< USART mode mask.
00128 #define US_USART_MODE_NORMA     0x00000000      ///< Normal.
00129 #define US_USART_MODE_RS485     0x00000001      ///< RS485.
00130 #define US_USART_MODE_HW_HDSH   0x00000002      ///< Hardware handshaking.
00131 #define US_USART_MODE_MODEM     0x00000003      ///< Modem.
00132 #define US_USART_MODE_ISO7816T0 0x00000004      ///< ISO7816 protocol: T=0.
00133 #define US_USART_MODE_ISO7816T1 0x00000006      ///< ISO7816 protocol: T=1.
00134 #define US_USART_MODE_IRDA      0x00000008      ///< IrDA.
00135 
00136 #define US_CLKS_MASK            0x00000030      ///< Clock selection mask.
00137 #define US_CLKS_MCK             0x00000000      ///< Master clock.
00138 #define US_CLKS_MCK8            0x00000010      ///< Master clock divided by 8.
00139 #define US_CLKS_SCK             0x00000020      ///< External clock.
00140 #define US_CLKS_SLCK            0x00000030      ///< Slow clock.
00141 
00142 #define US_CHRL_MASK            0x000000C0      ///< Masks data length.
00143 #define US_CHRL_5               0x00000000      ///< 5 data bits.
00144 #define US_CHRL_6               0x00000040      ///< 6 data bits.
00145 #define US_CHRL_7               0x00000080      ///< 7 data bits.
00146 #define US_CHRL_8               0x000000C0      ///< 8 data bits.
00147 
00148 #define US_SYNC                          8      ///< Synchronous mode enable.
00149 
00150 #define US_PAR_MASK             0x00000E00      ///< Parity mode mask.
00151 #define US_PAR_EVEN             0x00000000      ///< Even parity.
00152 #define US_PAR_ODD              0x00000200      ///< Odd parity.
00153 #define US_PAR_SPACE            0x00000400      ///< Space parity.
00154 #define US_PAR_MARK             0x00000600      ///< Marked parity.
00155 #define US_PAR_NO               0x00000800      ///< No parity.
00156 #define US_PAR_MULTIDROP        0x00000C00      ///< Multi-drop mode.
00157 
00158 #define US_NBSTOP_MASK          0x00003000      ///< Masks stop bit length.
00159 #define US_NBSTOP_1             0x00000000      ///< 1 stop bit.
00160 #define US_NBSTOP_1_5           0x00001000      ///< 1.5 stop bits.
00161 #define US_NBSTOP_2             0x00002000      ///< 2 stop bits.
00162 
00163 #define US_CHMODE_MASK              0x0000C000  ///< Channel mode mask.
00164 #define US_CHMODE_NORMAL            0x00000000  ///< Normal mode.
00165 #define US_CHMODE_AUTOMATIC_ECHO    0x00004000  ///< Automatic echo.
00166 #define US_CHMODE_LOCAL_LOOPBACK    0x00008000  ///< Local loopback.
00167 #define US_CHMODE_REMOTE_LOOPBACK   0x0000C000  ///< Remote loopback.
00168 
00169 #define US_MSBF                         16      ///< Bit order.
00170 #define US_MODE9                        17      ///< 9 bit mode.
00171 #define US_CLKO                         18      ///< Clock output select.
00172 #define US_OVER                         19      ///< Oversampling mode.
00173 #define US_INACK                        20      ///< Inhibit non acknowledge.
00174 #define US_DSNACK                       21      ///< Disable successive nack.
00175 
00176 #define US_MAX_INTERATION_MASK      0x07000000  ///< Max numer of interation in mode ISO7816 T=0.
00177 
00178 #define US_FILTER                       28      ///< Infrared receive line filter.
00179 
00180 /*\}*/
00181 
00185 /*\{*/
00186 #define US_IER_OFF              0x00000008      ///< USART interrupt enable register offset.
00187 #define US0_IER (*((reg32_t *)(USART0_BASE + US_IER_OFF)))      ///< Channel 0 interrupt enable register address.
00188 #define US1_IER (*((reg32_t *)(USART1_BASE + US_IER_OFF)))      ///< Channel 1 interrupt enable register address.
00189 
00190 #define US_IDR_OFF              0x0000000C      ///< USART interrupt disable register offset.
00191 #define US0_IDR (*((reg32_t *)(USART0_BASE + US_IDR_OFF)))      ///< Channel 0 interrupt disable register address.
00192 #define US1_IDR (*((reg32_t *)(USART1_BASE + US_IDR_OFF)))      ///< Channel 1 interrupt disable register address.
00193 
00194 #define US_IMR_OFF              0x00000010      ///< USART interrupt mask register offset.
00195 #define US0_IMR (*((reg32_t *)(USART0_BASE + US_IMR_OFF)))      ///< Channel 0 interrupt mask register address.
00196 #define US1_IMR (*((reg32_t *)(USART1_BASE + US_IMR_OFF)))      ///< Channel 1 interrupt mask register address.
00197 
00198 #define US_CSR_OFF              0x00000014      ///< USART status register offset.
00199 #define US0_CSR (*((reg32_t *)(USART0_BASE + US_CSR_OFF)))      ///< Channel 0 status register address.
00200 #define US1_CSR (*((reg32_t *)(USART1_BASE + US_CSR_OFF)))      ///< Channel 1 status register address.
00201 #define US_CSR_RI                       20      ///< Image of RI input.
00202 #define US_CSR_DSR                      21      ///< Image of DSR input.
00203 #define US_CSR_DCD                      22      ///< Image of DCD input.
00204 #define US_CSR_CTS                      23      ///< Image of CTS input.
00205 
00206 #define US_RXRDY                         0      ///< Receiver ready.
00207 #define US_TXRDY                         1      ///< Transmitter ready.
00208 #define US_RXBRK                         2      ///< Receiver break.
00209 #define US_ENDRX                         3      ///< End of receiver PDC transfer.
00210 #define US_ENDTX                         4      ///< End of transmitter PDC transfer.
00211 #define US_OVRE                          5      ///< Overrun error.
00212 #define US_FRAME                         6      ///< Framing error.
00213 #define US_PARE                          7      ///< Parity error.
00214 #define US_TIMEOUT                       8      ///< Receiver timeout.
00215 #define US_TXEMPTY                       9      ///< Transmitter empty.
00216 #define US_ITERATION                    10      ///< Iteration interrupt enable.
00217 #define US_TXBUFE                       11      ///< Buffer empty interrupt enable.
00218 #define US_RXBUFF                       12      ///< Buffer full interrupt enable.
00219 #define US_NACK                         13      ///< Non acknowledge interrupt enable.
00220 #define US_RIIC                         16      ///< Ring indicator input change enable.
00221 #define US_DSRIC                        17      ///< Data set ready input change enable.
00222 #define US_DCDIC                        18      ///< Data carrier detect input change interrupt enable.
00223 #define US_CTSIC                        19      ///< Clear to send input change interrupt enable.
00224 
00228 /*\{*/
00229 #define US_RHR_OFF              0x00000018      ///< USART receiver holding register offset.
00230 #define US0_RHR (*((reg32_t *)(USART0_BASE + US_RHR_OFF)))      ///< Channel 0 receiver holding register address.
00231 #define US1_RHR (*((reg32_t *)(USART1_BASE + US_RHR_OFF)))      ///< Channel 1 receiver holding register address.
00232 #define US_RHR_RXCHR_MASK       0x000001FF      ///< Last char received if US_RXRDY is set.
00233 #define US_RHR_RXSYNH                   15      ///< Received sync.
00234 /*\}*/
00235 
00239 /*\{*/
00240 #define US_THR_OFF              0x0000001C      ///< USART transmitter holding register offset.
00241 #define US0_THR (*((reg32_t *)(USART0_BASE + US_THR_OFF)))      ///< Channel 0 transmitter holding register address.
00242 #define US1_THR (*((reg32_t *)(USART1_BASE + US_THR_OFF)))      ///< Channel 1 transmitter holding register address.
00243 #define US_THR_TXCHR_MASK       0x000001FF      ///< Next char to be trasmitted.
00244 #define US_THR_TXSYNH                   15      ///< Sync field to be trasmitted.
00245 /*\}*/
00246 
00250 /*\{*/
00251 #define US_BRGR_OFF             0x00000020      ///< USART baud rate register offset.
00252 #define US0_BRGR (*((reg32_t *)(USART0_BASE + US_BRGR_OFF)))    ///< Channel 0 baud rate register address.
00253 #define US1_BRGR (*((reg32_t *)(USART1_BASE + US_BRGR_OFF)))    ///< Channel 1 baud rate register address.
00254 /*\}*/
00255 
00259 /*\{*/
00260 #define US_RTOR_OFF             0x00000024      ///< USART receiver timeout register offset.
00261 #define US0_RTOR (*((reg32_t *)(USART0_BASE + US_RTOR_OFF)))    ///< Channel 0 receiver timeout register address.
00262 #define US1_RTOR (*((reg32_t *)(USART1_BASE + US_RTOR_OFF)))    ///< Channel 1 receiver timeout register address.
00263 /*\}*/
00264 
00268 /*\{*/
00269 #define US_TTGR_OFF             0x00000028      ///< USART transmitter time guard register offset.
00270 #define US0_TTGR (*((reg32_t *)(USART0_BASE + US_TTGR_OFF)))    ///< Channel 0 transmitter time guard register address.
00271 #define US1_TTGR (*((reg32_t *)(USART1_BASE + US_TTGR_OFF)))    ///< Channel 1 transmitter time guard register address.
00272 /*\}*/
00273 
00277 /*\{*/
00278 #define US_FIDI_OFF             0x00000040      ///< USART FI DI ratio register offset.
00279 #define US0_FIDI (*((reg32_t *)(USART0_BASE + US_FIDI_OFF)))    ///< Channel 0 FI DI ratio register address.
00280 #define US1_FIDI (*((reg32_t *)(USART1_BASE + US_FIDI_OFF)))    ///< Channel 1 FI DI ratio register address.
00281 /*\}*/
00282 
00286 /*\{*/
00287 #define US_NER_OFF              0x00000044      ///< USART error counter register offset.
00288 #define US0_NER  (*((reg32_t *)(USART0_BASE + US_NER_OFF)))     ///< Channel 0 error counter register address.
00289 #define US1_NER  (*((reg32_t *)(USART1_BASE + US_NER_OFF)))     ///< Channel 1 error counter register address.
00290 /*\}*/
00291 
00295 /*\{*/
00296 #define US_IF_OFF               0x0000004C      ///< USART IrDA filter register offset.
00297 #define US0_IF (*((reg32_t *)(USART0_BASE + US_IF_OFF)))        ///< Channel 0 IrDA filter register address.
00298 #define US1_IF (*((reg32_t *)(USART1_BASE + US_IF_OFF)))        ///< Channel 1 IrDA filter register address.
00299 /*\}*/
00300 
00301 #if USART_HAS_PDC
00302 
00306     /*\{*/
00307     #define US0_RPR (*((reg32_t *)(USART0_BASE + PERIPH_RPR_OFF)))      ///< Channel 0 receive pointer register address.
00308     #define US1_RPR (*((reg32_t *)(USART1_BASE + PERIPH_RPR_OFF)))      ///< Channel 1 receive pointer register address.
00309     /*\}*/
00310 
00314     /*\{*/
00315     #define US0_RCR (*((reg32_t *)(USART0_BASE + PERIPH_RCR_OFF)))      ///< Channel 0 receive counter register address.
00316     #define US1_RCR (*((reg32_t *)(USART1_BASE + PERIPH_RCR_OFF)))      ///< Channel 1 receive counter register address.
00317     /*\}*/
00318 
00322     /*\{*/
00323     #define US0_TPR (*((reg32_t *)(USART0_BASE + PERIPH_TPR_OFF)))      ///< Channel 0 transmit pointer register address.
00324     #define US1_TPR (*((reg32_t *)(USART1_BASE + PERIPH_TPR_OFF)))      ///< Channel 1 transmit pointer register address.
00325     /*\}*/
00326 
00330     /*\{*/
00331     #define US0_TCR (*((reg32_t *)(USART0_BASE + PERIPH_TCR_OFF)))      ///< Channel 0 transmit counter register address.
00332     #define US1_TCR (*((reg32_t *)(USART1_BASE + PERIPH_TCR_OFF)))      ///< Channel 1 transmit counter register address.
00333     /*\}*/
00334 
00335     #if defined(PERIPH_RNPR_OFF) && defined(PERIPH_RNCR_OFF)
00336     #define US0_RNPR   (*((reg32_t *)(USART0_BASE + PERIPH_RNPR_OFF)))  ///< PDC channel 0 receive next pointer register.
00337     #define US1_RNPR   (*((reg32_t *)(USART1_BASE + PERIPH_RNPR_OFF)))  ///< PDC channel 1 receive next pointer register.
00338     #define US0_RNCR   (*((reg32_t *)(USART0_BASE + PERIPH_RNCR_OFF)))  ///< PDC channel 0 receive next counter register.
00339     #define US1_RNCR   (*((reg32_t *)(USART1_BASE + PERIPH_RNCR_OFF)))  ///< PDC channel 1 receive next counter register.
00340     #endif
00341 
00342     #if defined(PERIPH_TNPR_OFF) && defined(PERIPH_TNCR_OFF)
00343     #define US0_TNPR   (*((reg32_t *)(USART0_BASE + PERIPH_TNPR_OFF)))  ///< PDC channel 0 transmit next pointer register.
00344     #define US1_TNPR   (*((reg32_t *)(USART1_BASE + PERIPH_TNPR_OFF)))  ///< PDC channel 1 transmit next pointer register.
00345     #define US0_TNCR   (*((reg32_t *)(USART0_BASE + PERIPH_TNCR_OFF)))  ///< PDC channel 0 transmit next counter register.
00346     #define US1_TNCR   (*((reg32_t *)(USART1_BASE + PERIPH_TNCR_OFF)))  ///< PDC channel 1 transmit next counter register.
00347     #endif
00348 
00349     #if defined(PERIPH_PTCR_OFF)
00350     #define US0_PTCR   (*((reg32_t *)(USART0_BASE + PERIPH_PTCR_OFF)))  ///< PDC channel 0 transfer control register.
00351     #define US1_PTCR   (*((reg32_t *)(USART1_BASE + PERIPH_PTCR_OFF)))  ///< PDC channel 1 transfer control register.
00352     #endif
00353 
00354     #if defined(PERIPH_PTSR_OFF)
00355     #define US0_PTSR   (*((reg32_t *)(USART0_BASE + PERIPH_PTSR_OFF)))  ///< PDC channel 0 transfer status register.
00356     #define US1_PTSR   (*((reg32_t *)(USART1_BASE + PERIPH_PTSR_OFF)))  ///< PDC channel 1 transfer status register.
00357     #endif
00358 
00359 #endif  /* USART_HAS_PDC */
00360 
00361 #endif /* SAM3_USART_H */