BeRTOS
|
00001 00040 #ifndef AT91_ADC_H 00041 #define AT91_ADC_H 00042 00043 00047 #define ADC_CR_OFF 0x00000000 ///< Control register offeset. 00048 #define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address. 00049 #define ADC_SWRST 0 ///< Software reset. 00050 #define ADC_START 1 ///< Start conversion. 00051 00052 00056 #define ADC_MR_OFF 0x00000004 ///< Mode register offeset. 00057 #define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address. 00058 #define ADC_TRGEN 0 ///< Trigger enable. 00059 00060 #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0. 00061 #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1. 00062 #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2. 00063 #define ADC_TRGSEL_EXT 0x0000000C ///< External trigger. 00064 00065 #define ADC_LOWRES 4 ///< Resolution 0: 10-bit, 1: 8-bit. 00066 #define ADC_SLEEP 5 ///< Sleep mode. 00067 00072 #define ADC_PRESCALER_MASK 0x00003F00 ///< Prescaler rate selection mask. 00073 #define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift. 00074 00079 #define ADC_STARTUP_MASK 0x001F0000 ///< Start up timer mask. 00080 #define ADC_STARTUP_SHIFT 16 ///< Start up timer shift. 00081 00082 00087 #define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask. 00088 #define ADC_SHTIME_SHIFT 24 ///< Sample & hold time shift. 00089 00090 00094 #define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset. 00095 #define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address. 00096 00100 #define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset. 00101 #define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address. 00102 00106 #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset. 00107 #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address. 00108 00109 #define ADC_CH_MASK 0x000000FF ///< Channel mask. 00110 #define ADC_CH0 0 ///< Channel 0 00111 #define ADC_CH1 1 ///< Channel 1 00112 #define ADC_CH2 2 ///< Channel 2 00113 #define ADC_CH3 3 ///< Channel 3 00114 #define ADC_CH4 4 ///< Channel 4 00115 #define ADC_CH5 5 ///< Channel 5 00116 #define ADC_CH6 6 ///< Channel 6 00117 #define ADC_CH7 7 ///< Channel 7 00118 00122 #define ADC_SR_OFF 0x0000001C ///< Status register offeset. 00123 #define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address. 00124 00128 #define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset. 00129 #define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register. 00130 00134 #define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset. 00135 #define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register. 00136 00140 #define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset. 00141 #define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register. 00142 00143 #define ADC_EOC_MASK 0x000000FF ///< End of converison mask. 00144 #define ADC_EOC0 0 ///< End of conversion channel 0. 00145 #define ADC_EOC1 1 ///< End of conversion channel 1. 00146 #define ADC_EOC2 2 ///< End of conversion channel 2. 00147 #define ADC_EOC3 3 ///< End of conversion channel 3. 00148 #define ADC_EOC4 4 ///< End of conversion channel 4. 00149 #define ADC_EOC5 5 ///< End of conversion channel 5. 00150 #define ADC_EOC6 6 ///< End of conversion channel 6. 00151 #define ADC_EOC7 7 ///< End of conversion channel 7. 00152 00153 #define ADC_OVRE0 8 ///< Overrun error channel 0. 00154 #define ADC_OVRE1 9 ///< Overrun error channel 1. 00155 #define ADC_OVRE2 10 ///< Overrun error channel 2. 00156 #define ADC_OVRE3 11 ///< Overrun error channel 3. 00157 #define ADC_OVRE4 12 ///< Overrun error channel 4. 00158 #define ADC_OVRE5 13 ///< Overrun error channel 5. 00159 #define ADC_OVRE6 14 ///< Overrun error channel 6. 00160 #define ADC_OVRE7 15 ///< Overrun error channel 7. 00161 00162 #define ADC_DRDY 16 ///< Data ready. 00163 #define ADC_GOVRE 17 ///< General overrun error. 00164 #define ADC_ENDRX 18 ///< End of RX buffer. 00165 #define ADC_RXBUFF 19 ///< Rx buffer full. 00166 00170 #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset. 00171 #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted data register. 00172 00178 #define ADC_CDR0_OFF 0x00000030 ///< Channel data register 0 offeset. 00179 #define ADC_CDR1_OFF 0x00000034 ///< Channel data register 1 offeset. 00180 #define ADC_CDR2_OFF 0x00000038 ///< Channel data register 2 offeset. 00181 #define ADC_CDR3_OFF 0x0000003C ///< Channel data register 3 offeset. 00182 #define ADC_CDR4_OFF 0x00000040 ///< Channel data register 4 offeset. 00183 #define ADC_CDR5_OFF 0x00000044 ///< Channel data register 5 offeset. 00184 #define ADC_CDR6_OFF 0x00000048 ///< Channel data register 6 offeset. 00185 #define ADC_CDR7_OFF 0x0000004C ///< Channel data register 7 offeset. 00186 00187 #define ADC_CDR0 (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF))) ///< Channel data register 0. 00188 #define ADC_CDR1 (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF))) ///< Channel data register 1. 00189 #define ADC_CDR2 (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF))) ///< Channel data register 2. 00190 #define ADC_CDR3 (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF))) ///< Channel data register 3. 00191 #define ADC_CDR4 (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF))) ///< Channel data register 4. 00192 #define ADC_CDR5 (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF))) ///< Channel data register 5. 00193 #define ADC_CDR6 (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF))) ///< Channel data register 6. 00194 #define ADC_CDR7 (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF))) ///< Channel data register 7. 00195 /* \} */ 00196 00197 #endif /* AT91_ADC_H */