BeRTOS
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00001 00041 /* 00042 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved. 00043 * 00044 * Redistribution and use in source and binary forms, with or without 00045 * modification, are permitted provided that the following conditions 00046 * are met: 00047 * 00048 * 1. Redistributions of source code must retain the above copyright 00049 * notice, this list of conditions and the following disclaimer. 00050 * 2. Redistributions in binary form must reproduce the above copyright 00051 * notice, this list of conditions and the following disclaimer in the 00052 * documentation and/or other materials provided with the distribution. 00053 * 3. Neither the name of the copyright holders nor the names of 00054 * contributors may be used to endorse or promote products derived 00055 * from this software without specific prior written permission. 00056 * 00057 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS 00058 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 00059 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 00060 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE 00061 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 00062 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 00063 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 00064 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 00065 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00066 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 00067 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 00068 * SUCH DAMAGE. 00069 * 00070 * For additional information see http://www.ethernut.de/ 00071 */ 00072 00073 #ifndef AT91_WDT_H 00074 #define AT91_WDT_H 00075 00076 00078 /*\{*/ 00079 #define WDT_CR_OFF 0x00000000 ///< Watchdog control register offset. 00080 #define WDT_CR (*((reg32_t *)(WDT_BASE + WDT_CR_OFF))) ///< Watchdog control register address. 00081 #define WDT_WDRSTT 0 ///< Watchdog restart. 00082 #define WDT_KEY 0xA5000000 ///< Watchdog password. 00083 /*\}*/ 00084 00086 /*\{*/ 00087 #define WDT_MR_OFF 0x00000004 ///< Mode register offset. 00088 #define WDT_MR (*((reg32_t *)(WDT_BASE + WDT_MR_OFF))) ///< Mode register address. 00089 #define WDT_WDV_MASK 0x00000FFF ///< Counter value mask. 00090 #define WDT_WDV_SHIFT 0 ///< Counter value LSB. 00091 #define WDT_WDFIEN 12 ///< Fault interrupt enable. 00092 #define WDT_WDRSTEN 13 ///< Reset enable. 00093 #define WDT_WDRPROC 14 ///< Eset processor enable. 00094 #define WDT_WDDIS 15 ///< Watchdog disable. 00095 #define WDT_WDD_MASK 0x0FFF0000 ///< Delta value mask. 00096 #define WDT_WDD_SHIFT 16 ///< Delta value LSB. 00097 #define WDT_WDDBGHLT 28 ///< Watchdog debug halt. 00098 #define WDT_WDIDLEHLT 29 ///< Watchdog idle halt. 00099 /*\}*/ 00100 00102 /*\{*/ 00103 #define WDT_SR_OFF 0x00000008 ///< Status register offset. 00104 #define WDT_SR (*((reg32_t *)(WDT_BASE + WDT_SR_OFF))) ///< Status register address. 00105 #define WDT_WDUNF 0 ///< Watchdog underflow. 00106 #define WDT_WDERR 1 ///< Watchdog error. 00107 /*\}*/ 00108 00109 00110 #endif /* AT91_WDT_H */