BeRTOS
lm3s_uart.h
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00001 
00036 #ifndef LM3S_UART_H
00037 #define LM3S_UART_H
00038 
00042 /*\{*/
00043 #define UART_O_DR               0x00000000  //< UART Data
00044 #define UART_O_RSR              0x00000004  //< UART Receive Status/Error Clear
00045 #define UART_O_ECR              0x00000004  //< UART Receive Status/Error Clear
00046 #define UART_O_FR               0x00000018  //< UART Flag
00047 #define UART_O_ILPR             0x00000020  //< UART IrDA Low-Power Register
00048 #define UART_O_IBRD             0x00000024  //< UART Integer Baud-Rate Divisor
00049 #define UART_O_FBRD             0x00000028  //< UART Fractional Baud-Rate
00050                                             //< Divisor
00051 #define UART_O_LCRH             0x0000002C  //< UART Line Control
00052 #define UART_O_CTL              0x00000030  //< UART Control
00053 #define UART_O_IFLS             0x00000034  //< UART Interrupt FIFO Level Select
00054 #define UART_O_IM               0x00000038  //< UART Interrupt Mask
00055 #define UART_O_RIS              0x0000003C  //< UART Raw Interrupt Status
00056 #define UART_O_MIS              0x00000040  //< UART Masked Interrupt Status
00057 #define UART_O_ICR              0x00000044  //< UART Interrupt Clear
00058 #define UART_O_DMACTL           0x00000048  //< UART DMA Control
00059 #define UART_O_LCTL             0x00000090  //< UART LIN Control
00060 #define UART_O_LSS              0x00000094  //< UART LIN Snap Shot
00061 #define UART_O_LTIM             0x00000098  //< UART LIN Timer
00062 /*\}*/
00063 
00067 /*\{*/
00068 #define UART_DR_OE              0x00000800  //< UART Overrun Error
00069 #define UART_DR_BE              0x00000400  //< UART Break Error
00070 #define UART_DR_PE              0x00000200  //< UART Parity Error
00071 #define UART_DR_FE              0x00000100  //< UART Framing Error
00072 #define UART_DR_DATA_M          0x000000FF  //< Data Transmitted or Received
00073 #define UART_DR_DATA_S          0
00074 /*\}*/
00075 
00079 /*\{*/
00080 #define UART_RSR_OE             0x00000008  //< UART Overrun Error
00081 #define UART_RSR_BE             0x00000004  //< UART Break Error
00082 #define UART_RSR_PE             0x00000002  //< UART Parity Error
00083 #define UART_RSR_FE             0x00000001  //< UART Framing Error
00084 /*\}*/
00085 
00089 /*\{*/
00090 #define UART_ECR_DATA_M         0x000000FF  //< Error Clear
00091 #define UART_ECR_DATA_S         0
00092 /*\}*/
00093 
00097 /*\{*/
00098 #define UART_FR_RI              0x00000100  //< Ring Indicator
00099 #define UART_FR_TXFE            0x00000080  //< UART Transmit FIFO Empty
00100 #define UART_FR_RXFF            0x00000040  //< UART Receive FIFO Full
00101 #define UART_FR_TXFF            0x00000020  //< UART Transmit FIFO Full
00102 #define UART_FR_RXFE            0x00000010  //< UART Receive FIFO Empty
00103 #define UART_FR_BUSY            0x00000008  //< UART Busy
00104 #define UART_FR_DCD             0x00000004  //< Data Carrier Detect
00105 #define UART_FR_DSR             0x00000002  //< Data Set Ready
00106 #define UART_FR_CTS             0x00000001  //< Clear To Send
00107 /*\}*/
00108 
00112 /*\{*/
00113 #define UART_ILPR_ILPDVSR_M     0x000000FF  //< IrDA Low-Power Divisor
00114 #define UART_ILPR_ILPDVSR_S     0
00115 /*\}*/
00116 
00120 /*\{*/
00121 #define UART_IBRD_DIVINT_M      0x0000FFFF  //< Integer Baud-Rate Divisor
00122 #define UART_IBRD_DIVINT_S      0
00123 /*\}*/
00124 
00128 /*\{*/
00129 #define UART_FBRD_DIVFRAC_M     0x0000003F  //< Fractional Baud-Rate Divisor
00130 #define UART_FBRD_DIVFRAC_S     0
00131 /*\}*/
00132 
00136 /*\{*/
00137 #define UART_LCRH_SPS           0x00000080  //< UART Stick Parity Select
00138 #define UART_LCRH_WLEN_M        0x00000060  //< UART Word Length
00139 #define UART_LCRH_WLEN_5        0x00000000  //< 5 bits (default)
00140 #define UART_LCRH_WLEN_6        0x00000020  //< 6 bits
00141 #define UART_LCRH_WLEN_7        0x00000040  //< 7 bits
00142 #define UART_LCRH_WLEN_8        0x00000060  //< 8 bits
00143 #define UART_LCRH_FEN           0x00000010  //< UART Enable FIFOs
00144 #define UART_LCRH_STP2          0x00000008  //< UART Two Stop Bits Select
00145 #define UART_LCRH_EPS           0x00000004  //< UART Even Parity Select
00146 #define UART_LCRH_PEN           0x00000002  //< UART Parity Enable
00147 #define UART_LCRH_BRK           0x00000001  //< UART Send Break
00148 /*\}*/
00149 
00153 /*\{*/
00154 #define UART_CTL_CTSEN          0x00008000  //< Enable Clear To Send
00155 #define UART_CTL_RTSEN          0x00004000  //< Enable Request to Send
00156 #define UART_CTL_RTS            0x00000800  //< Request to Send
00157 #define UART_CTL_DTR            0x00000400  //< Data Terminal Ready
00158 #define UART_CTL_RXE            0x00000200  //< UART Receive Enable
00159 #define UART_CTL_TXE            0x00000100  //< UART Transmit Enable
00160 #define UART_CTL_LBE            0x00000080  //< UART Loop Back Enable
00161 #define UART_CTL_LIN            0x00000040  //< LIN Mode Enable
00162 #define UART_CTL_HSE            0x00000020  //< High-Speed Enable
00163 #define UART_CTL_EOT            0x00000010  //< End of Transmission
00164 #define UART_CTL_SMART          0x00000008  //< ISO 7816 Smart Card Support
00165 #define UART_CTL_SIRLP          0x00000004  //< UART SIR Low-Power Mode
00166 #define UART_CTL_SIREN          0x00000002  //< UART SIR Enable
00167 #define UART_CTL_UARTEN         0x00000001  //< UART Enable
00168 /*\}*/
00169 
00173 /*\{*/
00174 #define UART_IFLS_RX_M          0x00000038  //< UART Receive Interrupt FIFO
00175                                             //< Level Select
00176 #define UART_IFLS_RX1_8         0x00000000  //< RX FIFO >= 1/8 full
00177 #define UART_IFLS_RX2_8         0x00000008  //< RX FIFO >= 1/4 full
00178 #define UART_IFLS_RX4_8         0x00000010  //< RX FIFO >= 1/2 full (default)
00179 #define UART_IFLS_RX6_8         0x00000018  //< RX FIFO >= 3/4 full
00180 #define UART_IFLS_RX7_8         0x00000020  //< RX FIFO >= 7/8 full
00181 #define UART_IFLS_TX_M          0x00000007  //< UART Transmit Interrupt FIFO
00182                                             //< Level Select
00183 #define UART_IFLS_TX1_8         0x00000000  //< TX FIFO <= 1/8 full
00184 #define UART_IFLS_TX2_8         0x00000001  //< TX FIFO <= 1/4 full
00185 #define UART_IFLS_TX4_8         0x00000002  //< TX FIFO <= 1/2 full (default)
00186 #define UART_IFLS_TX6_8         0x00000003  //< TX FIFO <= 3/4 full
00187 #define UART_IFLS_TX7_8         0x00000004  //< TX FIFO <= 7/8 full
00188 /*\}*/
00189 
00193 /*\{*/
00194 #define UART_IM_LME5IM          0x00008000  //< LIN Mode Edge 5 Interrupt Mask
00195 #define UART_IM_LME1IM          0x00004000  //< LIN Mode Edge 1 Interrupt Mask
00196 #define UART_IM_LMSBIM          0x00002000  //< LIN Mode Sync Break Interrupt
00197                                             //< Mask
00198 #define UART_IM_OEIM            0x00000400  //< UART Overrun Error Interrupt
00199                                             //< Mask
00200 #define UART_IM_BEIM            0x00000200  //< UART Break Error Interrupt Mask
00201 #define UART_IM_PEIM            0x00000100  //< UART Parity Error Interrupt Mask
00202 #define UART_IM_FEIM            0x00000080  //< UART Framing Error Interrupt
00203                                             //< Mask
00204 #define UART_IM_RTIM            0x00000040  //< UART Receive Time-Out Interrupt
00205                                             //< Mask
00206 #define UART_IM_TXIM            0x00000020  //< UART Transmit Interrupt Mask
00207 #define UART_IM_RXIM            0x00000010  //< UART Receive Interrupt Mask
00208 #define UART_IM_DSRMIM          0x00000008  //< UART Data Set Ready Modem
00209                                             //< Interrupt Mask
00210 #define UART_IM_DCDMIM          0x00000004  //< UART Data Carrier Detect Modem
00211                                             //< Interrupt Mask
00212 #define UART_IM_CTSMIM          0x00000002  //< UART Clear to Send Modem
00213                                             //< Interrupt Mask
00214 #define UART_IM_RIMIM           0x00000001  //< UART Ring Indicator Modem
00215                                             //< Interrupt Mask
00216 /*\}*/
00217 
00221 /*\{*/
00222 #define UART_RIS_LME5RIS        0x00008000  //< LIN Mode Edge 5 Raw Interrupt
00223                                             //< Status
00224 #define UART_RIS_LME1RIS        0x00004000  //< LIN Mode Edge 1 Raw Interrupt
00225                                             //< Status
00226 #define UART_RIS_LMSBRIS        0x00002000  //< LIN Mode Sync Break Raw
00227                                             //< Interrupt Status
00228 #define UART_RIS_OERIS          0x00000400  //< UART Overrun Error Raw Interrupt
00229                                             //< Status
00230 #define UART_RIS_BERIS          0x00000200  //< UART Break Error Raw Interrupt
00231                                             //< Status
00232 #define UART_RIS_PERIS          0x00000100  //< UART Parity Error Raw Interrupt
00233                                             //< Status
00234 #define UART_RIS_FERIS          0x00000080  //< UART Framing Error Raw Interrupt
00235                                             //< Status
00236 #define UART_RIS_RTRIS          0x00000040  //< UART Receive Time-Out Raw
00237                                             //< Interrupt Status
00238 #define UART_RIS_TXRIS          0x00000020  //< UART Transmit Raw Interrupt
00239                                             //< Status
00240 #define UART_RIS_RXRIS          0x00000010  //< UART Receive Raw Interrupt
00241                                             //< Status
00242 #define UART_RIS_DSRRIS         0x00000008  //< UART Data Set Ready Modem Raw
00243                                             //< Interrupt Status
00244 #define UART_RIS_DCDRIS         0x00000004  //< UART Data Carrier Detect Modem
00245                                             //< Raw Interrupt Status
00246 #define UART_RIS_CTSRIS         0x00000002  //< UART Clear to Send Modem Raw
00247                                             //< Interrupt Status
00248 #define UART_RIS_RIRIS          0x00000001  //< UART Ring Indicator Modem Raw
00249                                             //< Interrupt Status
00250 /*\}*/
00251 
00255 /*\{*/
00256 #define UART_MIS_LME5MIS        0x00008000  //< LIN Mode Edge 5 Masked Interrupt
00257                                             //< Status
00258 #define UART_MIS_LME1MIS        0x00004000  //< LIN Mode Edge 1 Masked Interrupt
00259                                             //< Status
00260 #define UART_MIS_LMSBMIS        0x00002000  //< LIN Mode Sync Break Masked
00261                                             //< Interrupt Status
00262 #define UART_MIS_OEMIS          0x00000400  //< UART Overrun Error Masked
00263                                             //< Interrupt Status
00264 #define UART_MIS_BEMIS          0x00000200  //< UART Break Error Masked
00265                                             //< Interrupt Status
00266 #define UART_MIS_PEMIS          0x00000100  //< UART Parity Error Masked
00267                                             //< Interrupt Status
00268 #define UART_MIS_FEMIS          0x00000080  //< UART Framing Error Masked
00269                                             //< Interrupt Status
00270 #define UART_MIS_RTMIS          0x00000040  //< UART Receive Time-Out Masked
00271                                             //< Interrupt Status
00272 #define UART_MIS_TXMIS          0x00000020  //< UART Transmit Masked Interrupt
00273                                             //< Status
00274 #define UART_MIS_RXMIS          0x00000010  //< UART Receive Masked Interrupt
00275                                             //< Status
00276 #define UART_MIS_DSRMIS         0x00000008  //< UART Data Set Ready Modem Masked
00277                                             //< Interrupt Status
00278 #define UART_MIS_DCDMIS         0x00000004  //< UART Data Carrier Detect Modem
00279                                             //< Masked Interrupt Status
00280 #define UART_MIS_CTSMIS         0x00000002  //< UART Clear to Send Modem Masked
00281                                             //< Interrupt Status
00282 #define UART_MIS_RIMIS          0x00000001  //< UART Ring Indicator Modem Masked
00283                                             //< Interrupt Status
00284 /*\}*/
00285 
00289 /*\{*/
00290 #define UART_ICR_LME5MIC        0x00008000  //< LIN Mode Edge 5 Interrupt Clear
00291 #define UART_ICR_LME1MIC        0x00004000  //< LIN Mode Edge 1 Interrupt Clear
00292 #define UART_ICR_LMSBMIC        0x00002000  //< LIN Mode Sync Break Interrupt
00293                                             //< Clear
00294 #define UART_ICR_OEIC           0x00000400  //< Overrun Error Interrupt Clear
00295 #define UART_ICR_BEIC           0x00000200  //< Break Error Interrupt Clear
00296 #define UART_ICR_PEIC           0x00000100  //< Parity Error Interrupt Clear
00297 #define UART_ICR_FEIC           0x00000080  //< Framing Error Interrupt Clear
00298 #define UART_ICR_RTIC           0x00000040  //< Receive Time-Out Interrupt Clear
00299 #define UART_ICR_TXIC           0x00000020  //< Transmit Interrupt Clear
00300 #define UART_ICR_RXIC           0x00000010  //< Receive Interrupt Clear
00301 #define UART_ICR_DSRMIC         0x00000008  //< UART Data Set Ready Modem
00302                                             //< Interrupt Clear
00303 #define UART_ICR_DCDMIC         0x00000004  //< UART Data Carrier Detect Modem
00304                                             //< Interrupt Clear
00305 #define UART_ICR_CTSMIC         0x00000002  //< UART Clear to Send Modem
00306                                             //< Interrupt Clear
00307 #define UART_ICR_RIMIC          0x00000001  //< UART Ring Indicator Modem
00308                                             //< Interrupt Clear
00309 /*\}*/
00310 
00314 /*\{*/
00315 #define UART_DMACTL_DMAERR      0x00000004  //< DMA on Error
00316 #define UART_DMACTL_TXDMAE      0x00000002  //< Transmit DMA Enable
00317 #define UART_DMACTL_RXDMAE      0x00000001  //< Receive DMA Enable
00318 /*\}*/
00319 
00323 /*\{*/
00324 #define UART_LCTL_BLEN_M        0x00000030  //< Sync Break Length
00325 #define UART_LCTL_BLEN_13T      0x00000000  //< Sync break length is 13T bits
00326                                             //< (default)
00327 #define UART_LCTL_BLEN_14T      0x00000010  //< Sync break length is 14T bits
00328 #define UART_LCTL_BLEN_15T      0x00000020  //< Sync break length is 15T bits
00329 #define UART_LCTL_BLEN_16T      0x00000030  //< Sync break length is 16T bits
00330 #define UART_LCTL_MASTER        0x00000001  //< LIN Master Enable
00331 /*\}*/
00332 
00336 /*\{*/
00337 #define UART_LSS_TSS_M          0x0000FFFF  //< Timer Snap Shot
00338 #define UART_LSS_TSS_S          0
00339 /*\}*/
00340 
00344 /*\{*/
00345 #define UART_LTIM_TIMER_M       0x0000FFFF  //< Timer Value
00346 #define UART_LTIM_TIMER_S       0
00347 /*\}*/
00348 
00352 /*\{*/
00353 #ifndef DEPRECATED
00354 /*\}*/
00355 
00359 /*\{*/
00360 #define UART_O_LCR_H            0x0000002C  //< Line Control Register, HIGH byte
00361 #define UART_O_PeriphID4        0x00000FD0
00362 #define UART_O_PeriphID5        0x00000FD4
00363 #define UART_O_PeriphID6        0x00000FD8
00364 #define UART_O_PeriphID7        0x00000FDC
00365 #define UART_O_PeriphID0        0x00000FE0
00366 #define UART_O_PeriphID1        0x00000FE4
00367 #define UART_O_PeriphID2        0x00000FE8
00368 #define UART_O_PeriphID3        0x00000FEC
00369 #define UART_O_PCellID0         0x00000FF0
00370 #define UART_O_PCellID1         0x00000FF4
00371 #define UART_O_PCellID2         0x00000FF8
00372 #define UART_O_PCellID3         0x00000FFC
00373 /*\}*/
00374 
00379 /*\{*/
00380 #define UART_DR_DATA_MASK       0x000000FF  //< UART data
00381 /*\}*/
00382 
00387 /*\{*/
00388 #define UART_IBRD_DIVINT_MASK   0x0000FFFF  //< Integer baud-rate divisor
00389 /*\}*/
00390 
00395 /*\{*/
00396 #define UART_FBRD_DIVFRAC_MASK  0x0000003F  //< Fractional baud-rate divisor
00397 /*\}*/
00398 
00403 /*\{*/
00404 #define UART_LCR_H_SPS          0x00000080  //< Stick Parity Select
00405 #define UART_LCR_H_WLEN         0x00000060  //< Word length
00406 #define UART_LCR_H_WLEN_5       0x00000000  //< 5 bit data
00407 #define UART_LCR_H_WLEN_6       0x00000020  //< 6 bit data
00408 #define UART_LCR_H_WLEN_7       0x00000040  //< 7 bit data
00409 #define UART_LCR_H_WLEN_8       0x00000060  //< 8 bit data
00410 #define UART_LCR_H_FEN          0x00000010  //< Enable FIFO
00411 #define UART_LCR_H_STP2         0x00000008  //< Two Stop Bits Select
00412 #define UART_LCR_H_EPS          0x00000004  //< Even Parity Select
00413 #define UART_LCR_H_PEN          0x00000002  //< Parity Enable
00414 #define UART_LCR_H_BRK          0x00000001  //< Send Break
00415 /*\}*/
00416 
00421 /*\{*/
00422 #define UART_IFLS_RX_MASK       0x00000038  //< RX FIFO level mask
00423 #define UART_IFLS_TX_MASK       0x00000007  //< TX FIFO level mask
00424 /*\}*/
00425 
00430 /*\{*/
00431 #define UART_RSR_ANY            (UART_RSR_OE | UART_RSR_BE | UART_RSR_PE | \
00432                                  UART_RSR_FE)
00433 /*\}*/
00434 
00439 /*\{*/
00440 #define UART_RV_CTL             0x00000300
00441 #define UART_RV_PCellID1        0x000000F0
00442 #define UART_RV_PCellID3        0x000000B1
00443 #define UART_RV_FR              0x00000090
00444 #define UART_RV_PeriphID2       0x00000018
00445 #define UART_RV_IFLS            0x00000012
00446 #define UART_RV_PeriphID0       0x00000011
00447 #define UART_RV_PCellID0        0x0000000D
00448 #define UART_RV_PCellID2        0x00000005
00449 #define UART_RV_PeriphID3       0x00000001
00450 #define UART_RV_PeriphID4       0x00000000
00451 #define UART_RV_LCR_H           0x00000000
00452 #define UART_RV_PeriphID6       0x00000000
00453 #define UART_RV_DR              0x00000000
00454 #define UART_RV_RSR             0x00000000
00455 #define UART_RV_ECR             0x00000000
00456 #define UART_RV_PeriphID5       0x00000000
00457 #define UART_RV_RIS             0x00000000
00458 #define UART_RV_FBRD            0x00000000
00459 #define UART_RV_IM              0x00000000
00460 #define UART_RV_MIS             0x00000000
00461 #define UART_RV_ICR             0x00000000
00462 #define UART_RV_PeriphID1       0x00000000
00463 #define UART_RV_PeriphID7       0x00000000
00464 #define UART_RV_IBRD            0x00000000
00465 /*\}*/
00466 
00467 #endif /* DEPRECATED */
00468 
00469 #endif /* LM3S_UART_H */