BeRTOS
|
00001 00039 #ifndef ETH_AT91_H 00040 #define ETH_AT91_H 00041 00042 // Settings and definition for DAVICOM 9161A 00043 // \{ 00044 #define NIC_PHY_ADDR 31 00045 00046 //Registry definition 00047 #define NIC_PHY_BMCR 0x00 // Basic mode control register. 00048 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test. 00049 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode. 00050 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation. 00051 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII. 00052 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down. 00053 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation. 00054 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps. 00055 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode. 00056 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset. 00057 00058 #define NIC_PHY_BMSR 0x01 // Basic mode status register. 00059 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete. 00060 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation 00061 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status. 00062 00063 #define NIC_PHY_ID1 0x02 // PHY identifier register 1. 00064 #define NIC_PHY_ID2 0x03 // PHY identifier register 2. 00065 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register. 00066 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register. 00067 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register. 00068 00069 // Pin definition for DAVICOM 9161A 00070 // See schematic for at91sam7x-ek evalution board 00071 #define PHY_TXCLK_ISOLATE_BIT 0 00072 #define PHY_REFCLK_XT2_BIT 0 00073 #define PHY_TXEN_BIT 1 00074 #define PHY_TXD0_BIT 2 00075 #define PHY_TXD1_BIT 3 00076 #define PHY_CRS_AD4_BIT 4 00077 #define PHY_RXD0_AD0_BIT 5 00078 #define PHY_RXD1_AD1_BIT 6 00079 #define PHY_RXER_RXD4_RPTR_BIT 7 00080 #define PHY_MDC_BIT 8 00081 #define PHY_MDIO_BIT 9 00082 #define PHY_TXD2_BIT 10 00083 #define PHY_TXD3_BIT 11 00084 #define PHY_TXER_TXD4_BIT 12 00085 #define PHY_RXD2_AD2_BIT 13 00086 #define PHY_RXD3_AD3_BIT 14 00087 #define PHY_RXDV_TESTMODE_BIT 15 00088 #define PHY_COL_RMII_BIT 16 00089 #define PHY_RXCLK_10BTSER_BIT 17 00090 #define PHY_PWRDN_BIT 18 00091 #define PHY_MDINTR_BIT 26 00092 00093 #define PHY_MII_PINS BV(PHY_REFCLK_XT2_BIT) \ 00094 | BV(PHY_TXEN_BIT) \ 00095 | BV(PHY_TXD0_BIT) \ 00096 | BV(PHY_TXD1_BIT) \ 00097 | BV(PHY_CRS_AD4_BIT) \ 00098 | BV(PHY_RXD0_AD0_BIT) \ 00099 | BV(PHY_RXD1_AD1_BIT) \ 00100 | BV(PHY_RXER_RXD4_RPTR_BIT) \ 00101 | BV(PHY_MDC_BIT) \ 00102 | BV(PHY_MDIO_BIT) \ 00103 | BV(PHY_TXD2_BIT) \ 00104 | BV(PHY_TXD3_BIT) \ 00105 | BV(PHY_TXER_TXD4_BIT) \ 00106 | BV(PHY_RXD2_AD2_BIT) \ 00107 | BV(PHY_RXD3_AD3_BIT) \ 00108 | BV(PHY_RXDV_TESTMODE_BIT) \ 00109 | BV(PHY_COL_RMII_BIT) \ 00110 | BV(PHY_RXCLK_10BTSER_BIT) 00111 // \} 00112 00113 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this 00114 #define EMAC_TX_BUFFERS 1 //!!! Don't change this 00115 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS 00116 00117 #define EMAC_RX_BUFFERS 32 //!!! Don't change this 00118 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this 00119 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS 00120 00121 // Flag to manage local tx buffer 00122 #define TXS_USED 0x80000000 //Used buffer. 00123 #define TXS_WRAP 0x40000000 //Last descriptor. 00124 #define TXS_ERROR 0x20000000 //Retry limit exceeded. 00125 #define TXS_UNDERRUN 0x10000000 //Transmit underrun. 00126 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted. 00127 #define TXS_NO_CRC 0x00010000 //CRC not appended. 00128 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame. 00129 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS. 00130 00131 // Flag to manage local rx buffer 00132 #define RXBUF_OWNERSHIP 0x00000001 00133 #define RXBUF_WRAP 0x00000002 00134 00135 #define BUF_ADDRMASK 0xFFFFFFFC 00136 00137 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected. 00138 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match. 00139 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match. 00140 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match. 00141 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match. 00142 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match. 00143 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match. 00144 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match. 00145 #define RXS_TYPE_ID 0x00400000 // Type ID match. 00146 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected. 00147 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected. 00148 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority. 00149 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator. 00150 #define RXS_EOF 0x00008000 // End of frame. 00151 #define RXS_SOF 0x00004000 // Start of frame. 00152 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask. 00153 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS. 00154 00155 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR)) 00156 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \ 00157 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND)) 00158 00159 typedef struct BufDescriptor 00160 { 00161 volatile uint32_t addr; 00162 volatile uint32_t stat; 00163 } BufDescriptor; 00164 00165 #endif /* ETH_AT91_H */