BeRTOS
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00001 00044 #include <drv/timer_mega.h> 00045 #include <cfg/macros.h> // BV() 00046 00047 #include <cpu/types.h> 00048 #include <cpu/irq.h> 00049 00050 #include <avr/io.h> 00051 00052 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA2560 00053 #define REG_TIFR0 TIFR0 00054 #define REG_TIFR1 TIFR1 00055 #define REG_TIFR2 TIFR2 00056 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 00057 #define REG_TIFR3 TIFR3 00058 #endif 00059 00060 #define REG_TIMSK0 TIMSK0 00061 #define REG_TIMSK1 TIMSK1 00062 #define REG_TIMSK2 TIMSK2 00063 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560 00064 #define REG_TIMSK3 TIMSK3 00065 #endif 00066 00067 #define REG_TCCR0A TCCR0A 00068 #define REG_TCCR0B TCCR0B 00069 00070 #define REG_TCCR2A TCCR2A 00071 #define REG_TCCR2B TCCR2B 00072 00073 #define REG_OCR0A OCR0A 00074 #define REG_OCR2A OCR2A 00075 00076 #define BIT_OCF0A OCF0A 00077 #define BIT_OCF2A OCF2A 00078 00079 #define BIT_OCIE0A OCIE0A 00080 #define BIT_OCIE2A OCIE2A 00081 #else 00082 #define REG_TIFR0 TIFR 00083 #define REG_TIFR1 TIFR 00084 #define REG_TIFR2 TIFR 00085 #define REG_TIFR3 TIFR 00086 00087 #define REG_TIMSK0 TIMSK 00088 #define REG_TIMSK1 TIMSK 00089 #define REG_TIMSK2 TIMSK 00090 #define REG_TIMSK3 ETIMSK 00091 00092 #define REG_TCCR0A TCCR0 00093 #define REG_TCCR0B TCCR0 00094 00095 #define REG_TCCR2A TCCR2 00096 #define REG_TCCR2B TCCR2 00097 00098 #define REG_OCR0A OCR0 00099 #define REG_OCR2A OCR2 00100 00101 #define BIT_OCF0A OCF0 00102 #define BIT_OCF2A OCF2 00103 00104 #define BIT_OCIE0A OCIE0 00105 #define BIT_OCIE2A OCIE2 00106 #endif 00107 00108 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103 00109 /* These ATMega have different prescaler options. */ 00110 #define TIMER0_PRESCALER_64 BV(CS02) 00111 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20)) 00112 #else 00113 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00)) 00114 #define TIMER2_PRESCALER_64 BV(CS22) 00115 #endif 00116 00118 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0) 00119 00120 void timer_hw_init(void) 00121 { 00122 cpu_flags_t flags; 00123 IRQ_SAVE_DISABLE(flags); 00124 00125 /* Reset Timer flags */ 00126 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0); 00127 00128 /* Setup Timer/Counter interrupt */ 00129 REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to 00130 REG_TCCR0B = 0; 00131 00132 REG_TCCR0A = BV(WGM01); /* Clear on Compare match */ 00133 #if TIMER_PRESCALER == 64 00134 REG_TCCR0B |= TIMER0_PRESCALER_64; 00135 #else 00136 #error Unsupported value of TIMER_PRESCALER 00137 #endif 00138 00139 TCNT0 = 0x00; /* Initialization of Timer/Counter */ 00140 REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */ 00141 00142 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ 00143 REG_TIMSK0 &= ~BV(TOIE0); 00144 REG_TIMSK0 |= BV(BIT_OCIE0A); 00145 00146 IRQ_RESTORE(flags); 00147 } 00148 00149 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1) 00150 00151 void timer_hw_init(void) 00152 { 00153 cpu_flags_t flags; 00154 IRQ_SAVE_DISABLE(flags); 00155 00156 /* Reset Timer overflow flag */ 00157 REG_TIFR1 |= BV(TOV1); 00158 00159 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ 00160 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) 00161 TCCR1A |= BV(WGM11); 00162 TCCR1A &= ~BV(WGM10); 00163 TCCR1B |= BV(WGM12) | BV(CS10); 00164 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); 00165 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ 00166 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) 00167 TCCR1A |= BV(WGM10); 00168 TCCR1A &= ~BV(WGM11); 00169 TCCR1B |= BV(WGM12) | BV(CS10); 00170 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12)); 00171 #else 00172 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS 00173 #endif 00174 00175 TCNT1 = 0x00; /* initialization of Timer/Counter */ 00176 00177 /* Enable timer interrupt: Timer/Counter1 Overflow */ 00178 REG_TIMSK1 |= BV(TOIE1); 00179 00180 IRQ_RESTORE(flags); 00181 } 00182 00183 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2) 00184 void timer_hw_init(void) 00185 { 00186 cpu_flags_t flags; 00187 IRQ_SAVE_DISABLE(flags); 00188 00189 /* Reset Timer flags */ 00190 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2); 00191 00192 /* Setup Timer/Counter interrupt */ 00193 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to 00194 REG_TCCR2B = 0; // ensure correct initialization. 00195 00196 REG_TCCR2A = BV(WGM21); 00197 #if TIMER_PRESCALER == 64 00198 REG_TCCR2B |= TIMER2_PRESCALER_64; 00199 #else 00200 #error Unsupported value of TIMER_PRESCALER 00201 #endif 00202 00203 /* Clear on Compare match & prescaler = 64, internal sys clock. 00204 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */ 00205 TCNT2 = 0x00; /* initialization of Timer/Counter */ 00206 REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */ 00207 00208 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */ 00209 REG_TIMSK2 &= ~BV(TOIE2); 00210 REG_TIMSK2 |= BV(BIT_OCIE2A); 00211 00212 IRQ_RESTORE(flags); 00213 } 00214 00215 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3) 00216 00217 #if CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32 00218 #error For select target there is not TIMER_ON_OVERFLOW3, please select an other one. 00219 #endif 00220 00221 void timer_hw_init(void) 00222 { 00223 cpu_flags_t flags; 00224 IRQ_SAVE_DISABLE(flags); 00225 00226 /* Reset Timer overflow flag */ 00227 REG_TIFR3 |= BV(TOV3); 00228 00229 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */ 00230 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9) 00231 TCCR3A |= BV(WGM31); 00232 TCCR3A &= ~BV(WGM30); 00233 TCCR3B |= BV(WGM32) | BV(CS30); 00234 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); 00235 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */ 00236 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8) 00237 TCCR3A |= BV(WGM30); 00238 TCCR3A &= ~BV(WGM31); 00239 TCCR3B |= BV(WGM32) | BV(CS30); 00240 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32)); 00241 #else 00242 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS 00243 #endif 00244 00245 /* initialization of Timer/Counter */ 00246 TCNT3 = 0x00; 00247 00248 /* Enable timer interrupt: Timer/Counter3 Overflow */ 00249 REG_TIMSK3 |= BV(TOIE3); 00250 00251 IRQ_RESTORE(flags); 00252 } 00253 00254 #else 00255 #error Unimplemented value for CONFIG_TIMER 00256 #endif /* CONFIG_TIMER */ 00257