BeRTOS
|
LM3S I2C definition. More...
Go to the source code of this file.
Defines | |
#define | I2C_O_MSA 0x00000000 |
I2C Master Slave Address. | |
#define | I2C_O_SOAR 0x00000000 |
I2C Slave Own Address. | |
#define | I2C_O_SCSR 0x00000004 |
I2C Slave Control/Status. | |
#define | I2C_O_MCS 0x00000004 |
I2C Master Control/Status. | |
#define | I2C_O_SDR 0x00000008 |
I2C Slave Data. | |
#define | I2C_O_MDR 0x00000008 |
I2C Master Data. | |
#define | I2C_O_MTPR 0x0000000C |
I2C Master Timer Period. | |
#define | I2C_O_SIMR 0x0000000C |
I2C Slave Interrupt Mask. | |
#define | I2C_O_SRIS 0x00000010 |
I2C Slave Raw Interrupt Status. | |
#define | I2C_O_MIMR 0x00000010 |
I2C Master Interrupt Mask. | |
#define | I2C_O_MRIS 0x00000014 |
I2C Master Raw Interrupt Status. | |
#define | I2C_O_SMIS 0x00000014 |
I2C Slave Masked Interrupt. | |
#define | I2C_O_SICR 0x00000018 |
I2C Slave Interrupt Clear. | |
#define | I2C_O_MMIS 0x00000018 |
I2C Master Masked Interrupt. | |
#define | I2C_O_MICR 0x0000001C |
I2C Master Interrupt Clear. | |
#define | I2C_O_MCR 0x00000020 |
I2C Master Configuration. | |
#define | I2C_MSA_SA_M 0x000000FE |
I2C Slave Address. | |
#define | I2C_MSA_RS 0x00000001 |
Receive not send. | |
#define | I2C_MSA_ADDS 0 |
Set address write bit. | |
#define | I2C_MSA_ADDR 1 |
Set address read bit. | |
#define | I2C_SOAR_OAR_M 0x0000007F |
I2C Slave Own Address. | |
#define | I2C_SCSR_FBR 0x00000004 |
First Byte Received. | |
#define | I2C_SCSR_TREQ 0x00000002 |
Transmit Request. | |
#define | I2C_SCSR_DA 0x00000001 |
Device Active. | |
#define | I2C_SCSR_RREQ 0x00000001 |
Receive Request. | |
#define | I2C_MCS_BUSBSY 0x00000040 |
Bus Busy. | |
#define | I2C_MCS_IDLE 0x00000020 |
I2C Idle. | |
#define | I2C_MCS_ARBLST 0x00000010 |
Arbitration Lost. | |
#define | I2C_MCS_ACK 0x00000008 |
Data Acknowledge Enable. | |
#define | I2C_MCS_DATACK 0x00000008 |
Acknowledge Data. | |
#define | I2C_MCS_ADRACK 0x00000004 |
Acknowledge Address. | |
#define | I2C_MCS_STOP 0x00000004 |
Generate STOP. | |
#define | I2C_MCS_START 0x00000002 |
Generate START. | |
#define | I2C_MCS_ERROR 0x00000002 |
Error. | |
#define | I2C_MCS_RUN 0x00000001 |
I2C Master Enable. | |
#define | I2C_MCS_BUSY 0x00000001 |
I2C Busy. | |
#define | I2C_SDR_DATA_M 0x000000FF |
Data for Transfer. | |
#define | I2C_MDR_DATA_M 0x000000FF |
Data Transferred. | |
#define | I2C_MTPR_TPR_M 0x000000FF |
SCL Clock Period. | |
#define | I2C_SIMR_STOPIM 0x00000004 |
Stop Condition Interrupt Mask. | |
#define | I2C_SIMR_STARTIM 0x00000002 |
Start Condition Interrupt Mask. | |
#define | I2C_SIMR_DATAIM 0x00000001 |
Data Interrupt Mask. | |
#define | I2C_SRIS_STOPRIS 0x00000004 |
Stop Condition Raw Interrupt. | |
#define | I2C_SRIS_STARTRIS 0x00000002 |
Start Condition Raw Interrupt. | |
#define | I2C_SRIS_DATARIS 0x00000001 |
Data Raw Interrupt Status. | |
#define | I2C_MIMR_IM 0x00000001 |
Interrupt Mask. | |
#define | I2C_MRIS_RIS 0x00000001 |
Raw Interrupt Status. | |
#define | I2C_SMIS_STOPMIS 0x00000004 |
Stop Condition Masked Interrupt. | |
#define | I2C_SMIS_STARTMIS 0x00000002 |
Start Condition Masked Interrupt. | |
#define | I2C_SMIS_DATAMIS 0x00000001 |
Data Masked Interrupt Status. | |
#define | I2C_SICR_STOPIC 0x00000004 |
Stop Condition Interrupt Clear. | |
#define | I2C_SICR_STARTIC 0x00000002 |
Start Condition Interrupt Clear. | |
#define | I2C_SICR_DATAIC 0x00000001 |
Data Interrupt Clear. | |
#define | I2C_MMIS_MIS 0x00000001 |
Masked Interrupt Status. | |
#define | I2C_MICR_IC 0x00000001 |
Interrupt Clear. | |
#define | I2C_MCR_SFE 0x00000020 |
I2C Slave Function Enable. | |
#define | I2C_MCR_MFE 0x00000010 |
I2C Master Function Enable. | |
#define | I2C_MCR_LPBK 0x00000001 |
I2C Loopback. | |
#define | I2C_O_SLAVE 0x00000800 |
Offset from master to slave. | |
#define | I2C_SIMR_IM 0x00000001 |
Interrupt Mask. | |
#define | I2C_SRIS_RIS 0x00000001 |
Raw Interrupt Status. | |
#define | I2C_SMIS_MIS 0x00000001 |
Masked Interrupt Status. | |
#define | I2C_SICR_IC 0x00000001 |
Clear Interrupt. | |
#define | I2C_MASTER_O_SA 0x00000000 |
Slave address register. | |
#define | I2C_MASTER_O_CS 0x00000004 |
Control and Status register. | |
#define | I2C_MASTER_O_DR 0x00000008 |
Data register. | |
#define | I2C_MASTER_O_TPR 0x0000000C |
Timer period register. | |
#define | I2C_MASTER_O_IMR 0x00000010 |
Interrupt mask register. | |
#define | I2C_MASTER_O_RIS 0x00000014 |
Raw interrupt status register. | |
#define | I2C_MASTER_O_MIS 0x00000018 |
Masked interrupt status reg. | |
#define | I2C_MASTER_O_MICR 0x0000001C |
Interrupt clear register. | |
#define | I2C_MASTER_O_CR 0x00000020 |
Configuration register. | |
#define | I2C_SLAVE_O_SICR 0x00000018 |
Interrupt clear register. | |
#define | I2C_SLAVE_O_MIS 0x00000014 |
Masked interrupt status reg. | |
#define | I2C_SLAVE_O_RIS 0x00000010 |
Raw interrupt status register. | |
#define | I2C_SLAVE_O_IM 0x0000000C |
Interrupt mask register. | |
#define | I2C_SLAVE_O_DR 0x00000008 |
Data register. | |
#define | I2C_SLAVE_O_CSR 0x00000004 |
Control/Status register. | |
#define | I2C_SLAVE_O_OAR 0x00000000 |
Own address register. | |
#define | I2C_MASTER_SA_SA_MASK 0x000000FE |
Slave address. | |
#define | I2C_MASTER_SA_RS 0x00000001 |
Receive/send. | |
#define | I2C_MASTER_CS_BUS_BUSY 0x00000040 |
Bus busy. | |
#define | I2C_MASTER_CS_IDLE 0x00000020 |
Idle. | |
#define | I2C_MASTER_CS_BUSY 0x00000001 |
Controller is TX/RX data. | |
#define | I2C_MASTER_CS_ERROR 0x00000002 |
Error occurred. | |
#define | I2C_MASTER_CS_ADDR_ACK 0x00000004 |
Address byte not acknowledged. | |
#define | I2C_MASTER_CS_DATA_ACK 0x00000008 |
Data byte not acknowledged. | |
#define | I2C_MASTER_CS_ARB_LOST 0x00000010 |
Lost arbitration. | |
#define | I2C_MASTER_CS_ACK 0x00000008 |
Acknowlegde. | |
#define | I2C_MASTER_CS_STOP 0x00000004 |
Stop. | |
#define | I2C_MASTER_CS_START 0x00000002 |
Start. | |
#define | I2C_MASTER_CS_RUN 0x00000001 |
Run. | |
#define | I2C_SCL_FAST 400000 |
SCL fast frequency. | |
#define | I2C_SCL_STANDARD 100000 |
SCL standard frequency. | |
#define | I2C_MASTER_TPR_SCL_LP 0x00000006 |
SCL low period. | |
#define | I2C_MASTER_TPR_SCL_HP 0x00000004 |
SCL high period. | |
#define | I2C_MASTER_IMR_IM 0x00000001 |
Master interrupt mask. | |
#define | I2C_MASTER_RIS_RIS 0x00000001 |
Master raw interrupt status. | |
#define | I2C_MASTER_MIS_MIS 0x00000001 |
Master masked interrupt status. | |
#define | I2C_MASTER_MICR_IC 0x00000001 |
Master interrupt clear. | |
#define | I2C_MASTER_CR_SFE 0x00000020 |
Slave function enable. | |
#define | I2C_MASTER_CR_MFE 0x00000010 |
Master function enable. | |
#define | I2C_MASTER_CR_LPBK 0x00000001 |
Loopback enable. | |
#define | I2C_SLAVE_SOAR_OAR_MASK 0x0000007F |
Slave address. | |
#define | I2C_SLAVE_CSR_FBR 0x00000004 |
First byte received from master. | |
#define | I2C_SLAVE_CSR_TREQ 0x00000002 |
Transmit request received. | |
#define | I2C_SLAVE_CSR_DA 0x00000001 |
Enable the device. | |
#define | I2C_SLAVE_CSR_RREQ 0x00000001 |
Receive data from I2C master. | |
#define | I2C_SLAVE_IMR_IM 0x00000001 |
Slave interrupt mask. | |
#define | I2C_SLAVE_RIS_RIS 0x00000001 |
Slave raw interrupt status. | |
#define | I2C_SLAVE_MIS_MIS 0x00000001 |
Slave masked interrupt status. | |
#define | I2C_SLAVE_SICR_IC 0x00000001 |
Slave interrupt clear. |
LM3S I2C definition.
Definition in file lm3s_i2c.h.
#define I2C_O_MMIS 0x00000018 |
#define I2C_O_SMIS 0x00000014 |
#define I2C_SMIS_STARTMIS 0x00000002 |
#define I2C_SMIS_STOPMIS 0x00000004 |
#define I2C_SRIS_STARTRIS 0x00000002 |
#define I2C_SRIS_STOPRIS 0x00000004 |