BeRTOS
at91_aic.h
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00001 
00040 /*
00041  * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
00042  *
00043  * Redistribution and use in source and binary forms, with or without
00044  * modification, are permitted provided that the following conditions
00045  * are met:
00046  *
00047  * 1. Redistributions of source code must retain the above copyright
00048  *    notice, this list of conditions and the following disclaimer.
00049  * 2. Redistributions in binary form must reproduce the above copyright
00050  *    notice, this list of conditions and the following disclaimer in the
00051  *    documentation and/or other materials provided with the distribution.
00052  * 3. Neither the name of the copyright holders nor the names of
00053  *    contributors may be used to endorse or promote products derived
00054  *    from this software without specific prior written permission.
00055  *
00056  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00057  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00058  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00059  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00060  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00061  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00062  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00063  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00064  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00065  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00066  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00067  * SUCH DAMAGE.
00068  *
00069  * For additional information see http://www.ethernut.de/
00070  */
00071 
00072 #ifndef AT91_AIC_H
00073 #define AT91_AIC_H
00074 
00075 #include <cfg/compiler.h>
00076 
00077 
00078 
00082 #define AIC_SMR(i)  (*((reg32_t *)(AIC_BASE + (i) * 4)))
00083 
00088 #define AIC_PRIOR_MASK 0x00000007
00089 
00097 /*\{*/
00098 #define AIC_SRCTYPE_MASK 0x00000060
00099 
00100 #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000      ///< Internal level sensitive.
00101 #define AIC_SRCTYPE_INT_EDGE_TRIGGERED  0x00000020      ///< Internal edge triggered.
00102 #define AIC_SRCTYPE_EXT_LOW_LEVEL       0x00000000      ///< External low level.
00103 #define AIC_SRCTYPE_EXT_NEGATIVE_EDGE   0x00000020      ///< External falling edge.
00104 #define AIC_SRCTYPE_EXT_HIGH_LEVEL      0x00000040      ///< External high level.
00105 #define AIC_SRCTYPE_EXT_POSITIVE_EDGE   0x00000060      ///< External rising edge.
00106 /*\}*/
00107 
00108 
00112 typedef void (*irq_handler_t)(void);
00113 
00115 /*\{*/
00120 #define AIC_SVR(i)  (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
00121 /*\}*/
00122 
00124 /*\{*/
00125 #define AIC_IVR_OFF 0x00000100  ///< IRQ vector register offset.
00126 #define AIC_IVR     (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address.
00127 /*\}*/
00128 
00130 /*\{*/
00131 #define AIC_FVR_OFF 0x00000104  ///< FIQ vector register offset.
00132 #define AIC_FVR     (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address.
00133 /*\}*/
00134 
00136 /*\{*/
00137 #define AIC_ISR_OFF    0x00000108  ///< Interrupt status register offset.
00138 #define AIC_ISR        (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address.
00139 #define AIC_IRQID_MASK 0x0000001F  ///< Current interrupt identifier mask.
00140 /*\}*/
00141 
00143 /*\{*/
00144 #define AIC_IPR_OFF 0x0000010C  ///< Interrupt pending register offset.
00145 #define AIC_IPR     (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address.
00146 /*\}*/
00147 
00149 /*\{*/
00150 #define AIC_IMR_OFF 0x00000110  ///< Interrupt mask register offset.
00151 #define AIC_IMR     (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address.
00152 /*\}*/
00153 
00155 /*\{*/
00156 #define AIC_CISR_OFF 0x00000114  ///< Core interrupt status register offset.
00157 #define AIC_CISR     (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address.
00158 #define AIC_NFIQ     1  ///< Core FIQ Status
00159 #define AIC_NIRQ     2  ///< Core IRQ Status
00160 /*\}*/
00161 
00163 /*\{*/
00164 #define AIC_IECR_OFF 0x00000120  ///< Interrupt enable command register offset.
00165 #define AIC_IECR     (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF)))   ///< Interrupt enable command register address.
00166 /*\}*/
00167 
00169 /*\{*/
00170 #define AIC_IDCR_OFF 0x00000124  ///< Interrupt disable command register offset.
00171 #define AIC_IDCR     (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF)))   ///< Interrupt disable command register address.
00172 /*\}*/
00173 
00175 /*\{*/
00176 #define AIC_ICCR_OFF 0x00000128  ///< Interrupt clear command register offset.
00177 #define AIC_ICCR     (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF)))   ///< Interrupt clear command register address.
00178 /*\}*/
00179 
00181 /*\{*/
00182 #define AIC_ISCR_OFF 0x0000012C  ///< Interrupt set command register offset.
00183 #define AIC_ISCR     (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF)))   ///< Interrupt set command register address.
00184 /*\}*/
00185 
00187 /*\{*/
00188 #define AIC_EOICR_OFF 0x00000130  ///< End of interrupt command register offset.
00189 #define AIC_EOICR     (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF)))  ///< End of interrupt command register address.
00190 /*\}*/
00191 
00193 /*\{*/
00194 #define AIC_SPU_OFF 0x00000134  ///< Spurious vector register offset.
00195 #define AIC_SPU     (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)==    ///< Spurious vector register address.
00196 /*\}*/
00197 
00199 /*\{*/
00200 #define AIC_DCR_OFF 0x0000138   ///< Debug control register offset.
00201 #define AIC_DCR     (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF)))    ///< Debug control register address.
00202 /*\}*/
00203 
00205 /*\{*/
00206 #define AIC_FFER_OFF 0x00000140  ///< Fast forcing enable register offset.
00207 #define AIC_FFER     (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF)))   ///< Fast forcing enable register address.
00208 /*\}*/
00209 
00211 /*\{*/
00212 #define AIC_FFDR_OFF 0x00000144  ///< Fast forcing disable register address.
00213 #define AIC_FFDR     (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF)))   ///< Fast forcing disable register address.
00214 /*\}*/
00215 
00217 /*\{*/
00218 #define AIC_FFSR_OFF 0x00000148  ///< Fast forcing status register address.
00219 #define AIC_FFSR     (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF)))   ///< Fast forcing status register address.
00220 /*\}*/
00221 
00222 #endif /* AT91_AIC_H */