BeRTOS
|
00001 00036 #ifndef STM32_FLASH_H 00037 #define STM32_FLASH_H 00038 00039 #include <cfg/compiler.h> 00040 00041 #include <cpu/types.h> 00042 00044 #define F_SIZE ((*(reg32_t *) 0x1FFFF7E0) & 0xFFFF) 00045 00046 00047 /* Flash Access Control Register bits */ 00048 #define ACR_LATENCY_MASK ((uint32_t)0x00000038) 00049 #define ACR_HLFCYA_MASK ((uint32_t)0xFFFFFFF7) 00050 #define ACR_PRFTBE_MASK ((uint32_t)0xFFFFFFEF) 00051 00052 /* Flash Access Control Register bits */ 00053 #define ACR_PRFTBS_MASK ((uint32_t)0x00000020) 00054 00055 /* Flash Control Register bits */ 00056 #define CR_PG_SET ((uint32_t)0x00000001) 00057 #define CR_PG_RESET ((uint32_t)0x00001FFE) 00058 00059 #define CR_PER_SET ((uint32_t)0x00000002) 00060 #define CR_PER_RESET ((uint32_t)0x00001FFD) 00061 00062 #define CR_MER_SET ((uint32_t)0x00000004) 00063 #define CR_MER_RESET ((uint32_t)0x00001FFB) 00064 00065 #define CR_OPTPG_SET ((uint32_t)0x00000010) 00066 #define CR_OPTPG_RESET ((uint32_t)0x00001FEF) 00067 00068 #define CR_OPTER_SET ((uint32_t)0x00000020) 00069 #define CR_OPTER_RESET ((uint32_t)0x00001FDF) 00070 00071 #define CR_STRT_SET ((uint32_t)0x00000040) 00072 00073 #define CR_LOCK_SET ((uint32_t)0x00000080) 00074 00075 /* FLASH Mask */ 00076 #define RDPRT_MASK ((uint32_t)0x00000002) 00077 #define WRP0_MASK ((uint32_t)0x000000FF) 00078 #define WRP1_MASK ((uint32_t)0x0000FF00) 00079 #define WRP2_MASK ((uint32_t)0x00FF0000) 00080 #define WRP3_MASK ((uint32_t)0xFF000000) 00081 00082 /* FLASH Keys */ 00083 #define RDP_KEY ((uint16_t)0x00A5) 00084 #define FLASH_KEY1 ((uint32_t)0x45670123) 00085 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) 00086 00087 /* Flash Latency */ 00088 #define FLASH_LATENCY_0 ((uint32_t)0x00000000) /* FLASH Zero Latency cycle */ 00089 #define FLASH_LATENCY_1 ((uint32_t)0x00000001) /* FLASH One Latency cycle */ 00090 #define FLASH_LATENCY_2 ((uint32_t)0x00000002) /* FLASH Two Latency cycles */ 00091 00092 /* Half Cycle Enable/Disable */ 00093 #define FLASH_HALFCYCLEACCESS_ENABLE ((uint32_t)0x00000008) /* FLASH Half Cycle Enable */ 00094 #define FLASH_HALFCYCLEACCESS_DISABLE ((uint32_t)0x00000000) /* FLASH Half Cycle Disable */ 00095 00096 /* Prefetch Buffer Enable/Disable */ 00097 #define FLASH_PREFETCHBUFFER_ENABLE ((uint32_t)0x00000010) /* FLASH Prefetch Buffer Enable */ 00098 #define FLASH_PREFETCHBUFFER_DISABLE ((uint32_t)0x00000000) /* FLASH Prefetch Buffer Disable */ 00099 00100 /* Option Bytes Write Protection */ 00101 #define FLASH_WRPROT_PAGES0TO3 ((uint32_t)0x00000001) /* Write protection of page 0 to 3 */ 00102 #define FLASH_WRPROT_PAGES4TO7 ((uint32_t)0x00000002) /* Write protection of page 4 to 7 */ 00103 #define FLASH_WRPROT_PAGES8TO11 ((uint32_t)0x00000004) /* Write protection of page 8 to 11 */ 00104 #define FLASH_WRPROT_PAGES12TO15 ((uint32_t)0x00000008) /* Write protection of page 12 to 15 */ 00105 #define FLASH_WRPROT_PAGES16TO19 ((uint32_t)0x00000010) /* Write protection of page 16 to 19 */ 00106 #define FLASH_WRPROT_PAGES20TO23 ((uint32_t)0x00000020) /* Write protection of page 20 to 23 */ 00107 #define FLASH_WRPROT_PAGES24TO27 ((uint32_t)0x00000040) /* Write protection of page 24 to 27 */ 00108 #define FLASH_WRPROT_PAGES28TO31 ((uint32_t)0x00000080) /* Write protection of page 28 to 31 */ 00109 #define FLASH_WRPROT_PAGES32TO35 ((uint32_t)0x00000100) /* Write protection of page 32 to 35 */ 00110 #define FLASH_WRPROT_PAGES36TO39 ((uint32_t)0x00000200) /* Write protection of page 36 to 39 */ 00111 #define FLASH_WRPROT_PAGES40TO43 ((uint32_t)0x00000400) /* Write protection of page 40 to 43 */ 00112 #define FLASH_WRPROT_PAGES44TO47 ((uint32_t)0x00000800) /* Write protection of page 44 to 47 */ 00113 #define FLASH_WRPROT_PAGES48TO51 ((uint32_t)0x00001000) /* Write protection of page 48 to 51 */ 00114 #define FLASH_WRPROT_PAGES52TO55 ((uint32_t)0x00002000) /* Write protection of page 52 to 55 */ 00115 #define FLASH_WRPROT_PAGES56TO59 ((uint32_t)0x00004000) /* Write protection of page 56 to 59 */ 00116 #define FLASH_WRPROT_PAGES60TO63 ((uint32_t)0x00008000) /* Write protection of page 60 to 63 */ 00117 #define FLASH_WRPROT_PAGES64TO67 ((uint32_t)0x00010000) /* Write protection of page 64 to 67 */ 00118 #define FLASH_WRPROT_PAGES68TO71 ((uint32_t)0x00020000) /* Write protection of page 68 to 71 */ 00119 #define FLASH_WRPROT_PAGES72TO75 ((uint32_t)0x00040000) /* Write protection of page 72 to 75 */ 00120 #define FLASH_WRPROT_PAGES76TO79 ((uint32_t)0x00080000) /* Write protection of page 76 to 79 */ 00121 #define FLASH_WRPROT_PAGES80TO83 ((uint32_t)0x00100000) /* Write protection of page 80 to 83 */ 00122 #define FLASH_WRPROT_PAGES84TO87 ((uint32_t)0x00200000) /* Write protection of page 84 to 87 */ 00123 #define FLASH_WRPROT_PAGES88TO91 ((uint32_t)0x00400000) /* Write protection of page 88 to 91 */ 00124 #define FLASH_WRPROT_PAGES92TO95 ((uint32_t)0x00800000) /* Write protection of page 92 to 95 */ 00125 #define FLASH_WRPROT_PAGES96TO99 ((uint32_t)0x01000000) /* Write protection of page 96 to 99 */ 00126 #define FLASH_WRPROT_PAGES100TO103 ((uint32_t)0x02000000) /* Write protection of page 100 to 103 */ 00127 #define FLASH_WRPROT_PAGES104TO107 ((uint32_t)0x04000000) /* Write protection of page 104 to 107 */ 00128 #define FLASH_WRPROT_PAGES108TO111 ((uint32_t)0x08000000) /* Write protection of page 108 to 111 */ 00129 #define FLASH_WRPROT_PAGES112TO115 ((uint32_t)0x10000000) /* Write protection of page 112 to 115 */ 00130 #define FLASH_WRPROT_PAGES116TO119 ((uint32_t)0x20000000) /* Write protection of page 115 to 119 */ 00131 #define FLASH_WRPROT_PAGES120TO123 ((uint32_t)0x40000000) /* Write protection of page 120 to 123 */ 00132 #define FLASH_WRPROT_PAGES124TO127 ((uint32_t)0x80000000) /* Write protection of page 124 to 127 */ 00133 #define FLASH_WRPROT_ALLPAGES ((uint32_t)0xFFFFFFFF) /* Write protection All Pages */ 00134 00135 /* Option Bytes IWatchdog */ 00136 #define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */ 00137 #define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */ 00138 00139 /* Option Bytes nRST_STOP */ 00140 #define OB_STOP_NORST ((uint16_t)0x0002) /* No reset generated when entering in STOP */ 00141 #define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */ 00142 00143 /* Option Bytes nRST_STDBY */ 00144 #define OB_STDBY_NORST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */ 00145 #define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */ 00146 00147 /* FLASH Interrupts */ 00148 #define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */ 00149 #define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */ 00150 00151 /* FLASH Flags */ 00152 #define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */ 00153 #define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */ 00154 #define FLASH_FLAG_PGERR ((uint32_t)0x00000004) /* FLASH Program error flag */ 00155 #define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */ 00156 #define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */ 00157 00158 00159 00163 struct stm32_flash 00164 { 00165 reg32_t ACR; 00166 reg32_t KEYR; 00167 reg32_t OPTKEYR; 00168 reg32_t SR; 00169 reg32_t CR; 00170 reg32_t AR; 00171 reg32_t RESERVED; 00172 reg32_t OBR; 00173 reg32_t WRPR; 00174 }; 00175 00176 #endif /* STM32_FLASH_H */