BeRTOS
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00001 00036 #ifndef SAM3_UART_H 00037 #define SAM3_UART_H 00038 00042 /*\{*/ 00043 #if CPU_CM3_SAM3N 00044 #define UART0_BASE 0x400E0600 00045 #elif CPU_CM3_SAM3U 00046 #define UART0_BASE 0x400E0600 00047 #define UART1_BASE 0x400E0800 00048 #elif CPU_CM3_SAM3X 00049 #define UART0_BASE 0x400E0800 00050 #endif 00051 /*\}*/ 00052 00056 /*\{*/ 00057 #define UART_CR_OFF 0x000 //< Control Register 00058 #define UART_MR_OFF 0x004 //< Mode Register 00059 #define UART_IER_OFF 0x008 //< Interrupt Enable Register 00060 #define UART_IDR_OFF 0x00C //< Interrupt Disable Register 00061 #define UART_IMR_OFF 0x010 //< Interrupt Mask Register 00062 #define UART_SR_OFF 0x014 //< Status Register 00063 #define UART_RHR_OFF 0x018 //< Receive Holding Register 00064 #define UART_THR_OFF 0x01C //< Transmit Holding Register 00065 #define UART_BRGR_OFF 0x020 //< Baud Rate Generator Register 00066 00067 #define UART_RPR_OFF 0x100 //< Receive Pointer Register 00068 #define UART_RCR_OFF 0x104 //< Receive Counter Register 00069 #define UART_TPR_OFF 0x108 //< Transmit Pointer Register 00070 #define UART_TCR_OFF 0x10C //< Transmit Counter Register 00071 #define UART_RNPR_OFF 0x110 //< Receive Next Pointer Register 00072 #define UART_RNCR_OFF 0x114 //< Receive Next Counter Register 00073 #define UART_TNPR_OFF 0x118 //< Transmit Next Pointer Register 00074 #define UART_TNCR_OFF 0x11C //< Transmit Next Counter Register 00075 #define UART_PTCR_OFF 0x120 //< Transfer Control Register 00076 #define UART_PTSR_OFF 0x124 //< Transfer Status Register 00077 /*\}*/ 00078 00082 /*\{*/ 00083 #if defined(UART0_BASE) 00084 #define UART0_ACCESS(offset) (*((reg32_t *)(UART0_BASE + (offset)))) 00085 00086 #define UART_CR UART0_ACCESS(UART_CR_OFF) //< Control Register 00087 #define UART_MR UART0_ACCESS(UART_MR_OFF) //< Mode Register 00088 #define UART_IER UART0_ACCESS(UART_IER_OFF) //< Interrupt Enable Register 00089 #define UART_IDR UART0_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register 00090 #define UART_IMR UART0_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register 00091 #define UART_SR UART0_ACCESS(UART_SR_OFF) //< Status Register 00092 #define UART_RHR UART0_ACCESS(UART_RHR_OFF) //< Receive Holding Register 00093 #define UART_THR UART0_ACCESS(UART_THR_OFF) //< Transmit Holding Register 00094 #define UART_BRGR UART0_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register 00095 00096 #define UART_RPR UART0_ACCESS(UART_RPR_OFF) //< Receive Pointer Register 00097 #define UART_RCR UART0_ACCESS(UART_RCR_OFF) //< Receive Counter Register 00098 #define UART_TPR UART0_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register 00099 #define UART_TCR UART0_ACCESS(UART_TCR_OFF) //< Transmit Counter Register 00100 #define UART_RNPR UART0_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register 00101 #define UART_RNCR UART0_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register 00102 #define UART_TNPR UART0_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register 00103 #define UART_TNCR UART0_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register 00104 #define UART_PTCR UART0_ACCESS(UART_PTCR_OFF) //< Transfer Control Register 00105 #define UART_PTSR UART0_ACCESS(UART_PTSR_OFF) //< Transfer Status Register 00106 #endif /* UART0_BASE */ 00107 00108 #if defined(UART1_BASE) 00109 #define UART1_ACCESS(offset) (*((reg32_t *)(UART1_BASE + (offset)))) 00110 00111 #define UART_CR UART1_ACCESS(UART_CR_OFF) //< Control Register 00112 #define UART_MR UART1_ACCESS(UART_MR_OFF) //< Mode Register 00113 #define UART_IER UART1_ACCESS(UART_IER_OFF) //< Interrupt Enable Register 00114 #define UART_IDR UART1_ACCESS(UART_IDR_OFF) //< Interrupt Disable Register 00115 #define UART_IMR UART1_ACCESS(UART_IMR_OFF) //< Interrupt Mask Register 00116 #define UART_SR UART1_ACCESS(UART_SR_OFF) //< Status Register 00117 #define UART_RHR UART1_ACCESS(UART_RHR_OFF) //< Receive Holding Register 00118 #define UART_THR UART1_ACCESS(UART_THR_OFF) //< Transmit Holding Register 00119 #define UART_BRGR UART1_ACCESS(UART_BRGR_OFF) //< Baud Rate Generator Register 00120 00121 #define UART_RPR UART1_ACCESS(UART_RPR_OFF) //< Receive Pointer Register 00122 #define UART_RCR UART1_ACCESS(UART_RCR_OFF) //< Receive Counter Register 00123 #define UART_TPR UART1_ACCESS(UART_TPR_OFF) //< Transmit Pointer Register 00124 #define UART_TCR UART1_ACCESS(UART_TCR_OFF) //< Transmit Counter Register 00125 #define UART_RNPR UART1_ACCESS(UART_RNPR_OFF) //< Receive Next Pointer Register 00126 #define UART_RNCR UART1_ACCESS(UART_RNCR_OFF) //< Receive Next Counter Register 00127 #define UART_TNPR UART1_ACCESS(UART_TNPR_OFF) //< Transmit Next Pointer Register 00128 #define UART_TNCR UART1_ACCESS(UART_TNCR_OFF) //< Transmit Next Counter Register 00129 #define UART_PTCR UART1_ACCESS(UART_PTCR_OFF) //< Transfer Control Register 00130 #define UART_PTSR UART1_ACCESS(UART_PTSR_OFF) //< Transfer Status Register 00131 #endif /* UART0_BASE */ 00132 /*\}*/ 00133 00137 /*\{*/ 00138 #define UART_CR_RSTRX 2 //< Reset Receiver 00139 #define UART_CR_RSTTX 3 //< Reset Transmitter 00140 #define UART_CR_RXEN 4 //< Receiver Enable 00141 #define UART_CR_RXDIS 5 //< Receiver Disable 00142 #define UART_CR_TXEN 6 //< Transmitter Enable 00143 #define UART_CR_TXDIS 7 //< Transmitter Disable 00144 #define UART_CR_RSTSTA 8 //< Reset Status Bits 00145 /*\}*/ 00146 00150 /*\{*/ 00151 #define UART_MR_PAR_SHIFT 9 //< Parity Type shift 00152 #define UART_MR_PAR_MASK (0x7 << UART_MR_PAR_SHIFT) //< Parity Type mask 00153 #define UART_MR_PAR_EVEN (0x0 << UART_MR_PAR_SHIFT) //< Even parity 00154 #define UART_MR_PAR_ODD (0x1 << UART_MR_PAR_SHIFT) //< Odd parity 00155 #define UART_MR_PAR_SPACE (0x2 << UART_MR_PAR_SHIFT) //< Space: parity forced to 0 00156 #define UART_MR_PAR_MARK (0x3 << UART_MR_PAR_SHIFT) //< Mark: parity forced to 1 00157 #define UART_MR_PAR_NO (0x4 << UART_MR_PAR_SHIFT) //< No parity 00158 #define UART_MR_CHMODE_SHIFT 14 //< Channel Mode shift 00159 #define UART_MR_CHMODE_MASK (0x3 << UART_MR_CHMODE_SHIFT) //< Channel Mode mask 00160 #define UART_MR_CHMODE_NORMAL (0x0 << UART_MR_CHMODE_SHIFT) //< Normal Mode 00161 #define UART_MR_CHMODE_AUTOMATIC (0x1 << UART_MR_CHMODE_SHIFT) //< Automatic Echo 00162 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SHIFT) //< Local Loopback 00163 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SHIFT) //< Remote Loopback 00164 /*\}*/ 00165 00169 /*\{*/ 00170 #define UART_IER_RXRDY 0 //< Enable RXRDY Interrupt 00171 #define UART_IER_TXRDY 1 //< Enable TXRDY Interrupt 00172 #define UART_IER_ENDRX 3 //< Enable End of Receive Transfer Interrupt 00173 #define UART_IER_ENDTX 4 //< Enable End of Transmit Interrupt 00174 #define UART_IER_OVRE 5 //< Enable Overrun Error Interrupt 00175 #define UART_IER_FRAME 6 //< Enable Framing Error Interrupt 00176 #define UART_IER_PARE 7 //< Enable Parity Error Interrupt 00177 #define UART_IER_TXEMPTY 9 //< Enable TXEMPTY Interrupt 00178 #define UART_IER_TXBUFE 11 //< Enable Buffer Empty Interrupt 00179 #define UART_IER_RXBUFF 12 //< Enable Buffer Full Interrupt 00180 /*\}*/ 00181 00185 /*\{*/ 00186 #define UART_IDR_RXRDY 0 //< Disable RXRDY Interrupt 00187 #define UART_IDR_TXRDY 1 //< Disable TXRDY Interrupt 00188 #define UART_IDR_ENDRX 3 //< Disable End of Receive Transfer Interrupt 00189 #define UART_IDR_ENDTX 4 //< Disable End of Transmit Interrupt 00190 #define UART_IDR_OVRE 5 //< Disable Overrun Error Interrupt 00191 #define UART_IDR_FRAME 6 //< Disable Framing Error Interrupt 00192 #define UART_IDR_PARE 7 //< Disable Parity Error Interrupt 00193 #define UART_IDR_TXEMPTY 9 //< Disable TXEMPTY Interrupt 00194 #define UART_IDR_TXBUFE 11 //< Disable Buffer Empty Interrupt 00195 #define UART_IDR_RXBUFF 12 //< Disable Buffer Full Interrupt 00196 /*\}*/ 00197 00201 /*\{*/ 00202 #define UART_IMR_RXRDY 0 //< Mask RXRDY Interrupt 00203 #define UART_IMR_TXRDY 1 //< Disable TXRDY Interrupt 00204 #define UART_IMR_ENDRX 3 //< Mask End of Receive Transfer Interrupt 00205 #define UART_IMR_ENDTX 4 //< Mask End of Transmit Interrupt 00206 #define UART_IMR_OVRE 5 //< Mask Overrun Error Interrupt 00207 #define UART_IMR_FRAME 6 //< Mask Framing Error Interrupt 00208 #define UART_IMR_PARE 7 //< Mask Parity Error Interrupt 00209 #define UART_IMR_TXEMPTY 9 //< Mask TXEMPTY Interrupt 00210 #define UART_IMR_TXBUFE 11 //< Mask TXBUFE Interrupt 00211 #define UART_IMR_RXBUFF 12 //< Mask RXBUFF Interrupt 00212 /*\}*/ 00213 00217 /*\{*/ 00218 #define UART_SR_RXRDY 0 //< Receiver Ready 00219 #define UART_SR_TXRDY 1 //< Transmitter Ready 00220 #define UART_SR_ENDRX 3 //< End of Receiver Transfer 00221 #define UART_SR_ENDTX 4 //< End of Transmitter Transfer 00222 #define UART_SR_OVRE 5 //< Overrun Error 00223 #define UART_SR_FRAME 6 //< Framing Error 00224 #define UART_SR_PARE 7 //< Parity Error 00225 #define UART_SR_TXEMPTY 9 //< Transmitter Empty 00226 #define UART_SR_TXBUFE 11 //< Transmission Buffer Empty 00227 #define UART_SR_RXBUFF 12 //< Receive Buffer Full 00228 /*\}*/ 00229 00233 /*\{*/ 00234 #define UART_RHR_RXCHR_MASK 0xFF //< Received Character mask 00235 #define UART_RHR_RXCHR_SHIFT 0 //< Received Character shift 00236 /*\}*/ 00237 00241 /*\{*/ 00242 #define UART_THR_TXCHR_MASK 0xFF //< Character to be Transmitted mask 00243 #define UART_THR_TXCHR_SHIFT 0 //< Character to be Transmitted shift 00244 /*\}*/ 00245 00249 /*\{*/ 00250 #define UART_BRGR_CD_MASK 0xFFFF //< Clock Divisor mask 00251 #define UART_BRGR_CD_SHIFT 0 //< Clock Divisor shift 00252 /*\}*/ 00253 00257 /*\{*/ 00258 #define UART_RPR_RXPTR_MASK 0xFFFFFFFF //< Receive Pointer Register mask 00259 #define UART_RPR_RXPTR_SHIFT 0 //< Receive Pointer Register shift 00260 /*\}*/ 00261 00265 /*\{*/ 00266 #define UART_RCR_RXCTR_MASK 0xFFFF //< Receive Counter Register mask 00267 #define UART_RCR_RXCTR_SHIFT 0 //< Receive Counter Register shift 00268 /*\}*/ 00269 00273 /*\{*/ 00274 #define UART_TPR_TXPTR_MASK 0xFFFFFFFF //< Transmit Counter Register mask 00275 #define UART_TPR_TXPTR_SHIFT 0 //< Transmit Counter Register shift 00276 /*\}*/ 00277 00281 /*\{*/ 00282 #define UART_TCR_TXCTR_MASK 0xFFFF //< Transmit Counter Register mask 00283 #define UART_TCR_TXCTR_SHIFT 0 //< Transmit Counter Register shift 00284 /*\}*/ 00285 00289 /*\{*/ 00290 #define UART_RNPR_RXNPTR_MASK 0xFFFFFFFF //< Receive Next Pointer mask 00291 #define UART_RNPR_RXNPTR_SHIFT 0 //< Receive Next Pointer shift 00292 /*\}*/ 00293 00297 /*\{*/ 00298 #define UART_RNCR_RXNCTR_MASK 0xFFFF //< Receive Next Counter mask 00299 #define UART_RNCR_RXNCTR_SHIFT 0 //< Receive Next Counter shift 00300 /*\}*/ 00301 00305 /*\{*/ 00306 #define UART_TNPR_TXNPTR_MASK 0xFFFFFFFF //< Transmit Next Pointer mask 00307 #define UART_TNPR_TXNPTR_SHIFT 0 //< Transmit Next Pointer shift 00308 /*\}*/ 00309 00313 /*\{*/ 00314 #define UART_TNCR_TXNCTR_MASK 0xFFFF //< Transmit Counter Next mask 00315 #define UART_TNCR_TXNCTR_SHIFT 0 //< Transmit Counter Next shift 00316 /*\}*/ 00317 00321 /*\{*/ 00322 #define UART_PTCR_RXTEN 0 //< Receiver Transfer Enable 00323 #define UART_PTCR_RXTDIS 1 //< Receiver Transfer Disable 00324 #define UART_PTCR_TXTEN 8 //< Transmitter Transfer Enable 00325 #define UART_PTCR_TXTDIS 9 //< Transmitter Transfer Disable 00326 /*\}*/ 00327 00331 /*\{*/ 00332 #define UART_PTSR_RXTEN 0 //< Receiver Transfer Enable 00333 #define UART_PTSR_TXTEN 8 //< Transmitter Transfer Enable 00334 /*\}*/ 00335 00336 #endif /* SAM3_UART_H */