BeRTOS
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00001 00038 #ifndef LPC23XX_H 00039 #define LPC23XX_H 00040 00041 #include <cfg/compiler.h> 00042 00043 #include <cpu/detect.h> 00044 /* Vectored Interrupt Controller (VIC) */ 00045 #define VIC_BASE_ADDR 0xFFFFF000 00046 #define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000)) 00047 #define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004)) 00048 #define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008)) 00049 #define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C)) 00050 #define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010)) 00051 #define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014)) 00052 #define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018)) 00053 #define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C)) 00054 #define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020)) 00055 #define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024)) 00056 00057 #define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100)) 00058 #define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104)) 00059 #define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108)) 00060 #define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C)) 00061 #define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110)) 00062 #define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114)) 00063 #define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118)) 00064 #define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C)) 00065 #define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120)) 00066 #define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124)) 00067 #define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128)) 00068 #define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C)) 00069 #define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130)) 00070 #define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134)) 00071 #define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138)) 00072 #define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C)) 00073 #define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140)) 00074 #define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144)) 00075 #define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148)) 00076 #define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C)) 00077 #define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150)) 00078 #define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154)) 00079 #define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158)) 00080 #define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C)) 00081 #define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160)) 00082 #define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164)) 00083 #define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168)) 00084 #define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C)) 00085 #define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170)) 00086 #define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174)) 00087 #define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178)) 00088 #define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C)) 00089 00090 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx, 00091 these registers are known as "VICVectPriority(x)". */ 00092 #define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200)) 00093 #define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204)) 00094 #define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208)) 00095 #define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C)) 00096 #define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210)) 00097 #define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214)) 00098 #define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218)) 00099 #define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C)) 00100 #define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220)) 00101 #define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224)) 00102 #define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228)) 00103 #define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C)) 00104 #define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230)) 00105 #define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234)) 00106 #define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238)) 00107 #define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C)) 00108 #define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240)) 00109 #define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244)) 00110 #define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248)) 00111 #define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C)) 00112 #define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250)) 00113 #define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254)) 00114 #define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258)) 00115 #define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C)) 00116 #define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260)) 00117 #define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264)) 00118 #define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268)) 00119 #define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C)) 00120 #define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270)) 00121 #define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274)) 00122 #define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278)) 00123 #define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C)) 00124 00125 #define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00)) 00126 00127 00128 /* Pin Connect Block */ 00129 #define PINSEL_BASE_ADDR 0xE002C000 00130 #define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00)) 00131 #define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04)) 00132 #define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08)) 00133 #define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C)) 00134 #define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10)) 00135 #define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14)) 00136 #define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18)) 00137 #define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C)) 00138 #define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20)) 00139 #define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24)) 00140 #define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28)) 00141 00142 #define PINSEL0_OFF 0x00 00143 #define PINSEL1_OFF 0x04 00144 #define PINSEL2_OFF 0x08 00145 #define PINSEL3_OFF 0x0C 00146 #define PINSEL4_OFF 0x10 00147 #define PINSEL5_OFF 0x14 00148 #define PINSEL6_OFF 0x18 00149 #define PINSEL7_OFF 0x1C 00150 #define PINSEL8_OFF 0x20 00151 #define PINSEL9_OFF 0x24 00152 #define PINSEL10_OFF 0x28 00153 00154 #define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40)) 00155 #define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44)) 00156 #define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48)) 00157 #define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C)) 00158 #define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50)) 00159 #define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54)) 00160 #define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58)) 00161 #define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C)) 00162 #define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60)) 00163 #define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64)) 00164 00165 /* General Purpose Input/Output (GPIO) */ 00166 #define GPIO_BASE_ADDR 0xE0028000 00167 #define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00)) 00168 #define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04)) 00169 #define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08)) 00170 #define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C)) 00171 #define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10)) 00172 #define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14)) 00173 #define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18)) 00174 #define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C)) 00175 00176 /* GPIO Interrupt Registers */ 00177 #define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90)) 00178 #define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94)) 00179 #define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84)) 00180 #define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88)) 00181 #define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C)) 00182 00183 #define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0)) 00184 #define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4)) 00185 #define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4)) 00186 #define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8)) 00187 #define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC)) 00188 00189 #define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80)) 00190 00191 #define PARTCFG_BASE_ADDR 0x3FFF8000 00192 #define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00)) 00193 00194 /* Fast I/O setup */ 00195 #define FIO_BASE_ADDR 0x3FFFC000 00196 #define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00)) 00197 #define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10)) 00198 #define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14)) 00199 #define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18)) 00200 #define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C)) 00201 00202 #define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20)) 00203 #define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30)) 00204 #define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34)) 00205 #define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38)) 00206 #define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C)) 00207 00208 #define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40)) 00209 #define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50)) 00210 #define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54)) 00211 #define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58)) 00212 #define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C)) 00213 00214 #define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60)) 00215 #define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70)) 00216 #define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74)) 00217 #define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78)) 00218 #define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C)) 00219 00220 #define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80)) 00221 #define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90)) 00222 #define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94)) 00223 #define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98)) 00224 #define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C)) 00225 00226 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */ 00227 #define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00)) 00228 #define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20)) 00229 #define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40)) 00230 #define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60)) 00231 #define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80)) 00232 00233 #define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01)) 00234 #define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) 00235 #define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41)) 00236 #define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61)) 00237 #define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81)) 00238 00239 #define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02)) 00240 #define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22)) 00241 #define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42)) 00242 #define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62)) 00243 #define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82)) 00244 00245 #define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03)) 00246 #define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23)) 00247 #define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43)) 00248 #define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63)) 00249 #define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83)) 00250 00251 #define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00)) 00252 #define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20)) 00253 #define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40)) 00254 #define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60)) 00255 #define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80)) 00256 00257 #define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02)) 00258 #define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22)) 00259 #define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42)) 00260 #define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62)) 00261 #define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82)) 00262 00263 #define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10)) 00264 #define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30)) 00265 #define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50)) 00266 #define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70)) 00267 #define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90)) 00268 00269 #define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11)) 00270 #define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21)) 00271 #define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51)) 00272 #define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71)) 00273 #define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91)) 00274 00275 #define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12)) 00276 #define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32)) 00277 #define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52)) 00278 #define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72)) 00279 #define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92)) 00280 00281 #define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13)) 00282 #define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33)) 00283 #define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53)) 00284 #define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73)) 00285 #define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93)) 00286 00287 #define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10)) 00288 #define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30)) 00289 #define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50)) 00290 #define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70)) 00291 #define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90)) 00292 00293 #define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12)) 00294 #define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32)) 00295 #define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52)) 00296 #define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72)) 00297 #define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92)) 00298 00299 #define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14)) 00300 #define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34)) 00301 #define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54)) 00302 #define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74)) 00303 #define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94)) 00304 00305 #define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15)) 00306 #define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25)) 00307 #define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55)) 00308 #define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75)) 00309 #define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95)) 00310 00311 #define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16)) 00312 #define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36)) 00313 #define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56)) 00314 #define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76)) 00315 #define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96)) 00316 00317 #define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17)) 00318 #define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37)) 00319 #define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57)) 00320 #define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77)) 00321 #define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97)) 00322 00323 #define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14)) 00324 #define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34)) 00325 #define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54)) 00326 #define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74)) 00327 #define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94)) 00328 00329 #define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16)) 00330 #define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36)) 00331 #define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56)) 00332 #define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76)) 00333 #define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96)) 00334 00335 #define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18)) 00336 #define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38)) 00337 #define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58)) 00338 #define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78)) 00339 #define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98)) 00340 00341 #define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19)) 00342 #define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29)) 00343 #define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59)) 00344 #define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79)) 00345 #define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99)) 00346 00347 #define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A)) 00348 #define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A)) 00349 #define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A)) 00350 #define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A)) 00351 #define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A)) 00352 00353 #define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B)) 00354 #define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B)) 00355 #define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B)) 00356 #define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B)) 00357 #define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B)) 00358 00359 #define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18)) 00360 #define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38)) 00361 #define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58)) 00362 #define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78)) 00363 #define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98)) 00364 00365 #define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A)) 00366 #define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A)) 00367 #define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A)) 00368 #define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A)) 00369 #define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A)) 00370 00371 #define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C)) 00372 #define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C)) 00373 #define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C)) 00374 #define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C)) 00375 #define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C)) 00376 00377 #define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D)) 00378 #define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D)) 00379 #define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D)) 00380 #define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D)) 00381 #define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D)) 00382 00383 #define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E)) 00384 #define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E)) 00385 #define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E)) 00386 #define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E)) 00387 #define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E)) 00388 00389 #define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F)) 00390 #define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F)) 00391 #define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F)) 00392 #define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F)) 00393 #define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F)) 00394 00395 #define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C)) 00396 #define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C)) 00397 #define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C)) 00398 #define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C)) 00399 #define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C)) 00400 00401 #define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E)) 00402 #define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E)) 00403 #define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E)) 00404 #define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E)) 00405 #define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E)) 00406 00407 00408 /* System Control Block(SCB) modules include Memory Accelerator Module, 00409 Phase Locked Loop, VPB divider, Power Control, External Interrupt, 00410 Reset, and Code Security/Debugging */ 00411 #define SCB_BASE_ADDR 0xE01FC000 00412 00413 /* Memory Accelerator Module (MAM) */ 00414 #define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000)) 00415 #define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004)) 00416 #define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040)) 00417 00418 /* Phase Locked Loop (PLL) */ 00419 #define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080)) 00420 #define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084)) 00421 #define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088)) 00422 #define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C)) 00423 00424 /* Power Control */ 00425 #define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0)) 00426 #define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4)) 00427 #define PCONP_PCI2C0 7 00428 #define PCONP_PCI2C1 19 00429 #define PCONP_PCI2C2 26 00430 00431 00432 /* Clock Divider */ 00433 // #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100)) 00434 #define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104)) 00435 #define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108)) 00436 #define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C)) 00437 #define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8)) 00438 #define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC)) 00439 00440 #define CCLKCFG_OFF 0x104 00441 #define USBCLKCFG_OFF 0x108 00442 #define CLKSRCSEL_OFF 0x10C 00443 #define PCLKSEL0_OFF 0x1A8 00444 #define PCLKSEL1_OFF 0x1AC 00445 00446 00447 /* External Interrupts */ 00448 #define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140)) 00449 #define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144)) 00450 #define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148)) 00451 #define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C)) 00452 00453 /* Reset, reset source identification */ 00454 #define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180)) 00455 00456 /* RSID, code security protection */ 00457 #define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184)) 00458 00459 /* AHB configuration */ 00460 #define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188)) 00461 #define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C)) 00462 00463 /* System Controls and Status */ 00464 #define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0)) 00465 00466 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers 00467 are for LPC24xx only. */ 00468 #define STATIC_MEM0_BASE 0x80000000 00469 #define STATIC_MEM1_BASE 0x81000000 00470 #define STATIC_MEM2_BASE 0x82000000 00471 #define STATIC_MEM3_BASE 0x83000000 00472 00473 #define DYNAMIC_MEM0_BASE 0xA0000000 00474 #define DYNAMIC_MEM1_BASE 0xB0000000 00475 #define DYNAMIC_MEM2_BASE 0xC0000000 00476 #define DYNAMIC_MEM3_BASE 0xD0000000 00477 00478 /* External Memory Controller (EMC) */ 00479 #define EMC_BASE_ADDR 0xFFE08000 00480 #define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000)) 00481 #define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004)) 00482 #define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008)) 00483 00484 /* Dynamic RAM access registers */ 00485 #define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020)) 00486 #define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024)) 00487 #define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028)) 00488 #define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030)) 00489 #define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034)) 00490 #define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038)) 00491 #define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C)) 00492 #define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040)) 00493 #define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044)) 00494 #define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048)) 00495 #define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C)) 00496 #define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050)) 00497 #define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054)) 00498 #define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058)) 00499 00500 #define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100)) 00501 #define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104)) 00502 #define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140)) 00503 #define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144)) 00504 #define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160)) 00505 #define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164)) 00506 #define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180)) 00507 #define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184)) 00508 00509 /* static RAM access registers */ 00510 #define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200)) 00511 #define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204)) 00512 #define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208)) 00513 #define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C)) 00514 #define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210)) 00515 #define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214)) 00516 #define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218)) 00517 00518 #define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220)) 00519 #define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224)) 00520 #define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228)) 00521 #define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C)) 00522 #define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230)) 00523 #define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234)) 00524 #define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238)) 00525 00526 #define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240)) 00527 #define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244)) 00528 #define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248)) 00529 #define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C)) 00530 #define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250)) 00531 #define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254)) 00532 #define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258)) 00533 00534 #define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260)) 00535 #define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264)) 00536 #define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268)) 00537 #define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C)) 00538 #define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270)) 00539 #define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274)) 00540 #define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278)) 00541 00542 #define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880)) 00543 00544 00545 /* Timer 0 */ 00546 #define TMR0_BASE_ADDR 0xE0004000 00547 #define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00)) 00548 #define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04)) 00549 #define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08)) 00550 #define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C)) 00551 #define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10)) 00552 #define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14)) 00553 #define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18)) 00554 #define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C)) 00555 #define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20)) 00556 #define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24)) 00557 #define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28)) 00558 #define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C)) 00559 #define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30)) 00560 #define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34)) 00561 #define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38)) 00562 #define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C)) 00563 #define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70)) 00564 00565 /* Timer 1 */ 00566 #define TMR1_BASE_ADDR 0xE0008000 00567 #define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00)) 00568 #define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04)) 00569 #define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08)) 00570 #define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C)) 00571 #define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10)) 00572 #define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14)) 00573 #define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18)) 00574 #define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C)) 00575 #define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20)) 00576 #define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24)) 00577 #define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28)) 00578 #define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C)) 00579 #define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30)) 00580 #define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34)) 00581 #define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38)) 00582 #define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C)) 00583 #define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70)) 00584 00585 /* Timer 2 */ 00586 #define TMR2_BASE_ADDR 0xE0070000 00587 #define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00)) 00588 #define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04)) 00589 #define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08)) 00590 #define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C)) 00591 #define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10)) 00592 #define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14)) 00593 #define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18)) 00594 #define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C)) 00595 #define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20)) 00596 #define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24)) 00597 #define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28)) 00598 #define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C)) 00599 #define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30)) 00600 #define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34)) 00601 #define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38)) 00602 #define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C)) 00603 #define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70)) 00604 00605 /* Timer 3 */ 00606 #define TMR3_BASE_ADDR 0xE0074000 00607 #define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00)) 00608 #define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04)) 00609 #define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08)) 00610 #define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C)) 00611 #define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10)) 00612 #define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14)) 00613 #define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18)) 00614 #define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C)) 00615 #define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20)) 00616 #define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24)) 00617 #define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28)) 00618 #define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C)) 00619 #define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30)) 00620 #define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34)) 00621 #define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38)) 00622 #define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C)) 00623 #define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70)) 00624 00625 00626 /* Pulse Width Modulator (PWM) */ 00627 #define PWM0_BASE_ADDR 0xE0014000 00628 #define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00)) 00629 #define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04)) 00630 #define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08)) 00631 #define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C)) 00632 #define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10)) 00633 #define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14)) 00634 #define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18)) 00635 #define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C)) 00636 #define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20)) 00637 #define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24)) 00638 #define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28)) 00639 #define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C)) 00640 #define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30)) 00641 #define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34)) 00642 #define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38)) 00643 #define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C)) 00644 #define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40)) 00645 #define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44)) 00646 #define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48)) 00647 #define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C)) 00648 #define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50)) 00649 #define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70)) 00650 00651 #define PWM1_BASE_ADDR 0xE0018000 00652 #define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00)) 00653 #define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04)) 00654 #define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08)) 00655 #define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C)) 00656 #define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10)) 00657 #define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14)) 00658 #define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18)) 00659 #define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C)) 00660 #define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20)) 00661 #define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24)) 00662 #define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28)) 00663 #define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C)) 00664 #define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30)) 00665 #define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34)) 00666 #define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38)) 00667 #define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C)) 00668 #define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40)) 00669 #define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44)) 00670 #define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48)) 00671 #define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C)) 00672 #define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50)) 00673 #define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70)) 00674 00675 00676 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */ 00677 #define UART0_BASE_ADDR 0xE000C000 00678 #define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) 00679 #define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) 00680 #define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00)) 00681 #define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) 00682 #define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04)) 00683 #define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) 00684 #define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08)) 00685 #define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C)) 00686 #define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14)) 00687 #define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C)) 00688 #define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20)) 00689 #define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24)) 00690 #define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28)) 00691 #define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30)) 00692 00693 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */ 00694 #define UART1_BASE_ADDR 0xE0010000 00695 #define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) 00696 #define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) 00697 #define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00)) 00698 #define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) 00699 #define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04)) 00700 #define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) 00701 #define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08)) 00702 #define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C)) 00703 #define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10)) 00704 #define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14)) 00705 #define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18)) 00706 #define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C)) 00707 #define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20)) 00708 #define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28)) 00709 #define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30)) 00710 00711 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */ 00712 #define UART2_BASE_ADDR 0xE0078000 00713 #define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) 00714 #define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) 00715 #define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00)) 00716 #define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) 00717 #define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04)) 00718 #define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) 00719 #define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08)) 00720 #define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C)) 00721 #define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14)) 00722 #define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C)) 00723 #define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20)) 00724 #define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24)) 00725 #define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28)) 00726 #define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30)) 00727 00728 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */ 00729 #define UART3_BASE_ADDR 0xE007C000 00730 #define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) 00731 #define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) 00732 #define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00)) 00733 #define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) 00734 #define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04)) 00735 #define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) 00736 #define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08)) 00737 #define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C)) 00738 #define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14)) 00739 #define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C)) 00740 #define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20)) 00741 #define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24)) 00742 #define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28)) 00743 #define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30)) 00744 00745 /* I2C Interface 0 */ 00746 #define I2C0_BASE_ADDR 0xE001C000 00747 #define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00)) 00748 #define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04)) 00749 #define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08)) 00750 #define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C)) 00751 #define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10)) 00752 #define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14)) 00753 #define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18)) 00754 00755 /* I2C Interface 1 */ 00756 #define I2C1_BASE_ADDR 0xE005C000 00757 #define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00)) 00758 #define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04)) 00759 #define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08)) 00760 #define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C)) 00761 #define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10)) 00762 #define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14)) 00763 #define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18)) 00764 00765 /* I2C Interface 2 */ 00766 #define I2C2_BASE_ADDR 0xE0080000 00767 #define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00)) 00768 #define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04)) 00769 #define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08)) 00770 #define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C)) 00771 #define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10)) 00772 #define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14)) 00773 #define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18)) 00774 00775 /* I2C offesets */ 00776 #define I2C_CONSET_OFF 0x00 00777 #define I2C_STAT_OFF 0x04 00778 #define I2C_DAT_OFF 0x08 00779 #define I2C_ADR_OFF 0x0C 00780 #define I2C_SCLH_OFF 0x10 00781 #define I2C_SCLL_OFF 0x14 00782 #define I2C_CONCLR_OFF 0x18 00783 00784 /* I2C register definition Clear */ 00785 #define I2CON_I2ENC 6 // I2C interface Disable bit 00786 #define I2CON_STAC 5 // START flag Clear bit 00787 #define I2CON_SIC 3 // I2C interrupt Clear bit 00788 #define I2CON_AAC 2 // Assert acknowledge Clear bit 00789 00790 /* I2C register definition Set */ 00791 #define I2CON_I2EN 6 // I2C interface enable 00792 #define I2CON_STA 5 // START flag Clear bit 00793 #define I2CON_STO 4 // STOP flag Clear bit 00794 #define I2CON_SI 3 // I2C interrupt Clear bit 00795 #define I2CON_AA 2 // Assert acknowledge Clear bit 00796 00797 /* I2C Status codes */ 00798 #define I2C_STAT_ERROR 0x00 00799 #define I2C_STAT_UNKNOW 0xF8 00800 #define I2C_STAT_SEND 0x08 00801 #define I2C_STAT_RESEND 0x10 00802 #define I2C_STAT_SLAW_ACK 0x18 00803 #define I2C_STAT_SLAW_NACK 0x20 00804 #define I2C_STAT_SLAR_ACK 0x40 00805 #define I2C_STAT_SLAR_NACK 0x48 00806 #define I2C_STAT_DATA_ACK 0x28 00807 #define I2C_STAT_DATA_NACK 0x30 00808 #define I2C_STAT_RDATA_ACK 0x50 00809 #define I2C_STAT_RDATA_NACK 0x58 00810 #define I2C_STAT_ARB_LOST 0x38 00811 00812 #define I2C0_PCLK_MASK 0xC000 00813 #define I2C0_PCLK_DIV8 0xC000 00814 #define I2C0_PCLK_DIV4 0x4000 00815 #define I2C1_PCLK_MASK 0x00C0 00816 #define I2C1_PCLK_DIV8 0x00C0 00817 #define I2C1_PCLK_DIV4 0x0040 00818 #define I2C2_PCLK_MASK 0x300000 00819 #define I2C2_PCLK_DIV8 0x300000 00820 #define I2C2_PCLK_DIV4 0x100000 00821 00822 /* I2C pins defines */ 00823 #define I2C0_PINSEL_MASK 0x3C00000 00824 #define I2C0_PINSEL 0x1400000 00825 #define I2C1_PINSEL_MASK 0x000000F 00826 #define I2C1_PINSEL 0x000000F 00827 #define I2C2_PINSEL_MASK 0x0F00000 00828 #define I2C2_PINSEL 0x0A00000 00829 00830 /* SPI0 (Serial Peripheral Interface 0) */ 00831 #define SPI0_BASE_ADDR 0xE0020000 00832 #define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00)) 00833 #define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04)) 00834 #define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08)) 00835 #define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C)) 00836 #define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C)) 00837 00838 /* SSP0 Controller */ 00839 #define SSP0_BASE_ADDR 0xE0068000 00840 #define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00)) 00841 #define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04)) 00842 #define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08)) 00843 #define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C)) 00844 #define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10)) 00845 #define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14)) 00846 #define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18)) 00847 #define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C)) 00848 #define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20)) 00849 #define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24)) 00850 00851 /* SSP1 Controller */ 00852 #define SSP1_BASE_ADDR 0xE0030000 00853 #define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00)) 00854 #define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04)) 00855 #define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08)) 00856 #define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C)) 00857 #define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10)) 00858 #define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14)) 00859 #define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18)) 00860 #define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C)) 00861 #define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20)) 00862 #define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24)) 00863 00864 00865 /* Real Time Clock */ 00866 #define RTC_BASE_ADDR 0xE0024000 00867 #define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00)) 00868 #define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04)) 00869 #define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08)) 00870 #define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C)) 00871 #define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10)) 00872 #define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14)) 00873 #define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18)) 00874 #define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C)) 00875 #define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20)) 00876 #define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24)) 00877 #define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28)) 00878 #define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C)) 00879 #define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30)) 00880 #define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34)) 00881 #define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38)) 00882 #define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C)) 00883 #define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40)) 00884 #define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60)) 00885 #define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64)) 00886 #define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68)) 00887 #define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C)) 00888 #define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70)) 00889 #define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74)) 00890 #define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78)) 00891 #define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C)) 00892 #define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80)) 00893 #define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84)) 00894 00895 00896 /* A/D Converter 0 (AD0) */ 00897 #define AD0_BASE_ADDR 0xE0034000 00898 #define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00)) 00899 #define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04)) 00900 #define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C)) 00901 #define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10)) 00902 #define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14)) 00903 #define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18)) 00904 #define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C)) 00905 #define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20)) 00906 #define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24)) 00907 #define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28)) 00908 #define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C)) 00909 #define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30)) 00910 00911 00912 /* D/A Converter */ 00913 #define DAC_BASE_ADDR 0xE006C000 00914 #define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00)) 00915 00916 00917 /* Watchdog */ 00918 #define WDG_BASE_ADDR 0xE0000000 00919 #define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00)) 00920 #define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04)) 00921 #define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08)) 00922 #define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C)) 00923 #define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10)) 00924 00925 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */ 00926 #define CAN_ACCEPT_BASE_ADDR 0xE003C000 00927 #define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00)) 00928 #define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04)) 00929 #define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08)) 00930 #define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C)) 00931 #define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10)) 00932 #define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14)) 00933 #define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18)) 00934 #define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C)) 00935 00936 #define CAN_CENTRAL_BASE_ADDR 0xE0040000 00937 #define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00)) 00938 #define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04)) 00939 #define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08)) 00940 00941 #define CAN1_BASE_ADDR 0xE0044000 00942 #define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00)) 00943 #define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04)) 00944 #define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08)) 00945 #define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C)) 00946 #define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10)) 00947 #define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14)) 00948 #define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18)) 00949 #define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C)) 00950 #define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20)) 00951 #define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24)) 00952 #define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28)) 00953 #define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C)) 00954 00955 #define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30)) 00956 #define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34)) 00957 #define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38)) 00958 #define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C)) 00959 #define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40)) 00960 #define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44)) 00961 #define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48)) 00962 #define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C)) 00963 #define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50)) 00964 #define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54)) 00965 #define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58)) 00966 #define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C)) 00967 00968 #define CAN2_BASE_ADDR 0xE0048000 00969 #define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00)) 00970 #define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04)) 00971 #define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08)) 00972 #define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C)) 00973 #define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10)) 00974 #define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14)) 00975 #define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18)) 00976 #define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C)) 00977 #define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20)) 00978 #define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24)) 00979 #define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28)) 00980 #define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C)) 00981 00982 #define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30)) 00983 #define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34)) 00984 #define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38)) 00985 #define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C)) 00986 #define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40)) 00987 #define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44)) 00988 #define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48)) 00989 #define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C)) 00990 #define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50)) 00991 #define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54)) 00992 #define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58)) 00993 #define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C)) 00994 00995 00996 /* MultiMedia Card Interface(MCI) Controller */ 00997 #define MCI_BASE_ADDR 0xE008C000 00998 #define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00)) 00999 #define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04)) 01000 #define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08)) 01001 #define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C)) 01002 #define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10)) 01003 #define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14)) 01004 #define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18)) 01005 #define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C)) 01006 #define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20)) 01007 #define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24)) 01008 #define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28)) 01009 #define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C)) 01010 #define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30)) 01011 #define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34)) 01012 #define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38)) 01013 #define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C)) 01014 #define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40)) 01015 #define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48)) 01016 #define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80)) 01017 01018 01019 /* I2S Interface Controller (I2S) */ 01020 #define I2S_BASE_ADDR 0xE0088000 01021 #define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00)) 01022 #define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04)) 01023 #define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08)) 01024 #define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C)) 01025 #define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10)) 01026 #define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14)) 01027 #define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18)) 01028 #define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C)) 01029 #define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20)) 01030 #define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24)) 01031 01032 01033 /* General-purpose DMA Controller */ 01034 #define DMA_BASE_ADDR 0xFFE04000 01035 #define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000)) 01036 #define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004)) 01037 #define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008)) 01038 #define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C)) 01039 #define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010)) 01040 #define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014)) 01041 #define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018)) 01042 #define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C)) 01043 #define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020)) 01044 #define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024)) 01045 #define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028)) 01046 #define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C)) 01047 #define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030)) 01048 #define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034)) 01049 01050 /* DMA channel 0 registers */ 01051 #define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100)) 01052 #define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104)) 01053 #define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108)) 01054 #define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C)) 01055 #define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110)) 01056 01057 /* DMA channel 1 registers */ 01058 #define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120)) 01059 #define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124)) 01060 #define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128)) 01061 #define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C)) 01062 #define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130)) 01063 01064 01065 /* USB Controller */ 01066 #define USB_INT_BASE_ADDR 0xE01FC1C0 01067 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */ 01068 01069 #define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00)) 01070 01071 /* USB Device Interrupt Registers */ 01072 #define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00)) 01073 #define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04)) 01074 #define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08)) 01075 #define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C)) 01076 #define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C)) 01077 01078 /* USB Device Endpoint Interrupt Registers */ 01079 #define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30)) 01080 #define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34)) 01081 #define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38)) 01082 #define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C)) 01083 #define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40)) 01084 01085 /* USB Device Endpoint Realization Registers */ 01086 #define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44)) 01087 #define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48)) 01088 #define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C)) 01089 01090 /* USB Device Command Reagisters */ 01091 #define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10)) 01092 #define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14)) 01093 01094 /* USB Device Data Transfer Registers */ 01095 #define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18)) 01096 #define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C)) 01097 #define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20)) 01098 #define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24)) 01099 #define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28)) 01100 01101 /* USB Device DMA Registers */ 01102 #define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50)) 01103 #define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54)) 01104 #define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58)) 01105 #define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80)) 01106 #define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84)) 01107 #define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88)) 01108 #define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C)) 01109 #define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90)) 01110 #define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94)) 01111 #define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0)) 01112 #define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4)) 01113 #define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8)) 01114 #define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC)) 01115 #define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0)) 01116 #define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4)) 01117 #define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8)) 01118 #define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC)) 01119 #define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0)) 01120 01121 /* USB Host and OTG registers are for LPC24xx only */ 01122 /* USB Host Controller */ 01123 #define USBHC_BASE_ADDR 0xFFE0C000 01124 #define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00)) 01125 #define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04)) 01126 #define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08)) 01127 #define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C)) 01128 #define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10)) 01129 #define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14)) 01130 #define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18)) 01131 #define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C)) 01132 #define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20)) 01133 #define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24)) 01134 #define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28)) 01135 #define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C)) 01136 #define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30)) 01137 #define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34)) 01138 #define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38)) 01139 #define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C)) 01140 #define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40)) 01141 #define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44)) 01142 #define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48)) 01143 #define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C)) 01144 #define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50)) 01145 #define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54)) 01146 #define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58)) 01147 01148 /* USB OTG Controller */ 01149 #define USBOTG_BASE_ADDR 0xFFE0C100 01150 #define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00)) 01151 #define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04)) 01152 #define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08)) 01153 #define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C)) 01154 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */ 01155 #define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) 01156 #define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14)) 01157 01158 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300 01159 #define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) 01160 #define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00)) 01161 #define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04)) 01162 #define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08)) 01163 #define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C)) 01164 #define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10)) 01165 01166 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are 01167 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */ 01168 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0 01169 #define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) 01170 #define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) 01171 01172 /* Note: below three register name convention is for LPC23xx USB device only, match 01173 with the spec. update in USB Device Section. */ 01174 #define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10)) 01175 #define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04)) 01176 #define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08)) 01177 01178 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */ 01179 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */ 01180 #define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */ 01181 #define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */ 01182 #define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */ 01183 #define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */ 01184 #define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */ 01185 #define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */ 01186 #define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */ 01187 #define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */ 01188 #define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */ 01189 #define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */ 01190 #define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */ 01191 #define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */ 01192 #define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */ 01193 #define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */ 01194 01195 #define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */ 01196 #define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */ 01197 #define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */ 01198 01199 #define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */ 01200 #define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */ 01201 #define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */ 01202 #define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */ 01203 #define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */ 01204 #define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */ 01205 #define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */ 01206 #define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */ 01207 #define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */ 01208 #define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */ 01209 #define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */ 01210 #define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */ 01211 01212 #define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */ 01213 #define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */ 01214 #define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */ 01215 01216 #define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */ 01217 #define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */ 01218 01219 #define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */ 01220 #define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */ 01221 #define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */ 01222 01223 #define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */ 01224 #define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */ 01225 01226 #define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */ 01227 #define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */ 01228 #define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */ 01229 #define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */ 01230 01231 #define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */ 01232 #define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */ 01233 01234 01235 /* IRQ numbers */ 01236 #define INT_I2C0 9 01237 #define INT_I2C1 19 01238 #define INT_I2C2 30 01239 #define INT_UART0 6 01240 #define INT_UART1 7 01241 #define INT_UART2 28 01242 #define INT_UART3 29 01243 01244 #endif /* LPC23XX_H */