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LM3S1968 PWM hardware definitions. More...
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Defines | |
#define | PWM_O_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) |
The following are defines for the PWM register offsets. | |
#define | PWM_CTL_GLOBALSYNC3 3 |
Defines for the bit fields in the PWM_O_CTL register. | |
#define | PWM_SYNC_SYNC3 3 |
Defines for the bit fields in the PWM_O_SYNC register. | |
#define | PWM_ENABLE_PWM7EN 7 |
Defines for the bit fields in the PWM_O_ENABLE register. | |
#define | PWM_INVERT_PWM7INV 7 |
Defines for the bit fields in the PWM_O_INVERT register. | |
#define | PWM_FAULT_FAULT7 7 |
Defines for the bit fields in the PWM_O_FAULT register. | |
#define | PWM_INTEN_INTFAULT3 19 |
Defines for the bit fields in the PWM_O_INTEN register. | |
#define | PWM_RIS_INTFAULT3 19 |
Defines for the bit fields in the PWM_O_RIS register. | |
#define | PWM_ISC_INTFAULT3 19 |
Defines for the bit fields in the PWM_O_ISC register. | |
#define | PWM_STATUS_FAULT3 3 |
Defines for the bit fields in the PWM_O_STATUS register. | |
#define | PWM_FAULTVAL_PWM7 7 |
Defines for the bit fields in the PWM_O_FAULTVAL register. | |
#define | PWM_ENUPD_ENUPD7_M 0x0000C000 |
Defines for the bit fields in the PWM_O_ENUPD register. | |
#define | PWM_X_CTL_LATCH 0x00040000 |
Defines for the bit fields in the PWM_O_X_CTL register. | |
#define | PWM_X_INTEN_TRCMPBD 0x00002000 |
Defines for the bit fields in the PWM_O_X_INTEN register. | |
#define | PWM_X_RIS_INTCMPBD 0x00000020 |
Defines for the bit fields in the PWM_O_X_RIS register. | |
#define | PWM_X_ISC_INTCMPBD 0x00000020 |
Defines for the bit fields in the PWM_O_X_ISC register. | |
#define | PWM_X_LOAD_M 0x0000FFFF |
Defines for the bit fields in the PWM_O_X_LOAD register. | |
#define | PWM_X_COUNT_M 0x0000FFFF |
Defines for the bit fields in the PWM_O_X_COUNT register. | |
#define | PWM_X_CMPA_M 0x0000FFFF |
Defines for the bit fields in the PWM_O_X_CMPA register. | |
#define | PWM_X_CMPB_M 0x0000FFFF |
Defines for the bit fields in the PWM_O_X_CMPB register. | |
#define | PWM_X_GENA_ACTCMPBD_M 0x00000C00 |
Defines for the bit fields in the PWM_O_X_GENA register. | |
#define | PWM_X_GENB_ACTCMPBD_M 0x00000C00 |
Defines for the bit fields in the PWM_O_X_GENB register. | |
#define | PWM_X_DBCTL_ENABLE 0x00000001 |
Defines for the bit fields in the PWM_O_X_DBCTL register. | |
#define | PWM_X_DBRISE_DELAY_M 0x00000FFF |
Defines for the bit fields in the PWM_O_X_DBRISE register. | |
#define | PWM_X_DBFALL_DELAY_M 0x00000FFF |
Defines for the bit fields in the PWM_O_X_DBFALL register. | |
#define | PWM_X_FLTSRC0_FAULT3 0x00000008 |
Defines for the bit fields in the PWM_O_X_FLTSRC0 register. | |
#define | PWM_X_FLTSRC1_DCMP7 0x00000080 |
The following are defines for the bit fields in the PWM_O_X_FLTSRC1 register. | |
#define | PWM_X_MINFLTPER_M 0x0000FFFF |
Defines for the bit fields in the PWM_O_X_MINFLTPER register. | |
#define | PWM_X_FLTSEN_FAULT3 0x00000008 |
Defines for the bit fields in the PWM_O_X_FLTSEN register. | |
#define | PWM_X_FLTSTAT0_FAULT3 0x00000008 |
Defines for the bit fields in the PWM_O_X_FLTSTAT0 register. | |
#define | PWM_X_FLTSTAT1_DCMP7 0x00000080 |
Defines for the bit fields in the PWM_O_X_FLTSTAT1 register. | |
#define | PWM_O_X_CTL (*((reg32_t *)(PWMC_BASE + 0x00000000))) |
Defines for the PWM Generator standard offsets. | |
#define | PWM_O_X_FLTSEN (*((reg32_t *)(PWMC_BASE + 0x00000000))) |
Defines for the PWM Generator extended offsets. |
LM3S1968 PWM hardware definitions.
Definition in file lm3s_pwm.h.