BeRTOS
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00001 00037 #ifndef SSI_LM3S_H 00038 #define SSI_LM3S_H 00039 00040 #include <cpu/power.h> /* cpu_relax() */ 00041 #include <io/kfile.h> /* KFile */ 00042 #include <io/lm3s.h> 00043 00047 /*\{*/ 00048 #define SSI_FRF_MOTO_MODE_0 0x00000000 //< Moto fmt, polarity 0, phase 0 00049 #define SSI_FRF_MOTO_MODE_1 0x00000002 //< Moto fmt, polarity 0, phase 1 00050 #define SSI_FRF_MOTO_MODE_2 0x00000001 //< Moto fmt, polarity 1, phase 0 00051 #define SSI_FRF_MOTO_MODE_3 0x00000003 //< Moto fmt, polarity 1, phase 1 00052 #define SSI_FRF_TI 0x00000010 //< TI frame format 00053 #define SSI_FRF_NMW 0x00000020 //< National MicroWire frame format 00054 /*\}*/ 00055 00059 /*\{*/ 00060 #define SSI_MODE_MASTER 0x00000000 //< SSI master 00061 #define SSI_MODE_SLAVE 0x00000001 //< SSI slave 00062 #define SSI_MODE_SLAVE_OD 0x00000002 //< SSI slave with output disabled 00063 /*\}*/ 00064 00065 /* LM3S SSI handle properties */ 00066 enum 00067 { 00068 /* Non-blocking I/O */ 00069 LM3S_SSI_NONBLOCK = 1, 00070 }; 00071 00073 typedef struct LM3SSSI 00074 { 00075 /* SSI Kfile structure */ 00076 KFile fd; 00077 00078 /* Handle properties */ 00079 uint32_t flags; 00080 00081 /* SSI port address */ 00082 uint32_t addr; 00083 } LM3SSSI; 00084 00088 #define KFT_LM3SSSI MAKE_ID('L', 'S', 'S', 'I') 00089 00090 INLINE LM3SSSI *LM3SSSI_CAST(KFile *fd) 00091 { 00092 ASSERT(fd->_type == KFT_LM3SSSI); 00093 return (LM3SSSI *)fd; 00094 } 00095 00096 /* KFile interface to LM3S SSI */ 00097 void lm3s_ssiInit(struct LM3SSSI *fds, uint32_t addr, uint32_t frame, int mode, 00098 int bitrate, uint32_t data_width); 00099 00100 /* Raw interface to LM3S SSI */ 00101 int lm3s_ssiOpen(uint32_t addr, uint32_t frame, int mode, 00102 int bitrate, uint32_t data_width); 00103 00104 /* 00105 * Check if the SSI transmitter is busy or not 00106 * 00107 * This allows to determine whether the TX FIFO have been cleared by the 00108 * hardware, so the transmission can be safely considered completed. 00109 */ 00110 INLINE bool lm3s_ssiTxDone(uint32_t base) 00111 { 00112 return (HWREG(base + SSI_O_SR) & SSI_SR_BSY) ? true : false; 00113 } 00114 00115 /* 00116 * Check if the SSI TX FIFO is full 00117 */ 00118 INLINE bool lm3s_ssiTxReady(uint32_t base) 00119 { 00120 return (HWREG(base + SSI_O_SR) & SSI_SR_TNF) ? true : false; 00121 } 00122 00123 /* 00124 * Check for data available in the RX FIFO 00125 */ 00126 INLINE bool lm3s_ssiRxReady(uint32_t base) 00127 { 00128 return (HWREG(base + SSI_O_SR) & SSI_SR_RNE) ? true : false; 00129 } 00130 00131 /* 00132 * Get a frame into the SSI receive FIFO without blocking. 00133 * 00134 * Return the number of frames read from the RX FIFO. 00135 */ 00136 INLINE int lm3s_ssiReadFrameNonBlocking(uint32_t base, uint32_t *val) 00137 { 00138 /* Check for data available in the RX FIFO */ 00139 if (!lm3s_ssiRxReady(base)) 00140 return 0; 00141 /* Read data from SSI RX FIFO */ 00142 *val = HWREG(base + SSI_O_DR); 00143 return 1; 00144 } 00145 00146 /* 00147 * Get a frame from the SSI receive FIFO. 00148 */ 00149 INLINE void lm3s_ssiReadFrame(uint32_t base, uint32_t *val) 00150 { 00151 /* Wait for data available in the RX FIFO */ 00152 while (!lm3s_ssiRxReady(base)) 00153 cpu_relax(); 00154 /* Read data from SSI RX FIFO */ 00155 *val = HWREG(base + SSI_O_DR); 00156 } 00157 00158 /* 00159 * Put a frame into the SSI transmit FIFO without blocking. 00160 * 00161 * NOTE: the upper bits of the frame will be automatically discarded by the 00162 * hardware according to the frame data width. 00163 * 00164 * Return the number of frames written to the TX FIFO. 00165 */ 00166 INLINE int lm3s_ssiWriteFrameNonBlocking(uint32_t base, uint32_t val) 00167 { 00168 /* Check for available space in the TX FIFO */ 00169 if (!lm3s_ssiTxReady(base)) 00170 return 0; 00171 /* Enqueue data to the TX FIFO */ 00172 HWREG(base + SSI_O_DR) = val; 00173 return 1; 00174 } 00175 00176 /* 00177 * Put a frame into the SSI transmit FIFO. 00178 * 00179 * NOTE: the upper bits of the frame will be automatically discarded by the 00180 * hardware according to the frame data width. 00181 */ 00182 INLINE void lm3s_ssiWriteFrame(uint32_t base, uint32_t val) 00183 { 00184 /* Wait for available space in the TX FIFO */ 00185 while (!lm3s_ssiTxReady(base)) 00186 cpu_relax(); 00187 /* Enqueue data to the TX FIFO */ 00188 HWREG(base + SSI_O_DR) = val; 00189 } 00190 00191 #endif /* SSI_LM3S_H */