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stm32_adc.h
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00001 
00036 #ifndef STM32_ADC_H
00037 #define STM32_ADC_H
00038 
00039 #include <cpu/types.h>
00040 
00041 /* ADC dual mode */
00042 #define ADC_MODE_INDEPENDENT                       ((uint32_t)0x00000000)
00043 #define ADC_MODE_REGINJECSIMULT                    ((uint32_t)0x00010000)
00044 #define ADC_MODE_REGSIMULT_ALTERTRIG               ((uint32_t)0x00020000)
00045 #define ADC_MODE_INJECSIMULT_FASTINTERL            ((uint32_t)0x00030000)
00046 #define ADC_MODE_INJECSIMULT_SLOWINTERL            ((uint32_t)0x00040000)
00047 #define ADC_MODE_INJECSIMULT                       ((uint32_t)0x00050000)
00048 #define ADC_MODE_REGSIMULT                         ((uint32_t)0x00060000)
00049 #define ADC_MODE_FASTINTERL                        ((uint32_t)0x00070000)
00050 #define ADC_MODE_SLOWINTERL                        ((uint32_t)0x00080000)
00051 #define ADC_MODE_ALTERTRIG                         ((uint32_t)0x00090000)
00052 
00053 /* ADC extrenal trigger sources for regular channels conversion */
00054 #define ADC_EXTERNALTRIGCONV_T1_CC1                ((uint32_t)0x00000000)
00055 #define ADC_EXTERNALTRIGCONV_T1_CC2                ((uint32_t)0x00020000)
00056 #define ADC_EXTERNALTRIGCONV_T1_CC3                ((uint32_t)0x00040000)
00057 #define ADC_EXTERNALTRIGCONV_T2_CC2                ((uint32_t)0x00060000)
00058 #define ADC_EXTERNALTRIGCONV_T3_TRGO               ((uint32_t)0x00080000)
00059 #define ADC_EXTERNALTRIGCONV_T4_CC4                ((uint32_t)0x000A0000)
00060 #define ADC_EXTERNALTRIGCONV_EXT_IT11              ((uint32_t)0x000C0000)
00061 #define ADC_EXTERNALTRIGCONV_NONE                  ((uint32_t)0x000E0000)
00062 
00063 /* ADC data align */
00064 #define ADC_DATAALIGN_RIGHT                        ((uint32_t)0x00000000)
00065 #define ADC_DATAALIGN_LEFT                         ((uint32_t)0x00000800)
00066 
00067 /* ADC channels */
00068 #define ADC_CHANNEL_0                               ((uint8_t)0x00)
00069 #define ADC_CHANNEL_1                               ((uint8_t)0x01)
00070 #define ADC_CHANNEL_2                               ((uint8_t)0x02)
00071 #define ADC_CHANNEL_3                               ((uint8_t)0x03)
00072 #define ADC_CHANNEL_4                               ((uint8_t)0x04)
00073 #define ADC_CHANNEL_5                               ((uint8_t)0x05)
00074 #define ADC_CHANNEL_6                               ((uint8_t)0x06)
00075 #define ADC_CHANNEL_7                               ((uint8_t)0x07)
00076 #define ADC_CHANNEL_8                               ((uint8_t)0x08)
00077 #define ADC_CHANNEL_9                               ((uint8_t)0x09)
00078 #define ADC_CHANNEL_10                              ((uint8_t)0x0A)
00079 #define ADC_CHANNEL_11                              ((uint8_t)0x0B)
00080 #define ADC_CHANNEL_12                              ((uint8_t)0x0C)
00081 #define ADC_CHANNEL_13                              ((uint8_t)0x0D)
00082 #define ADC_CHANNEL_14                              ((uint8_t)0x0E)
00083 #define ADC_CHANNEL_15                              ((uint8_t)0x0F)
00084 #define ADC_CHANNEL_16                              ((uint8_t)0x10)
00085 #define ADC_CHANNEL_17                              ((uint8_t)0x11)
00086 
00087 /* ADC sampling times */
00088 #define ADC_SAMPLETIME_1CYCLES5                    ((uint8_t)0x00)
00089 #define ADC_SAMPLETIME_7CYCLES5                    ((uint8_t)0x01)
00090 #define ADC_SAMPLETIME_13CYCLES5                   ((uint8_t)0x02)
00091 #define ADC_SAMPLETIME_28CYCLES5                   ((uint8_t)0x03)
00092 #define ADC_SAMPLETIME_41CYCLES5                   ((uint8_t)0x04)
00093 #define ADC_SAMPLETIME_55CYCLES5                   ((uint8_t)0x05)
00094 #define ADC_SAMPLETIME_71CYCLES5                   ((uint8_t)0x06)
00095 #define ADC_SAMPLETIME_239CYCLES5                  ((uint8_t)0x07)
00096 
00097 /* ADC extrenal trigger sources for injected channels conversion */
00098 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO          ((uint32_t)0x00000000)
00099 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4           ((uint32_t)0x00001000)
00100 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO          ((uint32_t)0x00002000)
00101 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1           ((uint32_t)0x00003000)
00102 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4           ((uint32_t)0x00004000)
00103 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO          ((uint32_t)0x00005000)
00104 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15         ((uint32_t)0x00006000)
00105 #define ADC_EXTERNALTRIGINJECCONV_NONE             ((uint32_t)0x00007000)
00106 
00107 /* ADC injected channel selection */
00108 #define ADC_INJECTEDCHANNEL_1                       ((uint8_t)0x14)
00109 #define ADC_INJECTEDCHANNEL_2                       ((uint8_t)0x18)
00110 #define ADC_INJECTEDCHANNEL_3                       ((uint8_t)0x1C)
00111 #define ADC_INJECTEDCHANNEL_4                       ((uint8_t)0x20)
00112 
00113 /* ADC analog watchdog selection */
00114 #define ADC_ANALOGWATCHDOG_SINGLEREGENABLE         ((uint32_t)0x00800200)
00115 #define ADC_ANALOGWATCHDOG_SINGLEINJECENABLE       ((uint32_t)0x00400200)
00116 #define ADC_ANALOGWATCHDOG_SINGLEREGORINJECENABLE  ((uint32_t)0x00C00200)
00117 #define ADC_ANALOGWATCHDOG_ALLREGENABLE            ((uint32_t)0x00800000)
00118 #define ADC_ANALOGWATCHDOG_ALLINJECENABLE          ((uint32_t)0x00400000)
00119 #define ADC_ANALOGWATCHDOG_ALLREGALLINJECENABLE    ((uint32_t)0x00C00000)
00120 #define ADC_ANALOGWATCHDOG_NONE                    ((uint32_t)0x00000000)
00121 
00122 /* ADC interrupts definition */
00123 #define ADC_IT_EOC                                 ((uint16_t)0x0220)
00124 #define ADC_IT_AWD                                 ((uint16_t)0x0140)
00125 #define ADC_IT_JEOC                                ((uint16_t)0x0480)
00126 
00127 /* ADC flags definition */
00128 #define ADC_FLAG_AWD                               ((uint8_t)0x01)
00129 #define ADC_FLAG_EOC                               ((uint8_t)0x02)
00130 #define ADC_FLAG_JEOC                              ((uint8_t)0x04)
00131 #define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
00132 #define ADC_FLAG_STRT                              ((uint8_t)0X10)
00133 
00134 
00135 /* ADC ADON mask */
00136 #define CR2_ADON_SET               ((uint32_t)0x00000001)
00137 #define CR2_ADON_RESET             ((uint32_t)0xFFFFFFFE)
00138 
00139 /* ADC DMA mask */
00140 #define CR2_DMA_SET                ((uint16_t)0x0100)
00141 #define CR2_DMA_RESET              ((uint16_t)0xFEFF)
00142 
00143 /* ADC RSTCAL mask */
00144 #define CR2_RSTCAL_SET             ((uint16_t)0x0008)
00145 
00146 /* ADC CAL mask */
00147 #define CR2_CAL_SET                ((uint16_t)0x0004)
00148 
00149 /* ADC SWSTRT mask */
00150 #define CR2_SWSTRT_SET             ((uint32_t)0x00400000)
00151 
00152 /* ADC DISCNUM mask */
00153 #define CR1_DISCNUM_RESET          ((uint32_t)0xFFFF1FFF)
00154 
00155 /* ADC DISCEN mask */
00156 #define CR1_DISCEN_SET             ((uint32_t)0x00000800)
00157 #define CR1_DISCEN_RESET           ((uint32_t)0xFFFFF7FF)
00158 
00159 /* ADC EXTTRIG mask */
00160 #define CR2_EXTTRIG_SET            ((uint32_t)0x00100000)
00161 #define CR2_EXTTRIG_RESET          ((uint32_t)0xFFEFFFFF)
00162 
00163 /* ADC Software start mask */
00164 #define CR2_EXTTRIG_SWSTRT_SET     ((uint32_t)0x00500000)
00165 #define CR2_EXTTRIG_SWSTRT_RESET   ((uint32_t)0xFFAFFFFF)
00166 
00167 /* ADC JAUTO mask */
00168 #define CR1_JAUTO_SET              ((uint32_t)0x00000400)
00169 #define CR1_JAUTO_RESET            ((uint32_t)0xFFFFFBFF)
00170 
00171 /* ADC JDISCEN mask */
00172 #define CR1_JDISCEN_SET            ((uint32_t)0x00001000)
00173 #define CR1_JDISCEN_RESET          ((uint32_t)0xFFFFEFFF)
00174 
00175 /* ADC JEXTSEL mask */
00176 #define CR2_JEXTSEL_RESET          ((uint32_t)0xFFFF8FFF)
00177 
00178 /* ADC JEXTTRIG mask */
00179 #define CR2_JEXTTRIG_SET           ((uint32_t)0x00008000)
00180 #define CR2_JEXTTRIG_RESET         ((uint32_t)0xFFFF7FFF)
00181 
00182 /* ADC JSWSTRT mask */
00183 #define CR2_JSWSTRT_SET            ((uint32_t)0x00200000)
00184 
00185 /* ADC injected software start mask */
00186 #define CR2_JEXTTRIG_JSWSTRT_SET   ((uint32_t)0x00208000)
00187 #define CR2_JEXTTRIG_JSWSTRT_RESET ((uint32_t)0xFFDF7FFF)
00188 
00189 /* ADC AWDCH mask */
00190 #define CR1_AWDCH_RESET            ((uint32_t)0xFFFFFFE0)
00191 
00192 /* ADC SQx mask */
00193 #define SQR3_SQ_MASK                ((uint8_t)0x1F)
00194 #define SQR2_SQ_MASK                ((uint8_t)0x1F)
00195 #define SQR1_SQ_MASK                ((uint8_t)0x1F)
00196 #define SQR1_SQ_LEN_MASK                       0xF
00197 #define SQR1_SQ_LEN_SHIFT                       20
00198 
00199 /* ADC JSQx mask */
00200 #define JSQR_JSQ_SET               ((uint8_t)0x1F)
00201 
00202 /* ADC JL mask */
00203 #define JSQR_JL_RESET              ((uint32_t)0xFFCFFFFF)
00204 
00205 /* ADC SMPx mask */
00206 #define SMPR1_SMP_SET              ((uint8_t)0x07)
00207 #define SMPR2_SMP_SET              ((uint8_t)0x07)
00208 
00209 /* ADC Analog watchdog enable mode mask */
00210 #define CR1_AWDMODE_RESET          ((uint32_t)0xFF3FFDFF)
00211 
00212 /* ADC TSPD mask */
00213 #define CR2_TSVREFE_SET            ((uint32_t)0x00800000)
00214 #define CR2_TSVREFE_RESET          ((uint32_t)0xFF7FFFFF)
00215 
00216 /* ADC JDRx registers= offset */
00217 #define JDR_OFFSET                 ((uint8_t)0x28)
00218 
00219 /* ADC CR1 register */
00220 #define CR1_EOCIE                                      5
00221 #define CR1_AWDIE                                      6
00222 #define CR1_JEOCIE                                     7
00223 #define CR1_SCAN                                       8
00224 #define CR1_AWDSGL                                     9
00225 #define CR1_JAUTO                                     10
00226 #define CR1_DISCEN                                    11
00227 #define CR1_JDISCEN                                   12
00228 #define CR1_JAWDEN                                    22
00229 #define CR1_AWDEN                                     23
00230 
00231 /* ADC CR2 register */
00232 #define CR2_ADON                                       0
00233 #define CR2_CONT                                       1
00234 #define CR2_CAL                                        2
00235 #define CR2_RTSCAL                                     3
00236 #define CR2_DMA                                        8
00237 #define CR2_ALIGN                                     11
00238 #define CR2_JEXTTRIG                                  15
00239 #define CR2_EXTTRIG                                   20
00240 #define CR2_JSWSTART                                  21
00241 #define CR2_SWSTART                                   22
00242 #define CR2_TSVREFE                                   23
00243 
00244 /* ADC status */
00245 #define SR_AWD                                         0
00246 #define SR_EOC                                         1
00247 #define SR_JEOC                                        2
00248 #define SR_JSTRT                                       3
00249 #define SR_STRT                                        4
00250 
00251 /* ADC sample time */
00252 #define SMPR1_CH17                                    21
00253 #define SMPR1_CH16                                    18
00254 #define SMPR1_CH15                                    15
00255 #define SMPR1_CH14                                    12
00256 #define SMPR1_CH13                                     9
00257 #define SMPR1_CH12                                     6
00258 #define SMPR1_CH11                                     3
00259 #define SMPR1_CH10                                     0
00260 
00261 #define SMPR2_CH9                                     27
00262 #define SMPR2_CH8                                     24
00263 #define SMPR2_CH7                                     21
00264 #define SMPR2_CH6                                     18
00265 #define SMPR2_CH5                                     15
00266 #define SMPR2_CH4                                     12
00267 #define SMPR2_CH3                                      9
00268 #define SMPR2_CH2                                      6
00269 #define SMPR2_CH1                                      3
00270 #define SMPR2_CH0                                      0
00271 
00272 /* ADC registers Masks */
00273 #define CR1_ADC_CLEAR_MASK             ((uint32_t)0xFFF0FEFF)
00274 #define CR2_ADC_CLEAR_MASK             ((uint32_t)0xFFF1F7FD)
00275 #define SQR1_CLEAR_MASK                ((uint32_t)0xFF0FFFFF)
00276 
00277 
00278 
00279 /* ADC defines for SMT32F103Bxx */
00280 #define ADC_TEMP_V25         4300  // uV / C
00281 #define ADC_TEMP_SLOPE       1430  // mV
00282 #define ADC_TEMP_CONST      25000
00283 #define ADC_TEMP_CH            16
00284 #define ADC_VREFINT_CH         17
00285 
00286 struct stm32_adc
00287 {
00288     reg32_t SR;
00289     reg32_t CR1;
00290     reg32_t CR2;
00291     reg32_t SMPR1;
00292     reg32_t SMPR2;
00293     reg32_t JOFR1;
00294     reg32_t JOFR2;
00295     reg32_t JOFR3;
00296     reg32_t JOFR4;
00297     reg32_t HTR;
00298     reg32_t LTR;
00299     reg32_t SQR1;
00300     reg32_t SQR2;
00301     reg32_t SQR3;
00302     reg32_t JSQR;
00303     reg32_t JDR1;
00304     reg32_t JDR2;
00305     reg32_t JDR3;
00306     reg32_t JDR4;
00307     reg32_t DR;
00308 };
00309 
00310 #endif /* STM32_ADC_H */