BeRTOS
stm32_i2c.h
Go to the documentation of this file.
00001 
00036 #ifndef STM32_I2C_H
00037 #define STM32_I2C_H
00038 
00039 #include <cpu/types.h>
00040 
00041 
00042 /* I2C_modes */
00043 #define I2C_MODE_I2C                    ((uint16_t)0x0000)
00044 #define I2C_MODE_SMBUSDEVICE            ((uint16_t)0x0002)
00045 #define I2C_MODE_SMBUSHOST              ((uint16_t)0x000A)
00046 
00047 /* I2C_duty_cycle_in_fast_mode */
00048 #define I2C_DUTYCYCLE_16_9              ((uint16_t)0x4000)
00049 #define I2C_DUTYCYCLE_2                 ((uint16_t)0xBFFF)
00050 
00051 /* I2C_cknowledgementy */
00052 #define I2C_ACK_ENABLE                  ((uint16_t)0x0400)
00053 #define I2C_ACK_DISABLE                 ((uint16_t)0x0000)
00054 
00055 /* I2C_transfer_direction */
00056 #define I2C_DIRECTION_TRANSMITTER      ((uint8_t)0x00)
00057 #define I2C_DIRECTION_RECEIVER         ((uint8_t)0x01)
00058 
00059 /* I2C_acknowledged_address_defines  */
00060 #define I2C_ACKNOWLEDGEDADDRESS_7BIT    ((uint16_t)0x4000)
00061 #define I2C_ACKNOWLEDGEDADDRESS_10BIT   ((uint16_t)0xC000)
00062 
00063 /* I2C_registers */
00064 #define I2C_REGISTER_CR1                ((uint8_t)0x00)
00065 #define I2C_REGISTER_CR2                ((uint8_t)0x04)
00066 #define I2C_REGISTER_OAR1               ((uint8_t)0x08)
00067 #define I2C_REGISTER_OAR2               ((uint8_t)0x0C)
00068 #define I2C_REGISTER_DR                 ((uint8_t)0x10)
00069 #define I2C_REGISTER_SR1                ((uint8_t)0x14)
00070 #define I2C_REGISTER_SR2                ((uint8_t)0x18)
00071 #define I2C_REGISTER_CCR                ((uint8_t)0x1C)
00072 #define I2C_REGISTER_TRISE              ((uint8_t)0x20)
00073 
00074 /* I2C_SMBus_alert_pin_level  */
00075 #define I2C_SMBUSALERT_LOW              ((uint16_t)0x2000)
00076 #define I2C_SMBUSALERT_HIGH             ((uint16_t)0xDFFF)
00077 
00078 /* I2C_PEC_position  */
00079 #define I2C_PECPOSITION_NEXT            ((uint16_t)0x0800)
00080 #define I2C_PECPOSITION_CURRENT         ((uint16_t)0xF7FF)
00081 
00082 /* I2C_interrupts_definition  */
00083 #define I2C_IT_BUF                      ((uint16_t)0x0400)
00084 #define I2C_IT_EVT                      ((uint16_t)0x0200)
00085 #define I2C_IT_ERR                      ((uint16_t)0x0100)
00086 
00087 /* I2C_interrupts_definition  */
00088 #define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
00089 #define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
00090 #define I2C_IT_PECERR                   ((uint32_t)0x01001000)
00091 #define I2C_IT_OVR                      ((uint32_t)0x01000800)
00092 #define I2C_IT_AF                       ((uint32_t)0x01000400)
00093 #define I2C_IT_ARLO                     ((uint32_t)0x01000200)
00094 #define I2C_IT_BERR                     ((uint32_t)0x01000100)
00095 #define I2C_IT_TXE                      ((uint32_t)0x06000080)
00096 #define I2C_IT_RXNE                     ((uint32_t)0x06000040)
00097 #define I2C_IT_STOPF                    ((uint32_t)0x02000010)
00098 #define I2C_IT_ADD10                    ((uint32_t)0x02000008)
00099 #define I2C_IT_BTF                      ((uint32_t)0x02000004)
00100 #define I2C_IT_ADDR                     ((uint32_t)0x02000002)
00101 #define I2C_IT_SB                       ((uint32_t)0x02000001)
00102 
00103 /* SR2 register flags  */
00104 #define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
00105 #define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
00106 #define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
00107 #define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
00108 #define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
00109 #define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
00110 #define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
00111 
00112 /* SR1 register flags  */
00113 #define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
00114 #define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
00115 #define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
00116 #define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
00117 #define I2C_FLAG_AF                     ((uint32_t)0x10000400)
00118 #define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
00119 #define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
00120 #define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
00121 #define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
00122 #define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
00123 #define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
00124 #define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
00125 #define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
00126 #define I2C_FLAG_SB                     ((uint32_t)0x10000001)
00127 
00128 /* EV1  */
00129 #define I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
00130 #define I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
00131 #define I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
00132 #define I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
00133 #define I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
00134 
00135 /* EV2  */
00136 #define I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
00137 
00138 /* EV3 */
00139 #define I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
00140 
00141 /* EV4 */
00142 #define I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
00143 
00144 /* EV5 */
00145 #define I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
00146 
00147 
00148 /* EV6 */
00149 #define I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
00150 #define I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
00151 
00152 /* EV7 */
00153 #define I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
00154 
00155 /* EV8 */
00156 #define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
00157 
00158 /* EV8_2 */
00159 #define I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
00160 
00161 /* EV9 */
00162 #define I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
00163 
00164 /* EV3_2 */
00165 #define I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
00166 
00167 
00168 
00169 /* I2C SPE mask */
00170 #define CR1_PE_SET              ((uint16_t)0x0001)
00171 #define CR1_PE_RESET            ((uint16_t)0xFFFE)
00172 
00173 /* I2C START mask */
00174 #define CR1_START_SET           ((uint16_t)0x0100)
00175 #define CR1_START_RESET         ((uint16_t)0xFEFF)
00176 
00177 /* I2C STOP mask */
00178 #define CR1_STOP_SET            ((uint16_t)0x0200)
00179 #define CR1_STOP_RESET          ((uint16_t)0xFDFF)
00180 
00181 /* I2C ACK mask */
00182 #define CR1_ACK_SET             ((uint16_t)0x0400)
00183 #define CR1_ACK_RESET           ((uint16_t)0xFBFF)
00184 
00185 /* I2C ENGC mask */
00186 #define CR1_ENGC_SET            ((uint16_t)0x0040)
00187 #define CR1_ENGC_RESET          ((uint16_t)0xFFBF)
00188 
00189 /* I2C SWRST mask */
00190 #define CR1_SWRST_SET           ((uint16_t)0x8000)
00191 #define CR1_SWRST_RESET         ((uint16_t)0x7FFF)
00192 
00193 /* I2C PEC mask */
00194 #define CR1_PEC_SET             ((uint16_t)0x1000)
00195 #define CR1_PEC_RESET           ((uint16_t)0xEFFF)
00196 
00197 /* I2C ENPEC mask */
00198 #define CR1_ENPEC_SET           ((uint16_t)0x0020)
00199 #define CR1_ENPEC_RESET         ((uint16_t)0xFFDF)
00200 
00201 /* I2C ENARP mask */
00202 #define CR1_ENARP_SET           ((uint16_t)0x0010)
00203 #define CR1_ENARP_RESET         ((uint16_t)0xFFEF)
00204 
00205 /* I2C NOSTRETCH mask */
00206 #define CR1_NOSTRETCH_SET       ((uint16_t)0x0080)
00207 #define CR1_NOSTRETCH_RESET     ((uint16_t)0xFF7F)
00208 
00209 /* I2C registers Masks */
00210 #define CR1_CLEAR_MASK          ((uint16_t)0xFBF5)
00211 
00212 /* I2C DMAEN mask */
00213 #define CR2_DMAEN_SET           ((uint16_t)0x0800)
00214 #define CR2_DMAEN_RESET         ((uint16_t)0xF7FF)
00215 
00216 /* I2C LAST mask */
00217 #define CR2_LAST_SET            ((uint16_t)0x1000)
00218 #define CR2_LAST_RESET          ((uint16_t)0xEFFF)
00219 
00220 /* I2C FREQ mask */
00221 #define CR2_FREQ_RESET          ((uint16_t)0xFFC0)
00222 
00223 #define CR2_FREQ_36MHZ          ((uint16_t)0x100100)
00224 
00225 /* I2C ADD0 mask */
00226 #define OAR1_ADD0_SET           ((uint16_t)0x0001)
00227 #define OAR1_ADD0_RESET         ((uint16_t)0xFFFE)
00228 
00229 /* I2C ENDUAL mask */
00230 #define OAR2_ENDUAL_SET         ((uint16_t)0x0001)
00231 #define OAR2_ENDUAL_RESET       ((uint16_t)0xFFFE)
00232 
00233 /* I2C ADD2 mask */
00234 #define OAR2_ADD2_RESET         ((uint16_t)0xFF01)
00235 
00236 /* I2C F/S mask */
00237 #define CCR_FS_SET              ((uint16_t)0x8000)
00238 
00239 /* I2C CCR mask */
00240 #define CCR_CCR_SET             ((uint16_t)0x0FFF)
00241 
00242 
00243 /* I2C CR1 */
00244 #define CR1_POS_SET                ((uint16_t)0x800)
00245 #define CR1_POS_RESET                 (~CR1_POS_SET)
00246 
00247 /* I2C Status */
00248 #define SR1_PECERR                              12
00249 #define SR1_OVR                                 11
00250 #define SR1_AF                                  10
00251 #define SR1_ARLO                                 9
00252 #define SR1_BERR                                 8
00253 #define SR1_TXE                                  7
00254 #define SR1_RXNE                                 6
00255 #define SR1_ADDR                                 1
00256 #define SR1_BTF                                  2
00257 #define SR1_SB                                   0
00258 
00259 #define SR2_TRA                                  2
00260 #define SR2_BUSY                                 1
00261 #define SR2_MSL                                  0
00262 
00263 
00264 #define SR1_ERR_MASK        (BV(SR1_PECERR) | \
00265                              BV(SR1_OVR)    | \
00266                              BV(SR1_AF)     | \
00267                              BV(SR1_ARLO)   | \
00268                              BV(SR1_BERR))
00269 
00270 struct stm32_i2c
00271 {
00272     reg16_t CR1;
00273     uint16_t  RESERVED0;
00274     reg16_t CR2;
00275     uint16_t  RESERVED1;
00276     reg16_t OAR1;
00277     uint16_t  RESERVED2;
00278     reg16_t OAR2;
00279     uint16_t  RESERVED3;
00280     reg16_t DR;
00281     uint16_t  RESERVED4;
00282     reg16_t SR1;
00283     uint16_t  RESERVED5;
00284     reg16_t SR2;
00285     uint16_t  RESERVED6;
00286     reg16_t CCR;
00287     uint16_t  RESERVED7;
00288     reg16_t TRISE;
00289     uint16_t  RESERVED8;
00290 };
00291 
00292 #endif /* STM32_I2C_H */