BeRTOS
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00001 00038 #include <hw/hw_cpufreq.h> /* for CPU_FREQ */ 00039 #include "hw/hw_ser.h" /* Required for bus macros overrides */ 00040 00041 #include "cfg/cfg_debug.h" 00042 #include <cfg/macros.h> /* for BV(), DIV_ROUND */ 00043 00044 #include <io/lpc23xx.h> 00045 00046 #if CONFIG_KDEBUG_PORT == 0 00047 #define KDBG_WAIT_READY() while (!(U0LSR & BV(5))) {} 00048 #define KDBG_WAIT_TXDONE() while (!(U0LSR & BV(6))) {} 00049 00050 #define KDBG_WRITE_CHAR(c) do { U0THR = (c); } while(0) 00051 00052 #define KDBG_MASK_IRQ(old) do { \ 00053 (old) = U0IER; \ 00054 U0IER &= ~BV(1); \ 00055 } while(0) 00056 00057 #define KDBG_RESTORE_IRQ(old) do { \ 00058 KDBG_WAIT_TXDONE(); \ 00059 U0IER = (old); \ 00060 } while(0) 00061 00062 typedef uint32_t kdbg_irqsave_t; 00063 00064 #else 00065 #error CONFIG_KDEBUG_PORT should be 0 00066 #endif 00067 00068 00069 INLINE void kdbg_hw_init(void) 00070 { 00071 #if CONFIG_KDEBUG_PORT == 0 00072 /* Enable clock for UART0 */ 00073 PCONP = BV(3); 00074 /* Set UART0 clk to CPU_FREQ */ 00075 PCLKSEL0 &= ~0xC0; 00076 PCLKSEL0 |= 0x40; 00077 /* Set 8bit, 1 stop bit, no parity, DLAB = 1 (enable divisor modify) */ 00078 U0LCR = 0x83; 00079 U0DLL = DIV_ROUND(CPU_FREQ, 16 * CONFIG_KDEBUG_BAUDRATE) & 0xFF; 00080 U0DLM = (DIV_ROUND(CPU_FREQ, 16 * CONFIG_KDEBUG_BAUDRATE) >> 8) & 0xFF; 00081 U0FDR = 0x10; 00082 /* Assign TX pin to UART0*/ 00083 PINSEL0 &= ~0x30; 00084 PINSEL0 |= 0x10; 00085 /* Set 8bit, 1 stop bit, no parity, DLAB = 0 (disable divisor modify) */ 00086 U0LCR = 0x03; 00087 /* Enable transmitter */ 00088 U0TER = BV(7); 00089 #else 00090 #error CONFIG_KDEBUG_PORT should be 0 00091 #endif /* CONFIG_KDEBUG_PORT == 0 */ 00092 }