BeRTOS
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00001 00038 #include <cpu/irq.h> 00039 #include <drv/vic_lpc2.h> 00040 #include <io/lpc23xx.h> 00041 00042 #if CPU_FREQ != 72000000UL 00043 /* Avoid errors on nightly test */ 00044 #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST) 00045 #warning Clock registers set for 72MHz operation, revise following code if you want a different clock. 00046 #endif 00047 #endif 00048 00049 /* 00050 * With a 12MHz cristal, master clock is: 00051 * (((2 * 12 * (PLL_MUL_VAL + 1)) / (PLL_DIV_VAL + 1)) / (LPC2_CPUCLOCK_DIV + 1))= 72MHz 00052 */ 00053 #define PLL_MUL_VAL 11 00054 #define PLL_DIV_VAL 0 00055 #define LPC2_CPUCLOCK_DIV 3 00056 00057 00058 /* PLL feed sequence */ 00059 #define PLL_FEED_SEQ() ATOMIC(PLLFEED = 0xAA; PLLFEED = 0x55;) 00060 00061 static void configurePll(void) 00062 { 00063 /* Disconnect and disable the PLL, if already active */ 00064 if (PLLSTAT & (1 << 25)) 00065 { 00066 /* Disconnect PLL, but leave it enabled */ 00067 PLLCON = 0x01; 00068 PLL_FEED_SEQ(); 00069 /* Disable PLL */ 00070 PLLCON = 0; 00071 PLL_FEED_SEQ(); 00072 } 00073 00074 /* Enable the main oscillator and wait for it to be stable */ 00075 SCS |= (1 << 5); 00076 while (!(SCS & (1 << 6))) ; 00077 00078 /* Select the main oscillator as the PLL clock source */ 00079 CLKSRCSEL = 0x01; 00080 00081 /* Set up PLL mul and div */ 00082 PLLCFG = PLL_MUL_VAL | (PLL_DIV_VAL << 16); 00083 PLL_FEED_SEQ(); 00084 00085 /* Enable PLL, disconnected */ 00086 PLLCON = 0x01; 00087 PLL_FEED_SEQ(); 00088 00089 /* Set clock divider */ 00090 CCLKCFG = LPC2_CPUCLOCK_DIV; 00091 00092 /* Wait for the PLL to lock */ 00093 while (!(PLLSTAT & (1 << 26))) ; 00094 00095 /* Enable and connect the PLL */ 00096 PLLCON = 0x03; 00097 PLL_FEED_SEQ(); 00098 } 00099 00100 void __init1(void); 00101 00102 void __init1(void) 00103 { 00104 /* Map irq vectors to internal flash */ 00105 MEMMAP = 0x01; 00106 /* Configure PLL, switch from IRC to Main OSC */ 00107 configurePll(); 00108 00109 /* Set memory accelerator module flash timings */ 00110 #if CPU_FREQ < 20000000UL 00111 MAMTIM = 1; 00112 #elif CPU_FREQ < 40000000UL 00113 MAMTIM = 2; 00114 #elif CPU_FREQ < 60000000UL 00115 MAMTIM = 3; 00116 #else 00117 MAMTIM = 4; 00118 #endif 00119 00120 /* Memory accelerator module fully enabled */ 00121 MAMCR = 0x02; 00122 } 00123 00124 void __init2(void); 00125 00126 void __init2(void) 00127 { 00128 vic_init(); 00129 }