rtc_isr_tmr0

Real Time Clock running from ISR on TMR0

Author Eur van Andel, Copyright © 2003..2008, all rights reserved.
Adapted-by Rob Hamerling
Compiler 2.4l

Description

This Interrupt Service Routine updates the variable seconds
about once per second. The precision is 0.2 ppm, the accuracy depends
on the Xtal used.


Sources

http://www.romanblack.com/one_sec.htm
         http://en.wikipedia.org/wiki/Bresenham%27s_line_algorithm


Notes

This is the Bresenham Line Algorithm, invented at IBM in 1962,
which gets an accurate end result by summing the small errors resulting of
taking discrete steps and correcting when the error gets too large. This
means that individual second lengths may show some jitter, but that long-term
timekeeping is accurate. Original assembler by Roman Black.
.
At 20 MHz, so 200ns/clock, so 5 000 000 clocks/second
Rhe RTC has three bytes: bres_hi, bres_mid, bres_lo
timer 0 runs on internal clock speed and interrupts on overflow
every timer 0 interrupt decreases bres_mid by one.
The  5 000 000 value is added when bres_hi en bres_mid are zero
note that remainder is added to bres_lo, which can overflow in bres_mid
this keeps clock count accurate, although interrupts happen every 256 clock
counts the ISR subtracts 1 from the mid byte. It first checks
the mid byte for zero and borrows a bit from bres_hi if needed.
.
Required PIC settings: T0CON_PSA = 1
                       T0CON_PS = 0
                       T0CON_T0CS = 0   -- Timer0 on instruction cycle clock


Dependencies

No dependency found



Summary

Global variables/contants

Procedures

Functions


API details

Global variables/contants

Procedures

  • RTC()

    No documentation found

Functions


Related samples

Here are the list of samples which use this library:

16f876a16f876a_rtc_lcd.jal
16f876a16f876a_rtc_timeset.jal
16f877a16f877a_rtc_timeset.jal
16f877a16f877a_rtc_lcd.jal
16f88616f886_rtc_lcd_20mhz.jal
16f88616f886_rtc_lcd_4mhz.jal
16f88616f886_rtc_lcd_125khz.jal