Author | Joep Suijs, Copyright © 2014 .. 2014 Joep Suijs |
Adapted-by | |
Compiler | >=2.4q2 |
Control of 74595 shift register . Setup: alias sr_scl is pin_d2 ; SRCK (serial clock, rising egde) alias sr_g is pin_d3 ; G (output enable, low = enable) alias sr_sda is pin_d1 ; SER_IN / DS alias sr_rck is pin_d3 ; RCK (parallel clock / load, rising edge) include shift_register_74595 sr_output_enable(1) ; activate shift register outputs -- Use: set one output of each shift register sr_write(data) ; data for 74595 - end of chain sw_write for all intermediate 74595 here sr_write(data) ; data for 74595 #1 (directly connected to PIC) sr_commit() ; clock all data to outputs
No dependency found
sr_write(byte in data)
sr_write - write one byte of data to chip
sr_output_enable(bit in enable)
sr_enable - enable / disable parallel outputs of shift register
sr_commit()
sr_commit - commit (activate) previous provided data Note: the RCK pin is set to low in the write() procedure, as a preperation for the commit.
12f683 | 12f683_sr_74595.jal |
16f648a | 16f648a_sr_74595.jal |
16f723 | 16f723_sr_74595.jal |
16f73 | 16f73_sr_74595.jal |
16f877 | 16f877_sr_74595.jal |
16f877a | 16f877a_sr_74595.jal |
16f88 | 16f88_sr_74595.jal |
18f2450 | 18f2450_sr_74595.jal |
18f2520 | 18f2520_sr_74595.jal |
18f2550 | 18f2550_sr_74595.jal |
18f2620 | 18f2620_sr_74595.jal |
18f452 | 18f452_sr_74595.jal |
18f4550 | 18f4550_sr_74595.jal |
18f4620 | 18f4620_sr_74595.jal |
18f67j50 | 18f67j50_sr_74595.jal |