NIIETCM4 PD  v0.9.0
Драйвер периферии для микроконтроллеров на базе ядра ARM Cortex-M4
niietcm4_dma.h
См. документацию.
1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __NIIETCM4_DMA_H
31 #define __NIIETCM4_DMA_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "niietcm4.h"
39 
57 #define CHANNEL_CFG_CYCLE_CTRL_Pos 0
58 #define CHANNEL_CFG_NEXT_USEBURST_Pos 3
59 #define CHANNEL_CFG_N_MINUS_1_Pos 4
60 #define CHANNEL_CFG_R_POWER_Pos 14
61 #define CHANNEL_CFG_SRC_PROT_CTRL_Pos 18
62 #define CHANNEL_CFG_DST_PROT_CTRL_Pos 21
63 #define CHANNEL_CFG_SRC_SIZE_Pos 24
64 #define CHANNEL_CFG_SRC_INC_Pos 26
65 #define CHANNEL_CFG_DST_SIZE_Pos 28
66 #define CHANNEL_CFG_DST_INC_Pos 30
68 #define CHANNEL_CFG_CYCLE_CTRL_Msk ((uint32_t)0x00000007)
69 #define CHANNEL_CFG_NEXT_USEBURST_Msk ((uint32_t)0x00000008)
70 #define CHANNEL_CFG_N_MINUS_1_Msk ((uint32_t)0x00003FF0)
71 #define CHANNEL_CFG_R_POWER_Msk ((uint32_t)0x0003C000)
72 #define CHANNEL_CFG_SRC_PROT_CTRL_Msk ((uint32_t)0x001C0000)
73 #define CHANNEL_CFG_DST_PROT_CTRL_Msk ((uint32_t)0x00E00000)
74 #define CHANNEL_CFG_SRC_SIZE_Msk ((uint32_t)0x03000000)
75 #define CHANNEL_CFG_SRC_INC_Msk ((uint32_t)0x0C000000)
76 #define CHANNEL_CFG_DST_SIZE_Msk ((uint32_t)0x30000000)
77 #define CHANNEL_CFG_DST_INC_Msk ((uint32_t)0xC0000000)
87 #define DMA_Channel_All ((uint32_t)0x00FFFFFF)
93 #define DMA_Channel_0 ((uint32_t)0x00000001)
94 #define DMA_Channel_1 ((uint32_t)0x00000002)
95 #define DMA_Channel_2 ((uint32_t)0x00000004)
96 #define DMA_Channel_3 ((uint32_t)0x00000008)
97 #define DMA_Channel_4 ((uint32_t)0x00000010)
98 #define DMA_Channel_5 ((uint32_t)0x00000020)
99 #define DMA_Channel_6 ((uint32_t)0x00000040)
100 #define DMA_Channel_7 ((uint32_t)0x00000080)
101 #define DMA_Channel_8 ((uint32_t)0x00000100)
102 #define DMA_Channel_9 ((uint32_t)0x00000200)
103 #define DMA_Channel_10 ((uint32_t)0x00000400)
104 #define DMA_Channel_11 ((uint32_t)0x00000800)
105 #define DMA_Channel_12 ((uint32_t)0x00001000)
106 #define DMA_Channel_13 ((uint32_t)0x00002000)
107 #define DMA_Channel_14 ((uint32_t)0x00004000)
108 #define DMA_Channel_15 ((uint32_t)0x00008000)
109 #define DMA_Channel_16 ((uint32_t)0x00010000)
110 #define DMA_Channel_17 ((uint32_t)0x00020000)
111 #define DMA_Channel_18 ((uint32_t)0x00040000)
112 #define DMA_Channel_19 ((uint32_t)0x00080000)
113 #define DMA_Channel_20 ((uint32_t)0x00100000)
114 #define DMA_Channel_21 ((uint32_t)0x00200000)
115 #define DMA_Channel_22 ((uint32_t)0x00400000)
116 #define DMA_Channel_23 ((uint32_t)0x00800000)
126 #define DMA_Channel_UART0_TX DMA_Channel_0
127 #define DMA_Channel_UART1_TX DMA_Channel_1
128 #define DMA_Channel_UART2_TX DMA_Channel_2
129 #define DMA_Channel_UART3_TX DMA_Channel_3
130 #define DMA_Channel_UART0_RX DMA_Channel_4
131 #define DMA_Channel_UART1_RX DMA_Channel_5
132 #define DMA_Channel_UART2_RX DMA_Channel_6
133 #define DMA_Channel_UART3_RX DMA_Channel_7
134 #define DMA_Channel_ADCSEQ0 DMA_Channel_8
135 #define DMA_Channel_ADCSEQ1 DMA_Channel_9
136 #define DMA_Channel_ADCSEQ2 DMA_Channel_10
137 #define DMA_Channel_ADCSEQ3 DMA_Channel_11
138 #define DMA_Channel_ADCSEQ4 DMA_Channel_12
139 #define DMA_Channel_ADCSEQ5 DMA_Channel_13
140 #define DMA_Channel_ADCSEQ6 DMA_Channel_14
141 #define DMA_Channel_ADCSEQ7 DMA_Channel_15
142 #define DMA_Channel_SPI0_TX DMA_Channel_16
143 #define DMA_Channel_SPI1_TX DMA_Channel_17
144 #define DMA_Channel_SPI2_TX DMA_Channel_18
145 #define DMA_Channel_SPI3_TX DMA_Channel_19
146 #define DMA_Channel_SPI0_RX DMA_Channel_20
147 #define DMA_Channel_SPI1_RX DMA_Channel_21
148 #define DMA_Channel_SPI2_RX DMA_Channel_22
149 #define DMA_Channel_SPI3_RX DMA_Channel_23
159 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) != (uint32_t)0x000000) && (((CHANNEL) & (uint32_t)0xFF000000) == ((uint32_t)0x0000)))
160 
161 
166 #define IS_GET_DMA_CHANNEL(CHANNEL) (((CHANNEL) == (DMA_Channel_0)) || \
167  ((CHANNEL) == (DMA_Channel_1)) || \
168  ((CHANNEL) == (DMA_Channel_2)) || \
169  ((CHANNEL) == (DMA_Channel_3)) || \
170  ((CHANNEL) == (DMA_Channel_4)) || \
171  ((CHANNEL) == (DMA_Channel_5)) || \
172  ((CHANNEL) == (DMA_Channel_6)) || \
173  ((CHANNEL) == (DMA_Channel_7)) || \
174  ((CHANNEL) == (DMA_Channel_8)) || \
175  ((CHANNEL) == (DMA_Channel_9)) || \
176  ((CHANNEL) == (DMA_Channel_10)) || \
177  ((CHANNEL) == (DMA_Channel_11)) || \
178  ((CHANNEL) == (DMA_Channel_12)) || \
179  ((CHANNEL) == (DMA_Channel_13)) || \
180  ((CHANNEL) == (DMA_Channel_14)) || \
181  ((CHANNEL) == (DMA_Channel_15)) || \
182  ((CHANNEL) == (DMA_Channel_16)) || \
183  ((CHANNEL) == (DMA_Channel_17)) || \
184  ((CHANNEL) == (DMA_Channel_18)) || \
185  ((CHANNEL) == (DMA_Channel_10)) || \
186  ((CHANNEL) == (DMA_Channel_20)) || \
187  ((CHANNEL) == (DMA_Channel_21)) || \
188  ((CHANNEL) == (DMA_Channel_22)) || \
189  ((CHANNEL) == (DMA_Channel_23)))
190 
207 typedef struct {
208  uint32_t CYCLE_CTRL :3;
209  uint32_t NEXT_USEBURST :1;
210  uint32_t N_MINUS_1 :10;
211  uint32_t R_POWER :4;
212  uint32_t SRC_PROT_PRIVILEGED :1;
213  uint32_t SRC_PROT_BUFFERABLE :1;
214  uint32_t SRC_PROT_CACHEABLE :1;
215  uint32_t DST_PROT_PRIVILEGED :1;
216  uint32_t DST_PROT_BUFFERABLE :1;
217  uint32_t DST_PROT_CACHEABLE :1;
218  uint32_t SRC_SIZE :2;
219  uint32_t SRC_INC :2;
220  uint32_t DST_SIZE :2;
221  uint32_t DST_INC :2;
223 
228 typedef struct
229 {
230  uint32_t SRC_DATA_END;
231  uint32_t DST_DATA_END;
232  union
233  {
234  uint32_t CHANNEL_CFG;
236  };
237  uint32_t RESERVED;
239 
244 typedef struct
245 {
248 
256 typedef struct
257 {
259  uint32_t RESERVED0[32];
261  uint32_t RESERVED1[32];
263 
268 typedef enum
269 {
279 
284 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Disable) || \
285  ((MODE) == DMA_Mode_Basic) || \
286  ((MODE) == DMA_Mode_AutoReq) || \
287  ((MODE) == DMA_Mode_PingPong) || \
288  ((MODE) == DMA_Mode_PrmMemScatGath) || \
289  ((MODE) == DMA_Mode_AltMemScatGath) || \
290  ((MODE) == DMA_Mode_PrmPeriphScatGath) || \
291  ((MODE) == DMA_Mode_AltPeriphScatGath))
292 
297 typedef enum
298 {
311 
316 #define IS_DMA_ARBITRATION_RATE(ARBITRATION_RATE) (((ARBITRATION_RATE) == DMA_ArbitrationRate_1) || \
317  ((ARBITRATION_RATE) == DMA_ArbitrationRate_2) || \
318  ((ARBITRATION_RATE) == DMA_ArbitrationRate_4) || \
319  ((ARBITRATION_RATE) == DMA_ArbitrationRate_8) || \
320  ((ARBITRATION_RATE) == DMA_ArbitrationRate_16) || \
321  ((ARBITRATION_RATE) == DMA_ArbitrationRate_32) || \
322  ((ARBITRATION_RATE) == DMA_ArbitrationRate_64) || \
323  ((ARBITRATION_RATE) == DMA_ArbitrationRate_128) || \
324  ((ARBITRATION_RATE) == DMA_ArbitrationRate_256) || \
325  ((ARBITRATION_RATE) == DMA_ArbitrationRate_512) || \
326  ((ARBITRATION_RATE) == DMA_ArbitrationRate_1024))
327 
332 typedef struct
333 {
338 
343 typedef enum
344 {
349 
354 #define IS_DMA_DATA_SIZE(DATA_SIZE) (((DATA_SIZE) == DMA_DataSize_8) || \
355  ((DATA_SIZE) == DMA_DataSize_16) || \
356  ((DATA_SIZE) == DMA_DataSize_32))
357 
362 typedef enum
363 {
369 
374 #define IS_DMA_DATA_INC(DATA_INC) (((DATA_INC) == DMA_DataInc_8) || \
375  ((DATA_INC) == DMA_DataInc_16) || \
376  ((DATA_INC) == DMA_DataInc_32) || \
377  ((DATA_INC) == DMA_DataInc_Disable))
378 
383 typedef struct
384 {
385  uint32_t *DMA_SrcDataEndPtr;
386  uint32_t *DMA_DstDataEndPtr;
408 
413 #define IS_DMA_TRANSFERS_TOTAL(TRANSFERS_TOTAL) (((TRANSFERS_TOTAL) <= ((uint32_t)1024)) && ((TRANSFERS_TOTAL) >= ((uint32_t)1)))
414 
419 typedef struct
420 {
421  uint32_t DMA_Channel;
435 
440 typedef enum
441 {
454 
459 #define IS_DMA_STATE(STATE) (((STATE) == DMA_State_Free) || \
460  ((STATE) == DMA_State_ReadConfigData) || \
461  ((STATE) == DMA_State_ReadSrcDataEndPtr) || \
462  ((STATE) == DMA_State_ReadDstDataEndPtr) || \
463  ((STATE) == DMA_State_ReadSrcData) || \
464  ((STATE) == DMA_State_WriteDstData) || \
465  ((STATE) == DMA_State_WaitReq) || \
466  ((STATE) == DMA_State_Pause) || \
467  ((STATE) == DMA_State_Done) || \
468  ((STATE) == DMA_State_PeriphScatGath))
469 
483 void DMA_ChannelDeInit(DMA_Channel_TypeDef* DMA_Channel);
484 void DMA_ChannelInit(DMA_Channel_TypeDef* DMA_Channel, DMA_ChannelInit_TypeDef* DMA_ChannelInitStruct);
485 void DMA_ChannelStructInit(DMA_ChannelInit_TypeDef* DMA_ChannelInitStruct);
486 
495 void DMA_DeInit();
496 void DMA_Init(DMA_Init_TypeDef* DMA_InitStruct);
497 void DMA_StructInit(DMA_Init_TypeDef* DMA_InitStruct);
498 
507 void DMA_BasePtrConfig(uint32_t BasePtr);
508 void DMA_ProtectionConfig(DMA_Protect_TypeDef *DMA_Protection);
510 void DMA_SWRequestCmd(uint32_t DMA_Channel);
511 void DMA_UseBurstCmd(uint32_t DMA_Channel, FunctionalState State);
512 void DMA_ReqMaskCmd(uint32_t DMA_Channel, FunctionalState State);
513 void DMA_ChannelEnableCmd(uint32_t DMA_Channel, FunctionalState State);
514 void DMA_PrmAltCmd(uint32_t DMA_Channel, FunctionalState State);
515 void DMA_HighPriorityCmd(uint32_t DMA_Channel, FunctionalState State);
516 
528 FunctionalState DMA_WaitOnReqStatus(uint32_t DMA_Channel);
530 void DMA_ClearErrorStatus();
531 
540 #ifdef __cplusplus
541 }
542 #endif
543 
544 #endif /* __NIIETCM4_DMA_H */
545 
554 /******************* (C) COPYRIGHT 2015 NIIET *****END OF FILE****/
FunctionalState DMA_ReqMask
Definition: niietcm4_dma.h:426
DMA_Protect_TypeDef DMA_SrcProtect
Definition: niietcm4_dma.h:395
Защита шины при чтении из источника или записи в приемник через DMA.
Definition: niietcm4_dma.h:332
uint32_t * DMA_SrcDataEndPtr
Definition: niietcm4_dma.h:385
void DMA_Init(DMA_Init_TypeDef *DMA_InitStruct)
Инициализация контроллера DMA.
Definition: niietcm4_dma.c:195
DMA_Mode_TypeDef DMA_Mode
Definition: niietcm4_dma.h:387
void DMA_UseBurstCmd(uint32_t DMA_Channel, FunctionalState State)
Установка пакетного обмена каналов DMA.
Definition: niietcm4_dma.c:324
Тип, описывающий структуру канала DMA.
Definition: niietcm4_dma.h:228
FunctionalState
Описывает логическое состояние периферии. Используется для операций включения/выключения периферийных...
Definition: niietcm4.h:157
void DMA_ReqMaskCmd(uint32_t DMA_Channel, FunctionalState State)
Маскирование каналов DMA.
Definition: niietcm4_dma.c:349
DMA_State_TypeDef
Возможные состояния конечного автомата управления контроллером DMA.
Definition: niietcm4_dma.h:440
FunctionalState DMA_PrmAlt
Definition: niietcm4_dma.h:428
void DMA_ChannelStructInit(DMA_ChannelInit_TypeDef *DMA_ChannelInitStruct)
Заполнение каждого члена структуры DMA_ChannelInitStruct значениями по умолчанию. ...
Definition: niietcm4_dma.c:146
uint32_t * DMA_DstDataEndPtr
Definition: niietcm4_dma.h:386
FunctionalState PRIVELGED
Definition: niietcm4_dma.h:334
DMA_ConfigStruct_TypeDef ALT_DATA
Definition: niietcm4_dma.h:260
void DMA_SWRequestCmd(uint32_t DMA_Channel)
Программный запрос на осуществление передач DMA по выбранным каналам.
Definition: niietcm4_dma.c:308
DMA_Mode_TypeDef
Выбор режима работы DMA.
Definition: niietcm4_dma.h:268
FunctionalState DMA_WaitOnReqStatus(uint32_t DMA_Channel)
Показывает поддерживает ли канал одиночные SREQ запросы.
Definition: niietcm4_dma.c:478
void DMA_ChannelInit(DMA_Channel_TypeDef *DMA_Channel, DMA_ChannelInit_TypeDef *DMA_ChannelInitStruct)
Инициализация канала DMA.
Definition: niietcm4_dma.c:102
DMA_Protect_TypeDef DMA_Protection
Definition: niietcm4_dma.h:423
DMA_DataSize_TypeDef
Разрядность данных источника или приемника
Definition: niietcm4_dma.h:343
void DMA_ChannelEnableCmd(uint32_t DMA_Channel, FunctionalState State)
Активация каналов DMA.
Definition: niietcm4_dma.c:373
Битовый доступ к регистру CHANNEL_CFG в DMA_Channel_TypeDef.
Definition: niietcm4_dma.h:207
void DMA_HighPriorityCmd(uint32_t DMA_Channel, FunctionalState State)
Установка высокого приоритета каналов DMA.
Definition: niietcm4_dma.c:421
DMA_ArbitrationRate_TypeDef DMA_ArbitrationRate
Definition: niietcm4_dma.h:393
void DMA_ChannelDeInit(DMA_Channel_TypeDef *DMA_Channel)
Деинициализация канала DMA.
Definition: niietcm4_dma.c:87
DMA_DataInc_TypeDef DMA_DstDataInc
Definition: niietcm4_dma.h:405
uint32_t DMA_Channel
Definition: niietcm4_dma.h:421
FunctionalState DMA_UseBurst
Definition: niietcm4_dma.h:424
Совокупность из основной и управляющей структур DMA. Общий размер 1 кБ.
Definition: niietcm4_dma.h:256
FunctionalState CACHEABLE
Definition: niietcm4_dma.h:336
_CHANNEL_CFG_bits CHANNEL_CFG_bit
Definition: niietcm4_dma.h:235
void DMA_ClearErrorStatus()
Сброс флага ошибки на шине.
Definition: niietcm4_dma.c:524
DMA_Protect_TypeDef DMA_DstProtect
Definition: niietcm4_dma.h:397
OperationStatus
Описывает коды возврата для функций при выполнении какой-либо операции.
Definition: niietcm4.h:173
void DMA_PrmAltCmd(uint32_t DMA_Channel, FunctionalState State)
Установка первичной/альтернативной управляющей структуры каналов DMA.
Definition: niietcm4_dma.c:397
void DMA_BasePtrConfig(uint32_t BasePtr)
Установка базового адреса управляющих каналов.
Definition: niietcm4_dma.c:231
FunctionalState DMA_MasterEnableStatus()
Состояние контроллера DMA.
Definition: niietcm4_dma.c:455
DMA_DataSize_TypeDef DMA_DstDataSize
Definition: niietcm4_dma.h:401
Это главный заголовочный файл драйвера, обычно включаемый в main.c.
void DMA_ProtectionConfig(DMA_Protect_TypeDef *DMA_Protection)
Управление защитой шины при обращении DMA к управляющим данным.
Definition: niietcm4_dma.c:243
OperationStatus DMA_ErrorStatus()
Показывает наличие ошибки на шине.
Definition: niietcm4_dma.c:503
DMA_DataSize_TypeDef DMA_SrcDataSize
Definition: niietcm4_dma.h:399
DMA_DataInc_TypeDef DMA_SrcDataInc
Definition: niietcm4_dma.h:403
DMA_ArbitrationRate_TypeDef
Выбор количества передач до выполнения переарбитрации.
Definition: niietcm4_dma.h:297
FunctionalState DMA_HighPriority
Definition: niietcm4_dma.h:430
FunctionalState BUFFERABLE
Definition: niietcm4_dma.h:335
Структура инициализации канала DMA.
Definition: niietcm4_dma.h:383
FunctionalState DMA_NextUseburst
Definition: niietcm4_dma.h:389
void DMA_DeInit()
Деинициализация контроллера DMA.
Definition: niietcm4_dma.c:174
void DMA_StructInit(DMA_Init_TypeDef *DMA_InitStruct)
Заполнение каждого члена структуры DMA_InitStruct значениями по умолчанию.
Definition: niietcm4_dma.c:212
void DMA_MasterEnableCmd(FunctionalState State)
Разрешения работы контроллера DMA.
Definition: niietcm4_dma.c:287
DMA_State_TypeDef DMA_StateStatus()
Доступ к текущему конечного автомата контроллера DMA.
Definition: niietcm4_dma.c:441
Структура инициализации контроллера DMA.
Definition: niietcm4_dma.h:419
DMA_ConfigStruct_TypeDef PRM_DATA
Definition: niietcm4_dma.h:258
DMA_DataInc_TypeDef
Шаг инкремента адреса источника при чтении или приемника при записи
Definition: niietcm4_dma.h:362
FunctionalState DMA_ChannelEnable
Definition: niietcm4_dma.h:432
Управляющая структура данных DMA.
Definition: niietcm4_dma.h:244