NIIETCM4 PD  v0.9.0
Драйвер периферии для микроконтроллеров на базе ядра ARM Cortex-M4
niietcm4_dma.c
См. документацию.
1 
29 /* Includes ------------------------------------------------------------------*/
30 #include "niietcm4_dma.h"
31 
88 {
89  DMA_Channel->SRC_DATA_END = 0;
90  DMA_Channel->DST_DATA_END = 0;
91  DMA_Channel->CHANNEL_CFG = 0;
92 }
93 
102 void DMA_ChannelInit(DMA_Channel_TypeDef* DMA_Channel, DMA_ChannelInit_TypeDef* DMA_ChannelInitStruct)
103 {
104  assert_param(IS_DMA_MODE(DMA_ChannelInitStruct->DMA_Mode));
105  assert_param(IS_DMA_ARBITRATION_RATE(DMA_ChannelInitStruct->DMA_ArbitrationRate));
106  assert_param(IS_DMA_DATA_INC(DMA_ChannelInitStruct->DMA_DstDataInc));
107  assert_param(IS_DMA_DATA_INC(DMA_ChannelInitStruct->DMA_SrcDataInc));
108  assert_param(IS_DMA_DATA_SIZE(DMA_ChannelInitStruct->DMA_DstDataSize));
109  assert_param(IS_DMA_DATA_SIZE(DMA_ChannelInitStruct->DMA_SrcDataSize));
110  assert_param(IS_DMA_TRANSFERS_TOTAL(DMA_ChannelInitStruct->DMA_TransfersTotal));
111  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_DstProtect.BUFFERABLE));
112  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_DstProtect.CACHEABLE));
113  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_DstProtect.PRIVELGED));
114  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_SrcProtect.BUFFERABLE));
115  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_SrcProtect.CACHEABLE));
116  assert_param(IS_FUNCTIONAL_STATE(DMA_ChannelInitStruct->DMA_SrcProtect.PRIVELGED));
117 
118  /* источник */
119  DMA_Channel->SRC_DATA_END = (uint32_t)DMA_ChannelInitStruct->DMA_SrcDataEndPtr;
120  DMA_Channel->CHANNEL_CFG_bit.SRC_SIZE = DMA_ChannelInitStruct->DMA_SrcDataSize;
121  DMA_Channel->CHANNEL_CFG_bit.SRC_INC = DMA_ChannelInitStruct->DMA_SrcDataInc;
122  DMA_Channel->CHANNEL_CFG_bit.SRC_PROT_BUFFERABLE = DMA_ChannelInitStruct->DMA_SrcProtect.BUFFERABLE;
123  DMA_Channel->CHANNEL_CFG_bit.SRC_PROT_PRIVILEGED = DMA_ChannelInitStruct->DMA_SrcProtect.PRIVELGED;
124  DMA_Channel->CHANNEL_CFG_bit.SRC_PROT_CACHEABLE = DMA_ChannelInitStruct->DMA_SrcProtect.CACHEABLE;
125  /* приемник */
126  DMA_Channel->DST_DATA_END = (uint32_t)DMA_ChannelInitStruct->DMA_DstDataEndPtr;
127  DMA_Channel->CHANNEL_CFG_bit.DST_SIZE = DMA_ChannelInitStruct->DMA_DstDataSize;
128  DMA_Channel->CHANNEL_CFG_bit.DST_INC = DMA_ChannelInitStruct->DMA_DstDataInc;
129  DMA_Channel->CHANNEL_CFG_bit.DST_PROT_BUFFERABLE = DMA_ChannelInitStruct->DMA_DstProtect.BUFFERABLE;
130  DMA_Channel->CHANNEL_CFG_bit.DST_PROT_PRIVILEGED = DMA_ChannelInitStruct->DMA_DstProtect.PRIVELGED;
131  DMA_Channel->CHANNEL_CFG_bit.DST_PROT_CACHEABLE = DMA_ChannelInitStruct->DMA_DstProtect.CACHEABLE;
132  /* общее */
133  DMA_Channel->CHANNEL_CFG_bit.NEXT_USEBURST = DMA_ChannelInitStruct->DMA_NextUseburst;
134  DMA_Channel->CHANNEL_CFG_bit.R_POWER = DMA_ChannelInitStruct->DMA_ArbitrationRate;
135  DMA_Channel->CHANNEL_CFG_bit.N_MINUS_1 = DMA_ChannelInitStruct->DMA_TransfersTotal - 1;
136  DMA_Channel->CHANNEL_CFG_bit.CYCLE_CTRL = DMA_ChannelInitStruct->DMA_Mode;
137 }
138 
146 void DMA_ChannelStructInit(DMA_ChannelInit_TypeDef* DMA_ChannelInitStruct)
147 {
148  /* источник */
149  DMA_ChannelInitStruct->DMA_SrcDataEndPtr = (uint32_t *)0x00000000;
150  DMA_ChannelInitStruct->DMA_SrcDataSize = DMA_DataSize_8;
151  DMA_ChannelInitStruct->DMA_SrcDataInc = DMA_DataInc_Disable;
152  DMA_ChannelInitStruct->DMA_SrcProtect.BUFFERABLE = DISABLE;
153  DMA_ChannelInitStruct->DMA_SrcProtect.PRIVELGED = DISABLE;
154  DMA_ChannelInitStruct->DMA_SrcProtect.CACHEABLE = DISABLE;
155  /* приемник */
156  DMA_ChannelInitStruct->DMA_DstDataEndPtr = (uint32_t *)0x00000000;
157  DMA_ChannelInitStruct->DMA_DstDataSize = DMA_DataSize_8;
158  DMA_ChannelInitStruct->DMA_DstDataInc = DMA_DataInc_Disable;
159  DMA_ChannelInitStruct->DMA_DstProtect.BUFFERABLE = DISABLE;
160  DMA_ChannelInitStruct->DMA_DstProtect.PRIVELGED = DISABLE;
161  DMA_ChannelInitStruct->DMA_DstProtect.CACHEABLE = DISABLE;
162  /* общее */
163  DMA_ChannelInitStruct->DMA_NextUseburst = DISABLE;
164  DMA_ChannelInitStruct->DMA_ArbitrationRate = DMA_ArbitrationRate_1;
165  DMA_ChannelInitStruct->DMA_TransfersTotal = 1;
166  DMA_ChannelInitStruct->DMA_Mode = DMA_Mode_Disable;
167 }
168 
175 {
176  NT_DMA->CFG = 0;
177  NT_DMA->CTRL_BASE_PTR = 0;
178  NT_DMA->CHNL_ENABLE_CLR = 0xFFFFFFFF;
179  NT_DMA->CHNL_PRIORITY_CLR = 0xFFFFFFFF;
180  NT_DMA->CHNL_PRI_ALT_CLR = 0xFFFFFFFF;
181  NT_DMA->CHNL_REQ_MASK_CLR = 0xFFFFFFFF;
182  NT_DMA->CHNL_USEBURST_CLR = 0xFFFFFFFF;
183 }
184 
195 void DMA_Init(DMA_Init_TypeDef* DMA_InitStruct)
196 {
197  DMA_ProtectionConfig(&(DMA_InitStruct->DMA_Protection));
198  DMA_UseBurstCmd(DMA_InitStruct->DMA_Channel, DMA_InitStruct->DMA_UseBurst);
199  DMA_PrmAltCmd(DMA_InitStruct->DMA_Channel, DMA_InitStruct->DMA_PrmAlt);
200  DMA_HighPriorityCmd(DMA_InitStruct->DMA_Channel, DMA_InitStruct->DMA_HighPriority);
201  DMA_ReqMaskCmd(DMA_InitStruct->DMA_Channel, DMA_InitStruct->DMA_ReqMask);
202  DMA_ChannelEnableCmd(DMA_InitStruct->DMA_Channel, DMA_InitStruct->DMA_ChannelEnable);
203 }
204 
212 void DMA_StructInit(DMA_Init_TypeDef* DMA_InitStruct)
213 {
214  DMA_InitStruct->DMA_Channel = 0xFFFFFF;
215  DMA_InitStruct->DMA_ChannelEnable = DISABLE;
216  DMA_InitStruct->DMA_HighPriority = DISABLE;
217  DMA_InitStruct->DMA_PrmAlt = DISABLE;
218  DMA_InitStruct->DMA_ReqMask = DISABLE;
219  DMA_InitStruct->DMA_UseBurst = DISABLE;
220  DMA_InitStruct->DMA_Protection.BUFFERABLE = DISABLE;
221  DMA_InitStruct->DMA_Protection.CACHEABLE = DISABLE;
222  DMA_InitStruct->DMA_Protection.PRIVELGED = DISABLE;
223 }
224 
231 void DMA_BasePtrConfig(uint32_t BasePtr)
232 {
233  NT_DMA->CTRL_BASE_PTR = BasePtr;
234 }
235 
244 {
245  assert_param(IS_FUNCTIONAL_STATE(DMA_Protection->BUFFERABLE));
246  assert_param(IS_FUNCTIONAL_STATE(DMA_Protection->CACHEABLE));
247  assert_param(IS_FUNCTIONAL_STATE(DMA_Protection->PRIVELGED));
248 
249  if (DMA_Protection->PRIVELGED == ENABLE)
250  {
251  NT_DMA->CFG_bit.CHNL_PROT_CTRL |= (1<<0);
252  }
253  else /* DMA_Protection->PRIVELGED == DISABLE */
254  {
255  NT_DMA->CFG_bit.CHNL_PROT_CTRL &= ~(1<<0);
256  }
257 
258  if (DMA_Protection->BUFFERABLE == ENABLE)
259  {
260  NT_DMA->CFG_bit.CHNL_PROT_CTRL |= (1<<1);
261  }
262  else /* DMA_Protection->BUFFERABLE == DISABLE */
263  {
264  NT_DMA->CFG_bit.CHNL_PROT_CTRL &= ~(1<<1);
265  }
266 
267  if (DMA_Protection->CACHEABLE == ENABLE)
268  {
269  NT_DMA->CFG_bit.CHNL_PROT_CTRL |= (1<<2);
270  }
271  else /* DMA_Protection->CACHEABLE == DISABLE */
272  {
273  NT_DMA->CFG_bit.CHNL_PROT_CTRL &= ~(1<<2);
274  }
275 }
276 
288 {
289  assert_param(IS_FUNCTIONAL_STATE(State));
290 
291  if (State == ENABLE)
292  {
293  NT_DMA->CFG_bit.MASTER_EN = 1;
294  }
295  else /* State == DISABLE */
296  {
297  NT_DMA->CFG_bit.MASTER_EN = 0;
298  }
299 }
300 
308 void DMA_SWRequestCmd(uint32_t DMA_Channel)
309 {
310  assert_param(IS_DMA_CHANNEL(DMA_Channel));
311 
312  NT_DMA->CHNL_SW_REQUEST = DMA_Channel;
313 }
314 
324 void DMA_UseBurstCmd(uint32_t DMA_Channel, FunctionalState State)
325 {
326  assert_param(IS_DMA_CHANNEL(DMA_Channel));
327  assert_param(IS_FUNCTIONAL_STATE(State));
328 
329  if (State == ENABLE)
330  {
331  NT_DMA->CHNL_USEBURST_SET = DMA_Channel;
332  }
333  else /* State == DISABLE */
334  {
335  NT_DMA->CHNL_USEBURST_CLR = DMA_Channel;
336  }
337 }
338 
349 void DMA_ReqMaskCmd(uint32_t DMA_Channel, FunctionalState State)
350 {
351  assert_param(IS_DMA_CHANNEL(DMA_Channel));
352  assert_param(IS_FUNCTIONAL_STATE(State));
353 
354  if (State == ENABLE)
355  {
356  NT_DMA->CHNL_REQ_MASK_SET = DMA_Channel;
357  }
358  else /* State == DISABLE */
359  {
360  NT_DMA->CHNL_REQ_MASK_CLR = DMA_Channel;
361  }
362 }
363 
373 void DMA_ChannelEnableCmd(uint32_t DMA_Channel, FunctionalState State)
374 {
375  assert_param(IS_DMA_CHANNEL(DMA_Channel));
376  assert_param(IS_FUNCTIONAL_STATE(State));
377 
378  if (State == ENABLE)
379  {
380  NT_DMA->CHNL_ENABLE_SET = DMA_Channel;
381  }
382  else /* State == DISABLE */
383  {
384  NT_DMA->CHNL_ENABLE_CLR = DMA_Channel;
385  }
386 }
387 
397 void DMA_PrmAltCmd(uint32_t DMA_Channel, FunctionalState State)
398 {
399  assert_param(IS_DMA_CHANNEL(DMA_Channel));
400  assert_param(IS_FUNCTIONAL_STATE(State));
401 
402  if (State == ENABLE)
403  {
404  NT_DMA->CHNL_PRI_ALT_SET = DMA_Channel;
405  }
406  else /* State == DISABLE */
407  {
408  NT_DMA->CHNL_PRI_ALT_CLR = DMA_Channel;
409  }
410 }
411 
421 void DMA_HighPriorityCmd(uint32_t DMA_Channel, FunctionalState State)
422 {
423  assert_param(IS_DMA_CHANNEL(DMA_Channel));
424  assert_param(IS_FUNCTIONAL_STATE(State));
425 
426  if (State == ENABLE)
427  {
428  NT_DMA->CHNL_PRIORITY_SET = DMA_Channel;
429  }
430  else /* State == DISABLE */
431  {
432  NT_DMA->CHNL_PRIORITY_CLR = DMA_Channel;
433  }
434 }
435 
442 {
443  DMA_State_TypeDef State;
444 
445  State = (DMA_State_TypeDef)NT_DMA->STATUS_bit.STATE;
446 
447  return State;
448 }
449 
456 {
457  FunctionalState Status;
458 
459  if (NT_DMA->STATUS_bit.MASTER_EN)
460  {
461  Status = ENABLE;
462  }
463  else
464  {
465  Status = DISABLE;
466  }
467 
468  return Status;
469 }
470 
479 {
480  FunctionalState Status;
481 
482  assert_param(IS_GET_DMA_CHANNEL(DMA_Channel));
483 
484  if (NT_DMA->WAITONREQ_STATUS & DMA_Channel)
485  {
486  Status = ENABLE;
487  }
488  else
489  {
490  Status = DISABLE;
491  }
492 
493  return Status;
494 }
495 
504 {
505  OperationStatus Status;
506 
507  if (NT_DMA->ERR_CLR)
508  {
509  Status = ERROR;
510  }
511  else
512  {
513  Status = OK;
514  }
515 
516  return Status;
517 }
518 
525 {
526  NT_DMA->ERR_CLR = 1;
527 }
528 
545 /******************* (C) COPYRIGHT 2015 NIIET *****END OF FILE****/
FunctionalState DMA_ReqMask
Definition: niietcm4_dma.h:426
void DMA_DeInit()
Деинициализация контроллера DMA.
Definition: niietcm4_dma.c:174
uint32_t DST_PROT_CACHEABLE
Definition: niietcm4_dma.h:217
void DMA_MasterEnableCmd(FunctionalState State)
Разрешения работы контроллера DMA.
Definition: niietcm4_dma.c:287
DMA_Protect_TypeDef DMA_SrcProtect
Definition: niietcm4_dma.h:395
void DMA_ProtectionConfig(DMA_Protect_TypeDef *DMA_Protection)
Управление защитой шины при обращении DMA к управляющим данным.
Definition: niietcm4_dma.c:243
Защита шины при чтении из источника или записи в приемник через DMA.
Definition: niietcm4_dma.h:332
uint32_t * DMA_SrcDataEndPtr
Definition: niietcm4_dma.h:385
void DMA_ChannelDeInit(DMA_Channel_TypeDef *DMA_Channel)
Деинициализация канала DMA.
Definition: niietcm4_dma.c:87
DMA_State_TypeDef DMA_StateStatus()
Доступ к текущему конечного автомата контроллера DMA.
Definition: niietcm4_dma.c:441
DMA_Mode_TypeDef DMA_Mode
Definition: niietcm4_dma.h:387
void DMA_BasePtrConfig(uint32_t BasePtr)
Установка базового адреса управляющих каналов.
Definition: niietcm4_dma.c:231
Тип, описывающий структуру канала DMA.
Definition: niietcm4_dma.h:228
FunctionalState
Описывает логическое состояние периферии. Используется для операций включения/выключения периферийных...
Definition: niietcm4.h:157
void DMA_ReqMaskCmd(uint32_t DMA_Channel, FunctionalState State)
Маскирование каналов DMA.
Definition: niietcm4_dma.c:349
DMA_State_TypeDef
Возможные состояния конечного автомата управления контроллером DMA.
Definition: niietcm4_dma.h:440
FunctionalState DMA_PrmAlt
Definition: niietcm4_dma.h:428
uint32_t * DMA_DstDataEndPtr
Definition: niietcm4_dma.h:386
FunctionalState PRIVELGED
Definition: niietcm4_dma.h:334
void DMA_HighPriorityCmd(uint32_t DMA_Channel, FunctionalState State)
Установка высокого приоритета каналов DMA.
Definition: niietcm4_dma.c:421
uint32_t SRC_PROT_CACHEABLE
Definition: niietcm4_dma.h:214
void DMA_ChannelEnableCmd(uint32_t DMA_Channel, FunctionalState State)
Активация каналов DMA.
Definition: niietcm4_dma.c:373
#define IS_DMA_DATA_SIZE(DATA_SIZE)
Макрос проверки аргументов типа DMA_DataSize_TypeDef.
Definition: niietcm4_dma.h:354
void DMA_Init(DMA_Init_TypeDef *DMA_InitStruct)
Инициализация контроллера DMA.
Definition: niietcm4_dma.c:195
FunctionalState DMA_WaitOnReqStatus(uint32_t DMA_Channel)
Показывает поддерживает ли канал одиночные SREQ запросы.
Definition: niietcm4_dma.c:478
DMA_Protect_TypeDef DMA_Protection
Definition: niietcm4_dma.h:423
void DMA_PrmAltCmd(uint32_t DMA_Channel, FunctionalState State)
Установка первичной/альтернативной управляющей структуры каналов DMA.
Definition: niietcm4_dma.c:397
#define IS_DMA_MODE(MODE)
Макрос проверки аргументов типа DMA_Mode_TypeDef.
Definition: niietcm4_dma.h:284
DMA_ArbitrationRate_TypeDef DMA_ArbitrationRate
Definition: niietcm4_dma.h:393
uint32_t SRC_PROT_PRIVILEGED
Definition: niietcm4_dma.h:212
FunctionalState DMA_MasterEnableStatus()
Состояние контроллера DMA.
Definition: niietcm4_dma.c:455
#define IS_DMA_ARBITRATION_RATE(ARBITRATION_RATE)
Макрос проверки аргументов типа DMA_ArbitrationRate_TypeDef.
Definition: niietcm4_dma.h:316
uint32_t SRC_PROT_BUFFERABLE
Definition: niietcm4_dma.h:213
DMA_DataInc_TypeDef DMA_DstDataInc
Definition: niietcm4_dma.h:405
uint32_t NEXT_USEBURST
Definition: niietcm4_dma.h:209
uint32_t DMA_Channel
Definition: niietcm4_dma.h:421
FunctionalState DMA_UseBurst
Definition: niietcm4_dma.h:424
#define IS_DMA_CHANNEL(CHANNEL)
Макрос проверки маски каналов на попадание в допустимый диапазон.
Definition: niietcm4_dma.h:159
FunctionalState CACHEABLE
Definition: niietcm4_dma.h:336
void DMA_StructInit(DMA_Init_TypeDef *DMA_InitStruct)
Заполнение каждого члена структуры DMA_InitStruct значениями по умолчанию.
Definition: niietcm4_dma.c:212
_CHANNEL_CFG_bits CHANNEL_CFG_bit
Definition: niietcm4_dma.h:235
DMA_Protect_TypeDef DMA_DstProtect
Definition: niietcm4_dma.h:397
OperationStatus
Описывает коды возврата для функций при выполнении какой-либо операции.
Definition: niietcm4.h:173
Файл содержит все прототипы функций для DMA.
void DMA_ChannelInit(DMA_Channel_TypeDef *DMA_Channel, DMA_ChannelInit_TypeDef *DMA_ChannelInitStruct)
Инициализация канала DMA.
Definition: niietcm4_dma.c:102
OperationStatus DMA_ErrorStatus()
Показывает наличие ошибки на шине.
Definition: niietcm4_dma.c:503
DMA_DataSize_TypeDef DMA_DstDataSize
Definition: niietcm4_dma.h:401
#define IS_FUNCTIONAL_STATE(STATE)
Макрос проверки аргументов типа FunctionalState.
Definition: niietcm4.h:167
DMA_DataSize_TypeDef DMA_SrcDataSize
Definition: niietcm4_dma.h:399
DMA_DataInc_TypeDef DMA_SrcDataInc
Definition: niietcm4_dma.h:403
void DMA_UseBurstCmd(uint32_t DMA_Channel, FunctionalState State)
Установка пакетного обмена каналов DMA.
Definition: niietcm4_dma.c:324
void DMA_ClearErrorStatus()
Сброс флага ошибки на шине.
Definition: niietcm4_dma.c:524
FunctionalState DMA_HighPriority
Definition: niietcm4_dma.h:430
void DMA_ChannelStructInit(DMA_ChannelInit_TypeDef *DMA_ChannelInitStruct)
Заполнение каждого члена структуры DMA_ChannelInitStruct значениями по умолчанию. ...
Definition: niietcm4_dma.c:146
uint32_t DST_PROT_PRIVILEGED
Definition: niietcm4_dma.h:215
FunctionalState BUFFERABLE
Definition: niietcm4_dma.h:335
Структура инициализации канала DMA.
Definition: niietcm4_dma.h:383
FunctionalState DMA_NextUseburst
Definition: niietcm4_dma.h:389
void DMA_SWRequestCmd(uint32_t DMA_Channel)
Программный запрос на осуществление передач DMA по выбранным каналам.
Definition: niietcm4_dma.c:308
#define IS_DMA_TRANSFERS_TOTAL(TRANSFERS_TOTAL)
Макрос проверки соответсвия величины DMA_TransfersTotal из DMA_ChannelInit_TypeDef разрешенному диапа...
Definition: niietcm4_dma.h:413
#define IS_GET_DMA_CHANNEL(CHANNEL)
Макрос проверки маски канала при работе с каналами по отдельности.
Definition: niietcm4_dma.h:166
Структура инициализации контроллера DMA.
Definition: niietcm4_dma.h:419
uint32_t DST_PROT_BUFFERABLE
Definition: niietcm4_dma.h:216
FunctionalState DMA_ChannelEnable
Definition: niietcm4_dma.h:432
#define IS_DMA_DATA_INC(DATA_INC)
Макрос проверки аргументов типа DMA_DataSize_TypeDef.
Definition: niietcm4_dma.h:374